SparcInstrInfo.cpp revision e87146ace88464be4ea4f8869830642c40178f1f 
1//===- SparcInstrInfo.cpp - Sparc Instruction Information -------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file was developed by the LLVM research group and is distributed under
6// the University of Illinois Open Source License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the Sparc implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "SparcInstrInfo.h"
15#include "Sparc.h"
16#include "llvm/CodeGen/MachineInstrBuilder.h"
17#include "SparcGenInstrInfo.inc"
18using namespace llvm;
19
20SparcInstrInfo::SparcInstrInfo(SparcSubtarget &ST)
21  : TargetInstrInfo(SparcInsts, sizeof(SparcInsts)/sizeof(SparcInsts[0])),
22    RI(ST) {
23}
24
25static bool isZeroImm(const MachineOperand &op) {
26  return op.isImmediate() && op.getImmedValue() == 0;
27}
28
29/// Return true if the instruction is a register to register move and
30/// leave the source and dest operands in the passed parameters.
31///
32bool SparcInstrInfo::isMoveInstr(const MachineInstr &MI,
33                                 unsigned &SrcReg, unsigned &DstReg) const {
34  // We look for 3 kinds of patterns here:
35  // or with G0 or 0
36  // add with G0 or 0
37  // fmovs or FpMOVD (pseudo double move).
38  if (MI.getOpcode() == SP::ORrr || MI.getOpcode() == SP::ADDrr) {
39    if (MI.getOperand(1).getReg() == SP::G0) {
40      DstReg = MI.getOperand(0).getReg();
41      SrcReg = MI.getOperand(2).getReg();
42      return true;
43    } else if (MI.getOperand(2).getReg() == SP::G0) {
44      DstReg = MI.getOperand(0).getReg();
45      SrcReg = MI.getOperand(1).getReg();
46      return true;
47    }
48  } else if ((MI.getOpcode() == SP::ORri || MI.getOpcode() == SP::ADDri) &&
49             isZeroImm(MI.getOperand(2)) && MI.getOperand(1).isRegister()) {
50    DstReg = MI.getOperand(0).getReg();
51    SrcReg = MI.getOperand(1).getReg();
52    return true;
53  } else if (MI.getOpcode() == SP::FMOVS || MI.getOpcode() == SP::FpMOVD ||
54             MI.getOpcode() == SP::FMOVD) {
55    SrcReg = MI.getOperand(1).getReg();
56    DstReg = MI.getOperand(0).getReg();
57    return true;
58  }
59  return false;
60}
61
62/// isLoadFromStackSlot - If the specified machine instruction is a direct
63/// load from a stack slot, return the virtual or physical register number of
64/// the destination along with the FrameIndex of the loaded stack slot.  If
65/// not, return 0.  This predicate must return 0 if the instruction has
66/// any side effects other than loading from the stack slot.
67unsigned SparcInstrInfo::isLoadFromStackSlot(MachineInstr *MI,
68                                             int &FrameIndex) const {
69  if (MI->getOpcode() == SP::LDri ||
70      MI->getOpcode() == SP::LDFri ||
71      MI->getOpcode() == SP::LDDFri) {
72    if (MI->getOperand(1).isFrameIndex() && MI->getOperand(2).isImmediate() &&
73        MI->getOperand(2).getImmedValue() == 0) {
74      FrameIndex = MI->getOperand(1).getFrameIndex();
75      return MI->getOperand(0).getReg();
76    }
77  }
78  return 0;
79}
80
81/// isStoreToStackSlot - If the specified machine instruction is a direct
82/// store to a stack slot, return the virtual or physical register number of
83/// the source reg along with the FrameIndex of the loaded stack slot.  If
84/// not, return 0.  This predicate must return 0 if the instruction has
85/// any side effects other than storing to the stack slot.
86unsigned SparcInstrInfo::isStoreToStackSlot(MachineInstr *MI,
87                                            int &FrameIndex) const {
88  if (MI->getOpcode() == SP::STri ||
89      MI->getOpcode() == SP::STFri ||
90      MI->getOpcode() == SP::STDFri) {
91    if (MI->getOperand(0).isFrameIndex() && MI->getOperand(1).isImmediate() &&
92        MI->getOperand(1).getImmedValue() == 0) {
93      FrameIndex = MI->getOperand(0).getFrameIndex();
94      return MI->getOperand(2).getReg();
95    }
96  }
97  return 0;
98}
99
100void SparcInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB,
101                                  MachineBasicBlock *FBB,
102                                  const std::vector<MachineOperand> &Cond)const{
103  // Can only insert uncond branches so far.
104  assert(Cond.empty() && !FBB && TBB && "Can only handle uncond branches!");
105  BuildMI(&MBB, SP::BA, 1).addMBB(TBB);
106}