SparcInstrInfo.td revision 1b8af84a8448b7803695f86785944fb3d0b75eb1
1//===- SparcV8Instrs.td - Target Description for SparcV8 Target -----------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the SparcV8 instructions in TableGen format. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// Instruction format superclass 16//===----------------------------------------------------------------------===// 17 18include "SparcV8InstrFormats.td" 19 20//===----------------------------------------------------------------------===// 21// Instruction Pattern Stuff 22//===----------------------------------------------------------------------===// 23 24def simm13 : PatLeaf<(imm), [{ 25 // simm13 predicate - True if the imm fits in a 13-bit sign extended field. 26 return (((int)N->getValue() << (32-13)) >> (32-13)) == (int)N->getValue(); 27}]>; 28 29def LO10 : SDNodeXForm<imm, [{ 30 return CurDAG->getTargetConstant((unsigned)N->getValue() & 1023, MVT::i32); 31}]>; 32 33def HI22 : SDNodeXForm<imm, [{ 34 // Transformation function: shift the immediate value down into the low bits. 35 return CurDAG->getTargetConstant((unsigned)N->getValue() >> 10, MVT::i32); 36}]>; 37 38def SETHIimm : PatLeaf<(imm), [{ 39 return (((unsigned)N->getValue() >> 10) << 10) == (unsigned)N->getValue(); 40}], HI22>; 41 42// Addressing modes. 43def ADDRrr : ComplexPattern<i32, 2, "SelectADDRrr", []>; 44def ADDRri : ComplexPattern<i32, 2, "SelectADDRri", []>; 45 46// Address operands 47def MEMrr : Operand<i32> { 48 let PrintMethod = "printMemOperand"; 49 let NumMIOperands = 2; 50 let MIOperandInfo = (ops IntRegs, IntRegs); 51} 52def MEMri : Operand<i32> { 53 let PrintMethod = "printMemOperand"; 54 let NumMIOperands = 2; 55 let MIOperandInfo = (ops IntRegs, i32imm); 56} 57 58// Branch targets have OtherVT type. 59def brtarget : Operand<OtherVT>; 60def calltarget : Operand<i32>; 61 62def SDTV8cmpicc : 63SDTypeProfile<1, 2, [SDTCisVT<0, FlagVT>, SDTCisInt<1>, SDTCisSameAs<1, 2>]>; 64def SDTV8cmpfcc : 65SDTypeProfile<1, 2, [SDTCisVT<0, FlagVT>, SDTCisFP<1>, SDTCisSameAs<1, 2>]>; 66def SDTV8brcc : 67SDTypeProfile<0, 3, [SDTCisVT<0, OtherVT>, SDTCisVT<1, OtherVT>, 68 SDTCisVT<2, FlagVT>]>; 69def SDTV8selectcc : 70SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, 71 SDTCisVT<3, i32>, SDTCisVT<4, FlagVT>]>; 72def SDTV8FTOI : 73SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisFP<1>]>; 74def SDTV8ITOF : 75SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f32>]>; 76 77def V8cmpicc : SDNode<"V8ISD::CMPICC", SDTV8cmpicc>; 78def V8cmpfcc : SDNode<"V8ISD::CMPFCC", SDTV8cmpfcc>; 79def V8bricc : SDNode<"V8ISD::BRICC", SDTV8brcc, [SDNPHasChain]>; 80def V8brfcc : SDNode<"V8ISD::BRFCC", SDTV8brcc, [SDNPHasChain]>; 81 82def V8hi : SDNode<"V8ISD::Hi", SDTIntUnaryOp>; 83def V8lo : SDNode<"V8ISD::Lo", SDTIntUnaryOp>; 84 85def V8ftoi : SDNode<"V8ISD::FTOI", SDTV8FTOI>; 86def V8itof : SDNode<"V8ISD::ITOF", SDTV8ITOF>; 87 88def V8selecticc : SDNode<"V8ISD::SELECT_ICC", SDTV8selectcc>; 89def V8selectfcc : SDNode<"V8ISD::SELECT_FCC", SDTV8selectcc>; 90 91// These are target-independent nodes, but have target-specific formats. 92def SDT_V8CallSeq : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>; 93def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_V8CallSeq, [SDNPHasChain]>; 94def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_V8CallSeq, [SDNPHasChain]>; 95 96def SDT_V8Call : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>; 97def call : SDNode<"ISD::CALL", SDT_V8Call, 98 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; 99 100def SDT_V8RetFlag : SDTypeProfile<0, 0, []>; 101def retflag : SDNode<"V8ISD::RET_FLAG", SDT_V8RetFlag, 102 [SDNPHasChain, SDNPOptInFlag]>; 103 104//===----------------------------------------------------------------------===// 105// Instructions 106//===----------------------------------------------------------------------===// 107 108// Pseudo instructions. 109class Pseudo<dag ops, string asmstr, list<dag> pattern> 110 : InstV8<ops, asmstr, pattern>; 111 112def PHI : Pseudo<(ops variable_ops), "PHI", []>; 113def ADJCALLSTACKDOWN : Pseudo<(ops i32imm:$amt), 114 "!ADJCALLSTACKDOWN $amt", 115 [(callseq_start imm:$amt)]>; 116def ADJCALLSTACKUP : Pseudo<(ops i32imm:$amt), 117 "!ADJCALLSTACKUP $amt", 118 [(callseq_end imm:$amt)]>; 119def IMPLICIT_DEF_Int : Pseudo<(ops IntRegs:$dst), 120 "!IMPLICIT_DEF $dst", 121 [(set IntRegs:$dst, (undef))]>; 122def IMPLICIT_DEF_FP : Pseudo<(ops FPRegs:$dst), "!IMPLICIT_DEF $dst", 123 [(set FPRegs:$dst, (undef))]>; 124def IMPLICIT_DEF_DFP : Pseudo<(ops DFPRegs:$dst), "!IMPLICIT_DEF $dst", 125 [(set DFPRegs:$dst, (undef))]>; 126 127// FpMOVD/FpNEGD/FpABSD - These are lowered to single-precision ops by the 128// fpmover pass. 129def FpMOVD : Pseudo<(ops DFPRegs:$dst, DFPRegs:$src), 130 "!FpMOVD $src, $dst", []>; // pseudo 64-bit double move 131def FpNEGD : Pseudo<(ops DFPRegs:$dst, DFPRegs:$src), 132 "!FpNEGD $src, $dst", 133 [(set DFPRegs:$dst, (fneg DFPRegs:$src))]>; 134def FpABSD : Pseudo<(ops DFPRegs:$dst, DFPRegs:$src), 135 "!FpABSD $src, $dst", 136 [(set DFPRegs:$dst, (fabs DFPRegs:$src))]>; 137 138// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded by the 139// scheduler into a branch sequence. This has to handle all permutations of 140// selection between i32/f32/f64 on ICC and FCC. 141let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler. 142 def SELECT_CC_Int_ICC 143 : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F, i32imm:$Cond), 144 "; SELECT_CC_Int_ICC PSEUDO!", 145 [(set IntRegs:$dst, (V8selecticc IntRegs:$T, IntRegs:$F, 146 imm:$Cond, ICC))]>; 147 def SELECT_CC_Int_FCC 148 : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F, i32imm:$Cond), 149 "; SELECT_CC_Int_FCC PSEUDO!", 150 [(set IntRegs:$dst, (V8selectfcc IntRegs:$T, IntRegs:$F, 151 imm:$Cond, FCC))]>; 152 def SELECT_CC_FP_ICC 153 : Pseudo<(ops FPRegs:$dst, FPRegs:$T, FPRegs:$F, i32imm:$Cond), 154 "; SELECT_CC_FP_ICC PSEUDO!", 155 [(set FPRegs:$dst, (V8selecticc FPRegs:$T, FPRegs:$F, 156 imm:$Cond, ICC))]>; 157 def SELECT_CC_FP_FCC 158 : Pseudo<(ops FPRegs:$dst, FPRegs:$T, FPRegs:$F, i32imm:$Cond), 159 "; SELECT_CC_FP_FCC PSEUDO!", 160 [(set FPRegs:$dst, (V8selectfcc FPRegs:$T, FPRegs:$F, 161 imm:$Cond, FCC))]>; 162 def SELECT_CC_DFP_ICC 163 : Pseudo<(ops DFPRegs:$dst, DFPRegs:$T, DFPRegs:$F, i32imm:$Cond), 164 "; SELECT_CC_DFP_ICC PSEUDO!", 165 [(set DFPRegs:$dst, (V8selecticc DFPRegs:$T, DFPRegs:$F, 166 imm:$Cond, ICC))]>; 167 def SELECT_CC_DFP_FCC 168 : Pseudo<(ops DFPRegs:$dst, DFPRegs:$T, DFPRegs:$F, i32imm:$Cond), 169 "; SELECT_CC_DFP_FCC PSEUDO!", 170 [(set DFPRegs:$dst, (V8selectfcc DFPRegs:$T, DFPRegs:$F, 171 imm:$Cond, FCC))]>; 172} 173 174// Section A.3 - Synthetic Instructions, p. 85 175// special cases of JMPL: 176let isReturn = 1, isTerminator = 1, hasDelaySlot = 1, noResults = 1 in { 177 let rd = O7.Num, rs1 = G0.Num, simm13 = 8 in 178 def RETL: F3_2<2, 0b111000, (ops), "retl", [(retflag)]>; 179} 180 181// Section B.1 - Load Integer Instructions, p. 90 182def LDSBrr : F3_1<3, 0b001001, 183 (ops IntRegs:$dst, MEMrr:$addr), 184 "ldsb [$addr], $dst", 185 [(set IntRegs:$dst, (sextload ADDRrr:$addr, i8))]>; 186def LDSBri : F3_2<3, 0b001001, 187 (ops IntRegs:$dst, MEMri:$addr), 188 "ldsb [$addr], $dst", 189 [(set IntRegs:$dst, (sextload ADDRri:$addr, i8))]>; 190def LDSHrr : F3_1<3, 0b001010, 191 (ops IntRegs:$dst, MEMrr:$addr), 192 "ldsh [$addr], $dst", 193 [(set IntRegs:$dst, (sextload ADDRrr:$addr, i16))]>; 194def LDSHri : F3_2<3, 0b001010, 195 (ops IntRegs:$dst, MEMri:$addr), 196 "ldsh [$addr], $dst", 197 [(set IntRegs:$dst, (sextload ADDRri:$addr, i16))]>; 198def LDUBrr : F3_1<3, 0b000001, 199 (ops IntRegs:$dst, MEMrr:$addr), 200 "ldub [$addr], $dst", 201 [(set IntRegs:$dst, (zextload ADDRrr:$addr, i8))]>; 202def LDUBri : F3_2<3, 0b000001, 203 (ops IntRegs:$dst, MEMri:$addr), 204 "ldub [$addr], $dst", 205 [(set IntRegs:$dst, (zextload ADDRri:$addr, i8))]>; 206def LDUHrr : F3_1<3, 0b000010, 207 (ops IntRegs:$dst, MEMrr:$addr), 208 "lduh [$addr], $dst", 209 [(set IntRegs:$dst, (zextload ADDRrr:$addr, i16))]>; 210def LDUHri : F3_2<3, 0b000010, 211 (ops IntRegs:$dst, MEMri:$addr), 212 "lduh [$addr], $dst", 213 [(set IntRegs:$dst, (zextload ADDRri:$addr, i16))]>; 214def LDrr : F3_1<3, 0b000000, 215 (ops IntRegs:$dst, MEMrr:$addr), 216 "ld [$addr], $dst", 217 [(set IntRegs:$dst, (load ADDRrr:$addr))]>; 218def LDri : F3_2<3, 0b000000, 219 (ops IntRegs:$dst, MEMri:$addr), 220 "ld [$addr], $dst", 221 [(set IntRegs:$dst, (load ADDRri:$addr))]>; 222 223// Section B.2 - Load Floating-point Instructions, p. 92 224def LDFrr : F3_1<3, 0b100000, 225 (ops FPRegs:$dst, MEMrr:$addr), 226 "ld [$addr], $dst", 227 [(set FPRegs:$dst, (load ADDRrr:$addr))]>; 228def LDFri : F3_2<3, 0b100000, 229 (ops FPRegs:$dst, MEMri:$addr), 230 "ld [$addr], $dst", 231 [(set FPRegs:$dst, (load ADDRri:$addr))]>; 232def LDDFrr : F3_1<3, 0b100011, 233 (ops DFPRegs:$dst, MEMrr:$addr), 234 "ldd [$addr], $dst", 235 [(set DFPRegs:$dst, (load ADDRrr:$addr))]>; 236def LDDFri : F3_2<3, 0b100011, 237 (ops DFPRegs:$dst, MEMri:$addr), 238 "ldd [$addr], $dst", 239 [(set DFPRegs:$dst, (load ADDRri:$addr))]>; 240 241// Section B.4 - Store Integer Instructions, p. 95 242def STBrr : F3_1<3, 0b000101, 243 (ops MEMrr:$addr, IntRegs:$src), 244 "stb $src, [$addr]", 245 [(truncstore IntRegs:$src, ADDRrr:$addr, i8)]>; 246def STBri : F3_2<3, 0b000101, 247 (ops MEMri:$addr, IntRegs:$src), 248 "stb $src, [$addr]", 249 [(truncstore IntRegs:$src, ADDRri:$addr, i8)]>; 250def STHrr : F3_1<3, 0b000110, 251 (ops MEMrr:$addr, IntRegs:$src), 252 "sth $src, [$addr]", 253 [(truncstore IntRegs:$src, ADDRrr:$addr, i16)]>; 254def STHri : F3_2<3, 0b000110, 255 (ops MEMri:$addr, IntRegs:$src), 256 "sth $src, [$addr]", 257 [(truncstore IntRegs:$src, ADDRri:$addr, i16)]>; 258def STrr : F3_1<3, 0b000100, 259 (ops MEMrr:$addr, IntRegs:$src), 260 "st $src, [$addr]", 261 [(store IntRegs:$src, ADDRrr:$addr)]>; 262def STri : F3_2<3, 0b000100, 263 (ops MEMri:$addr, IntRegs:$src), 264 "st $src, [$addr]", 265 [(store IntRegs:$src, ADDRri:$addr)]>; 266 267// Section B.5 - Store Floating-point Instructions, p. 97 268def STFrr : F3_1<3, 0b100100, 269 (ops MEMrr:$addr, FPRegs:$src), 270 "st $src, [$addr]", 271 [(store FPRegs:$src, ADDRrr:$addr)]>; 272def STFri : F3_2<3, 0b100100, 273 (ops MEMri:$addr, FPRegs:$src), 274 "st $src, [$addr]", 275 [(store FPRegs:$src, ADDRri:$addr)]>; 276def STDFrr : F3_1<3, 0b100111, 277 (ops MEMrr:$addr, DFPRegs:$src), 278 "std $src, [$addr]", 279 [(store DFPRegs:$src, ADDRrr:$addr)]>; 280def STDFri : F3_2<3, 0b100111, 281 (ops MEMri:$addr, DFPRegs:$src), 282 "std $src, [$addr]", 283 [(store DFPRegs:$src, ADDRri:$addr)]>; 284 285// Section B.9 - SETHI Instruction, p. 104 286def SETHIi: F2_1<0b100, 287 (ops IntRegs:$dst, i32imm:$src), 288 "sethi $src, $dst", 289 [(set IntRegs:$dst, SETHIimm:$src)]>; 290 291// Section B.10 - NOP Instruction, p. 105 292// (It's a special case of SETHI) 293let rd = 0, imm22 = 0 in 294 def NOP : F2_1<0b100, (ops), "nop", []>; 295 296// Section B.11 - Logical Instructions, p. 106 297def ANDrr : F3_1<2, 0b000001, 298 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 299 "and $b, $c, $dst", 300 [(set IntRegs:$dst, (and IntRegs:$b, IntRegs:$c))]>; 301def ANDri : F3_2<2, 0b000001, 302 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 303 "and $b, $c, $dst", 304 [(set IntRegs:$dst, (and IntRegs:$b, simm13:$c))]>; 305def ANDNrr : F3_1<2, 0b000101, 306 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 307 "andn $b, $c, $dst", 308 [(set IntRegs:$dst, (and IntRegs:$b, (not IntRegs:$c)))]>; 309def ANDNri : F3_2<2, 0b000101, 310 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 311 "andn $b, $c, $dst", []>; 312def ORrr : F3_1<2, 0b000010, 313 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 314 "or $b, $c, $dst", 315 [(set IntRegs:$dst, (or IntRegs:$b, IntRegs:$c))]>; 316def ORri : F3_2<2, 0b000010, 317 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 318 "or $b, $c, $dst", 319 [(set IntRegs:$dst, (or IntRegs:$b, simm13:$c))]>; 320def ORNrr : F3_1<2, 0b000110, 321 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 322 "orn $b, $c, $dst", 323 [(set IntRegs:$dst, (or IntRegs:$b, (not IntRegs:$c)))]>; 324def ORNri : F3_2<2, 0b000110, 325 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 326 "orn $b, $c, $dst", []>; 327def XORrr : F3_1<2, 0b000011, 328 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 329 "xor $b, $c, $dst", 330 [(set IntRegs:$dst, (xor IntRegs:$b, IntRegs:$c))]>; 331def XORri : F3_2<2, 0b000011, 332 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 333 "xor $b, $c, $dst", 334 [(set IntRegs:$dst, (xor IntRegs:$b, simm13:$c))]>; 335def XNORrr : F3_1<2, 0b000111, 336 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 337 "xnor $b, $c, $dst", 338 [(set IntRegs:$dst, (not (xor IntRegs:$b, IntRegs:$c)))]>; 339def XNORri : F3_2<2, 0b000111, 340 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 341 "xnor $b, $c, $dst", []>; 342 343// Section B.12 - Shift Instructions, p. 107 344def SLLrr : F3_1<2, 0b100101, 345 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 346 "sll $b, $c, $dst", 347 [(set IntRegs:$dst, (shl IntRegs:$b, IntRegs:$c))]>; 348def SLLri : F3_2<2, 0b100101, 349 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 350 "sll $b, $c, $dst", 351 [(set IntRegs:$dst, (shl IntRegs:$b, simm13:$c))]>; 352def SRLrr : F3_1<2, 0b100110, 353 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 354 "srl $b, $c, $dst", 355 [(set IntRegs:$dst, (srl IntRegs:$b, IntRegs:$c))]>; 356def SRLri : F3_2<2, 0b100110, 357 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 358 "srl $b, $c, $dst", 359 [(set IntRegs:$dst, (srl IntRegs:$b, simm13:$c))]>; 360def SRArr : F3_1<2, 0b100111, 361 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 362 "sra $b, $c, $dst", 363 [(set IntRegs:$dst, (sra IntRegs:$b, IntRegs:$c))]>; 364def SRAri : F3_2<2, 0b100111, 365 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 366 "sra $b, $c, $dst", 367 [(set IntRegs:$dst, (sra IntRegs:$b, simm13:$c))]>; 368 369// Section B.13 - Add Instructions, p. 108 370def ADDrr : F3_1<2, 0b000000, 371 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 372 "add $b, $c, $dst", 373 [(set IntRegs:$dst, (add IntRegs:$b, IntRegs:$c))]>; 374def ADDri : F3_2<2, 0b000000, 375 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 376 "add $b, $c, $dst", 377 [(set IntRegs:$dst, (add IntRegs:$b, simm13:$c))]>; 378def ADDCCrr : F3_1<2, 0b010000, 379 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 380 "addcc $b, $c, $dst", []>; 381def ADDCCri : F3_2<2, 0b010000, 382 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 383 "addcc $b, $c, $dst", []>; 384def ADDXrr : F3_1<2, 0b001000, 385 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 386 "addx $b, $c, $dst", []>; 387def ADDXri : F3_2<2, 0b001000, 388 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 389 "addx $b, $c, $dst", []>; 390 391// Section B.15 - Subtract Instructions, p. 110 392def SUBrr : F3_1<2, 0b000100, 393 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 394 "sub $b, $c, $dst", 395 [(set IntRegs:$dst, (sub IntRegs:$b, IntRegs:$c))]>; 396def SUBri : F3_2<2, 0b000100, 397 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 398 "sub $b, $c, $dst", 399 [(set IntRegs:$dst, (sub IntRegs:$b, simm13:$c))]>; 400def SUBXrr : F3_1<2, 0b001100, 401 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 402 "subx $b, $c, $dst", []>; 403def SUBXri : F3_2<2, 0b001100, 404 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 405 "subx $b, $c, $dst", []>; 406def SUBCCrr : F3_1<2, 0b010100, 407 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 408 "subcc $b, $c, $dst", []>; 409def SUBCCri : F3_2<2, 0b010100, 410 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 411 "subcc $b, $c, $dst", []>; 412def SUBXCCrr: F3_1<2, 0b011100, 413 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 414 "subxcc $b, $c, $dst", []>; 415 416// Section B.18 - Multiply Instructions, p. 113 417def UMULrr : F3_1<2, 0b001010, 418 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 419 "umul $b, $c, $dst", []>; 420def UMULri : F3_2<2, 0b001010, 421 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 422 "umul $b, $c, $dst", []>; 423def SMULrr : F3_1<2, 0b001011, 424 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 425 "smul $b, $c, $dst", 426 [(set IntRegs:$dst, (mul IntRegs:$b, IntRegs:$c))]>; 427def SMULri : F3_2<2, 0b001011, 428 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 429 "smul $b, $c, $dst", 430 [(set IntRegs:$dst, (mul IntRegs:$b, simm13:$c))]>; 431 432// Section B.19 - Divide Instructions, p. 115 433def UDIVrr : F3_1<2, 0b001110, 434 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 435 "udiv $b, $c, $dst", []>; 436def UDIVri : F3_2<2, 0b001110, 437 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 438 "udiv $b, $c, $dst", []>; 439def SDIVrr : F3_1<2, 0b001111, 440 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 441 "sdiv $b, $c, $dst", []>; 442def SDIVri : F3_2<2, 0b001111, 443 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 444 "sdiv $b, $c, $dst", []>; 445 446// Section B.20 - SAVE and RESTORE, p. 117 447def SAVErr : F3_1<2, 0b111100, 448 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 449 "save $b, $c, $dst", []>; 450def SAVEri : F3_2<2, 0b111100, 451 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 452 "save $b, $c, $dst", []>; 453def RESTORErr : F3_1<2, 0b111101, 454 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 455 "restore $b, $c, $dst", []>; 456def RESTOREri : F3_2<2, 0b111101, 457 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 458 "restore $b, $c, $dst", []>; 459 460// Section B.21 - Branch on Integer Condition Codes Instructions, p. 119 461 462// conditional branch class: 463class BranchV8<bits<4> cc, dag ops, string asmstr, list<dag> pattern> 464 : F2_2<cc, 0b010, ops, asmstr, pattern> { 465 let isBranch = 1; 466 let isTerminator = 1; 467 let hasDelaySlot = 1; 468 let noResults = 1; 469} 470 471let isBarrier = 1 in 472 def BA : BranchV8<0b1000, (ops brtarget:$dst), 473 "ba $dst", 474 [(br bb:$dst)]>; 475def BNE : BranchV8<0b1001, (ops brtarget:$dst), 476 "bne $dst", 477 [(V8bricc bb:$dst, SETNE, ICC)]>; 478def BE : BranchV8<0b0001, (ops brtarget:$dst), 479 "be $dst", 480 [(V8bricc bb:$dst, SETEQ, ICC)]>; 481def BG : BranchV8<0b1010, (ops brtarget:$dst), 482 "bg $dst", 483 [(V8bricc bb:$dst, SETGT, ICC)]>; 484def BLE : BranchV8<0b0010, (ops brtarget:$dst), 485 "ble $dst", 486 [(V8bricc bb:$dst, SETLE, ICC)]>; 487def BGE : BranchV8<0b1011, (ops brtarget:$dst), 488 "bge $dst", 489 [(V8bricc bb:$dst, SETGE, ICC)]>; 490def BL : BranchV8<0b0011, (ops brtarget:$dst), 491 "bl $dst", 492 [(V8bricc bb:$dst, SETLT, ICC)]>; 493def BGU : BranchV8<0b1100, (ops brtarget:$dst), 494 "bgu $dst", 495 [(V8bricc bb:$dst, SETUGT, ICC)]>; 496def BLEU : BranchV8<0b0100, (ops brtarget:$dst), 497 "bleu $dst", 498 [(V8bricc bb:$dst, SETULE, ICC)]>; 499def BCC : BranchV8<0b1101, (ops brtarget:$dst), 500 "bcc $dst", 501 [(V8bricc bb:$dst, SETUGE, ICC)]>; 502def BCS : BranchV8<0b0101, (ops brtarget:$dst), 503 "bcs $dst", 504 [(V8bricc bb:$dst, SETULT, ICC)]>; 505 506// Section B.22 - Branch on Floating-point Condition Codes Instructions, p. 121 507 508// floating-point conditional branch class: 509class FPBranchV8<bits<4> cc, dag ops, string asmstr, list<dag> pattern> 510 : F2_2<cc, 0b110, ops, asmstr, pattern> { 511 let isBranch = 1; 512 let isTerminator = 1; 513 let hasDelaySlot = 1; 514 let noResults = 1; 515} 516 517def FBU : FPBranchV8<0b0111, (ops brtarget:$dst), 518 "fbu $dst", 519 [(V8brfcc bb:$dst, SETUO, FCC)]>; 520def FBG : FPBranchV8<0b0110, (ops brtarget:$dst), 521 "fbg $dst", 522 [(V8brfcc bb:$dst, SETGT, FCC)]>; 523def FBUG : FPBranchV8<0b0101, (ops brtarget:$dst), 524 "fbug $dst", 525 [(V8brfcc bb:$dst, SETUGT, FCC)]>; 526def FBL : FPBranchV8<0b0100, (ops brtarget:$dst), 527 "fbl $dst", 528 [(V8brfcc bb:$dst, SETLT, FCC)]>; 529def FBUL : FPBranchV8<0b0011, (ops brtarget:$dst), 530 "fbul $dst", 531 [(V8brfcc bb:$dst, SETULT, FCC)]>; 532def FBLG : FPBranchV8<0b0010, (ops brtarget:$dst), 533 "fblg $dst", 534 [(V8brfcc bb:$dst, SETONE, FCC)]>; 535def FBNE : FPBranchV8<0b0001, (ops brtarget:$dst), 536 "fbne $dst", 537 [(V8brfcc bb:$dst, SETNE, FCC)]>; 538def FBE : FPBranchV8<0b1001, (ops brtarget:$dst), 539 "fbe $dst", 540 [(V8brfcc bb:$dst, SETEQ, FCC)]>; 541def FBUE : FPBranchV8<0b1010, (ops brtarget:$dst), 542 "fbue $dst", 543 [(V8brfcc bb:$dst, SETUEQ, FCC)]>; 544def FBGE : FPBranchV8<0b1011, (ops brtarget:$dst), 545 "fbge $dst", 546 [(V8brfcc bb:$dst, SETGE, FCC)]>; 547def FBUGE: FPBranchV8<0b1100, (ops brtarget:$dst), 548 "fbuge $dst", 549 [(V8brfcc bb:$dst, SETUGE, FCC)]>; 550def FBLE : FPBranchV8<0b1101, (ops brtarget:$dst), 551 "fble $dst", 552 [(V8brfcc bb:$dst, SETLE, FCC)]>; 553def FBULE: FPBranchV8<0b1110, (ops brtarget:$dst), 554 "fbule $dst", 555 [(V8brfcc bb:$dst, SETULE, FCC)]>; 556def FBO : FPBranchV8<0b1111, (ops brtarget:$dst), 557 "fbo $dst", 558 [(V8brfcc bb:$dst, SETO, FCC)]>; 559 560 561 562// Section B.24 - Call and Link Instruction, p. 125 563// This is the only Format 1 instruction 564let Uses = [O0, O1, O2, O3, O4, O5], 565 hasDelaySlot = 1, isCall = 1, noResults = 1, 566 Defs = [O0, O1, O2, O3, O4, O5, O7, G1, G2, G3, G4, G5, G6, G7, 567 D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15] in { 568 def CALL : InstV8<(ops calltarget:$dst), 569 "call $dst", []> { 570 bits<30> disp; 571 let op = 1; 572 let Inst{29-0} = disp; 573 } 574 575 // indirect calls 576 def JMPLrr : F3_1<2, 0b111000, 577 (ops MEMrr:$ptr), 578 "call $ptr", 579 [(call ADDRrr:$ptr)]>; 580 def JMPLri : F3_2<2, 0b111000, 581 (ops MEMri:$ptr), 582 "call $ptr", 583 [(call ADDRri:$ptr)]>; 584} 585 586// Section B.28 - Read State Register Instructions 587def RDY : F3_1<2, 0b101000, 588 (ops IntRegs:$dst), 589 "rd %y, $dst", []>; 590 591// Section B.29 - Write State Register Instructions 592def WRYrr : F3_1<2, 0b110000, 593 (ops IntRegs:$b, IntRegs:$c), 594 "wr $b, $c, %y", []>; 595def WRYri : F3_2<2, 0b110000, 596 (ops IntRegs:$b, i32imm:$c), 597 "wr $b, $c, %y", []>; 598 599// Convert Integer to Floating-point Instructions, p. 141 600def FITOS : F3_3<2, 0b110100, 0b011000100, 601 (ops FPRegs:$dst, FPRegs:$src), 602 "fitos $src, $dst", 603 [(set FPRegs:$dst, (V8itof FPRegs:$src))]>; 604def FITOD : F3_3<2, 0b110100, 0b011001000, 605 (ops DFPRegs:$dst, FPRegs:$src), 606 "fitod $src, $dst", 607 [(set DFPRegs:$dst, (V8itof FPRegs:$src))]>; 608 609// Convert Floating-point to Integer Instructions, p. 142 610def FSTOI : F3_3<2, 0b110100, 0b011010001, 611 (ops FPRegs:$dst, FPRegs:$src), 612 "fstoi $src, $dst", 613 [(set FPRegs:$dst, (V8ftoi FPRegs:$src))]>; 614def FDTOI : F3_3<2, 0b110100, 0b011010010, 615 (ops FPRegs:$dst, DFPRegs:$src), 616 "fdtoi $src, $dst", 617 [(set FPRegs:$dst, (V8ftoi DFPRegs:$src))]>; 618 619// Convert between Floating-point Formats Instructions, p. 143 620def FSTOD : F3_3<2, 0b110100, 0b011001001, 621 (ops DFPRegs:$dst, FPRegs:$src), 622 "fstod $src, $dst", 623 [(set DFPRegs:$dst, (fextend FPRegs:$src))]>; 624def FDTOS : F3_3<2, 0b110100, 0b011000110, 625 (ops FPRegs:$dst, DFPRegs:$src), 626 "fdtos $src, $dst", 627 [(set FPRegs:$dst, (fround DFPRegs:$src))]>; 628 629// Floating-point Move Instructions, p. 144 630def FMOVS : F3_3<2, 0b110100, 0b000000001, 631 (ops FPRegs:$dst, FPRegs:$src), 632 "fmovs $src, $dst", []>; 633def FNEGS : F3_3<2, 0b110100, 0b000000101, 634 (ops FPRegs:$dst, FPRegs:$src), 635 "fnegs $src, $dst", 636 [(set FPRegs:$dst, (fneg FPRegs:$src))]>; 637def FABSS : F3_3<2, 0b110100, 0b000001001, 638 (ops FPRegs:$dst, FPRegs:$src), 639 "fabss $src, $dst", 640 [(set FPRegs:$dst, (fabs FPRegs:$src))]>; 641 642 643// Floating-point Square Root Instructions, p.145 644def FSQRTS : F3_3<2, 0b110100, 0b000101001, 645 (ops FPRegs:$dst, FPRegs:$src), 646 "fsqrts $src, $dst", 647 [(set FPRegs:$dst, (fsqrt FPRegs:$src))]>; 648def FSQRTD : F3_3<2, 0b110100, 0b000101010, 649 (ops DFPRegs:$dst, DFPRegs:$src), 650 "fsqrtd $src, $dst", 651 [(set DFPRegs:$dst, (fsqrt DFPRegs:$src))]>; 652 653 654 655// Floating-point Add and Subtract Instructions, p. 146 656def FADDS : F3_3<2, 0b110100, 0b001000001, 657 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2), 658 "fadds $src1, $src2, $dst", 659 [(set FPRegs:$dst, (fadd FPRegs:$src1, FPRegs:$src2))]>; 660def FADDD : F3_3<2, 0b110100, 0b001000010, 661 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2), 662 "faddd $src1, $src2, $dst", 663 [(set DFPRegs:$dst, (fadd DFPRegs:$src1, DFPRegs:$src2))]>; 664def FSUBS : F3_3<2, 0b110100, 0b001000101, 665 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2), 666 "fsubs $src1, $src2, $dst", 667 [(set FPRegs:$dst, (fsub FPRegs:$src1, FPRegs:$src2))]>; 668def FSUBD : F3_3<2, 0b110100, 0b001000110, 669 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2), 670 "fsubd $src1, $src2, $dst", 671 [(set DFPRegs:$dst, (fsub DFPRegs:$src1, DFPRegs:$src2))]>; 672 673// Floating-point Multiply and Divide Instructions, p. 147 674def FMULS : F3_3<2, 0b110100, 0b001001001, 675 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2), 676 "fmuls $src1, $src2, $dst", 677 [(set FPRegs:$dst, (fmul FPRegs:$src1, FPRegs:$src2))]>; 678def FMULD : F3_3<2, 0b110100, 0b001001010, 679 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2), 680 "fmuld $src1, $src2, $dst", 681 [(set DFPRegs:$dst, (fmul DFPRegs:$src1, DFPRegs:$src2))]>; 682def FSMULD : F3_3<2, 0b110100, 0b001101001, 683 (ops DFPRegs:$dst, FPRegs:$src1, FPRegs:$src2), 684 "fsmuld $src1, $src2, $dst", 685 [(set DFPRegs:$dst, (fmul (fextend FPRegs:$src1), 686 (fextend FPRegs:$src2)))]>; 687def FDIVS : F3_3<2, 0b110100, 0b001001101, 688 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2), 689 "fdivs $src1, $src2, $dst", 690 [(set FPRegs:$dst, (fdiv FPRegs:$src1, FPRegs:$src2))]>; 691def FDIVD : F3_3<2, 0b110100, 0b001001110, 692 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2), 693 "fdivd $src1, $src2, $dst", 694 [(set DFPRegs:$dst, (fdiv DFPRegs:$src1, DFPRegs:$src2))]>; 695 696// Floating-point Compare Instructions, p. 148 697// Note: the 2nd template arg is different for these guys. 698// Note 2: the result of a FCMP is not available until the 2nd cycle 699// after the instr is retired, but there is no interlock. This behavior 700// is modelled with a forced noop after the instruction. 701def FCMPS : F3_3<2, 0b110101, 0b001010001, 702 (ops FPRegs:$src1, FPRegs:$src2), 703 "fcmps $src1, $src2\n\tnop", 704 [(set FCC, (V8cmpfcc FPRegs:$src1, FPRegs:$src2))]>; 705def FCMPD : F3_3<2, 0b110101, 0b001010010, 706 (ops DFPRegs:$src1, DFPRegs:$src2), 707 "fcmpd $src1, $src2\n\tnop", 708 [(set FCC, (V8cmpfcc DFPRegs:$src1, DFPRegs:$src2))]>; 709 710//===----------------------------------------------------------------------===// 711// Non-Instruction Patterns 712//===----------------------------------------------------------------------===// 713 714// Small immediates. 715def : Pat<(i32 simm13:$val), 716 (ORri G0, imm:$val)>; 717// Arbitrary immediates. 718def : Pat<(i32 imm:$val), 719 (ORri (SETHIi (HI22 imm:$val)), (LO10 imm:$val))>; 720 721// Global addresses, constant pool entries 722def : Pat<(V8hi tglobaladdr:$in), (SETHIi tglobaladdr:$in)>; 723def : Pat<(V8lo tglobaladdr:$in), (ORri G0, tglobaladdr:$in)>; 724def : Pat<(V8hi tconstpool:$in), (SETHIi tconstpool:$in)>; 725def : Pat<(V8lo tconstpool:$in), (ORri G0, tconstpool:$in)>; 726 727// Calls: 728def : Pat<(call tglobaladdr:$dst), 729 (CALL tglobaladdr:$dst)>; 730def : Pat<(call externalsym:$dst), 731 (CALL externalsym:$dst)>; 732 733def : Pat<(ret), (RETL)>; 734 735// Map integer extload's to zextloads. 736def : Pat<(i32 (extload ADDRrr:$src, i1)), (LDUBrr ADDRrr:$src)>; 737def : Pat<(i32 (extload ADDRri:$src, i1)), (LDUBri ADDRri:$src)>; 738def : Pat<(i32 (extload ADDRrr:$src, i8)), (LDUBrr ADDRrr:$src)>; 739def : Pat<(i32 (extload ADDRri:$src, i8)), (LDUBri ADDRri:$src)>; 740def : Pat<(i32 (extload ADDRrr:$src, i16)), (LDUHrr ADDRrr:$src)>; 741def : Pat<(i32 (extload ADDRri:$src, i16)), (LDUHri ADDRri:$src)>; 742 743// zextload bool -> zextload byte 744def : Pat<(i32 (zextload ADDRrr:$src, i1)), (LDUBrr ADDRrr:$src)>; 745def : Pat<(i32 (zextload ADDRri:$src, i1)), (LDUBri ADDRri:$src)>; 746 747// truncstore bool -> truncstore byte. 748def : Pat<(truncstore IntRegs:$src, ADDRrr:$addr, i1), 749 (STBrr ADDRrr:$addr, IntRegs:$src)>; 750def : Pat<(truncstore IntRegs:$src, ADDRri:$addr, i1), 751 (STBri ADDRri:$addr, IntRegs:$src)>; 752