SparcInstrInfo.td revision 1c4f4356032195f05c715b113b4ee5e2d4909915
1//===- SparcV8Instrs.td - Target Description for SparcV8 Target -----------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the SparcV8 instructions in TableGen format. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// Instruction format superclass 16//===----------------------------------------------------------------------===// 17 18class InstV8 : Instruction { // SparcV8 instruction baseline 19 field bits<32> Inst; 20 21 let Namespace = "V8"; 22 23 bits<2> op; 24 let Inst{31-30} = op; // Top two bits are the 'op' field 25 26 // Bit attributes specific to SparcV8 instructions 27 bit isPasi = 0; // Does this instruction affect an alternate addr space? 28 bit isPrivileged = 0; // Is this a privileged instruction? 29} 30 31include "SparcV8InstrFormats.td" 32 33//===----------------------------------------------------------------------===// 34// Instructions 35//===----------------------------------------------------------------------===// 36 37// Pseudo instructions. 38class PseudoInstV8<string nm, dag ops> : InstV8 { 39 let Name = nm; 40 dag OperandList = ops; 41} 42def PHI : PseudoInstV8<"PHI", (ops variable_ops)>; 43def ADJCALLSTACKDOWN : PseudoInstV8<"ADJCALLSTACKDOWN", (ops variable_ops)>; 44def ADJCALLSTACKUP : PseudoInstV8<"ADJCALLSTACKUP", (ops variable_ops)>; 45def IMPLICIT_USE : PseudoInstV8<"IMPLICIT_USE", (ops variable_ops)>; 46def IMPLICIT_DEF : PseudoInstV8<"IMPLICIT_DEF", (ops variable_ops)>; 47def FpMOVD : PseudoInstV8<"FpMOVD", (ops)>; // pseudo 64-bit double move 48 49// Section A.3 - Synthetic Instructions, p. 85 50// special cases of JMPL: 51let isReturn = 1, isTerminator = 1, hasDelaySlot = 1 in { 52 let rd = I7.Num, rs1 = G0.Num, simm13 = 8 in 53 def RET : F3_2<2, 0b111000, 54 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "ret">; 55 let rd = O7.Num, rs1 = G0.Num, simm13 = 8 in 56 def RETL: F3_2<2, 0b111000, 57 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "retl">; 58} 59// CMP is a special case of SUBCC where destination is ignored, by setting it to 60// %g0 (hardwired zero). 61// FIXME: should keep track of the fact that it defs the integer condition codes 62let rd = 0 in 63 def CMPri: F3_2<2, 0b010100, 64 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "cmp">; 65 66// Section B.1 - Load Integer Instructions, p. 90 67def LDSB: F3_2<3, 0b001001, 68 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "ldsb">; 69def LDSH: F3_2<3, 0b001010, 70 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "ldsh">; 71def LDUB: F3_2<3, 0b000001, 72 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "ldub">; 73def LDUH: F3_2<3, 0b000010, 74 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "lduh">; 75def LD : F3_2<3, 0b000000, 76 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "ld">; 77def LDD : F3_2<3, 0b000011, 78 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "ldd">; 79 80// Section B.2 - Load Floating-point Instructions, p. 92 81def LDFrr : F3_1<3, 0b100000, 82 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 83 "ld $b, $c, $dst">; 84def LDFri : F3_2<3, 0b100000, 85 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "ld">; 86def LDDFrr : F3_1<3, 0b100011, 87 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 88 "ldd $b, $c, $dst">; 89def LDDFri : F3_2<3, 0b100011, 90 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "ldd">; 91def LDFSRrr: F3_1<3, 0b100001, 92 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 93 "ld $b, $c, $dst">; 94def LDFSRri: F3_2<3, 0b100001, 95 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "ld">; 96 97// Section B.4 - Store Integer Instructions, p. 95 98def STB : F3_2<3, 0b000101, 99 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "stb">; 100def STH : F3_2<3, 0b000110, 101 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "sth">; 102def ST : F3_2<3, 0b000100, 103 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "st">; 104def STD : F3_2<3, 0b000111, 105 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "std">; 106 107// Section B.5 - Store Floating-point Instructions, p. 97 108def STFrr : F3_1<3, 0b100100, 109 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 110 "st $b, $c, $dst">; 111def STFri : F3_2<3, 0b100100, 112 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "st">; 113def STDFrr : F3_1<3, 0b100111, 114 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 115 "std $b, $c, $dst">; 116def STDFri : F3_2<3, 0b100111, 117 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "std">; 118def STFSRrr : F3_1<3, 0b100101, 119 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 120 "st $b, $c, $dst">; 121def STFSRri : F3_2<3, 0b100101, 122 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "st">; 123def STDFQrr : F3_1<3, 0b100110, 124 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 125 "std $b, $c, $dst">; 126def STDFQri : F3_2<3, 0b100110, 127 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "std">; 128 129// Section B.9 - SETHI Instruction, p. 104 130def SETHIi: F2_1<0b100, "sethi">; 131 132// Section B.10 - NOP Instruction, p. 105 133// (It's a special case of SETHI) 134let rd = 0, imm22 = 0 in 135 def NOP : F2_1<0b100, "nop">; 136 137// Section B.11 - Logical Instructions, p. 106 138def ANDrr : F3_1<2, 0b000001, 139 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 140 "and $b, $c, $dst">; 141def ANDri : F3_2<2, 0b000001, 142 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "and">; 143def ANDCCrr : F3_1<2, 0b010001, 144 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 145 "andcc $b, $c, $dst">; 146def ANDCCri : F3_2<2, 0b010001, 147 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "andcc">; 148def ANDNrr : F3_1<2, 0b000101, 149 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 150 "andn $b, $c, $dst">; 151def ANDNri : F3_2<2, 0b000101, 152 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "andn">; 153def ANDNCCrr: F3_1<2, 0b010101, 154 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 155 "andncc $b, $c, $dst">; 156def ANDNCCri: F3_2<2, 0b010101, 157 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "andncc">; 158def ORrr : F3_1<2, 0b000010, 159 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 160 "or $b, $c, $dst">; 161def ORri : F3_2<2, 0b000010, 162 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "or">; 163def ORCCrr : F3_1<2, 0b010010, 164 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 165 "orcc $b, $c, $dst">; 166def ORCCri : F3_2<2, 0b010010, 167 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "orcc">; 168def ORNrr : F3_1<2, 0b000110, 169 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 170 "orn $b, $c, $dst">; 171def ORNri : F3_2<2, 0b000110, 172 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "orn">; 173def ORNCCrr : F3_1<2, 0b010110, 174 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 175 "orncc $b, $c, $dst">; 176def ORNCCri : F3_2<2, 0b010110, 177 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "orncc">; 178def XORrr : F3_1<2, 0b000011, 179 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 180 "xor $b, $c, $dst">; 181def XORri : F3_2<2, 0b000011, 182 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "xor">; 183def XORCCrr : F3_1<2, 0b010011, 184 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 185 "xorcc $b, $c, $dst">; 186def XORCCri : F3_2<2, 0b010011, 187 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "xorcc">; 188def XNORrr : F3_1<2, 0b000111, 189 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 190 "xnor $b, $c, $dst">; 191def XNORri : F3_2<2, 0b000111, 192 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "xnor">; 193def XNORCCrr: F3_1<2, 0b010111, 194 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 195 "xnorcc $b, $c, $dst">; 196def XNORCCri: F3_2<2, 0b010111, 197 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "xnorcc">; 198 199// Section B.12 - Shift Instructions, p. 107 200def SLLrr : F3_1<2, 0b100101, 201 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 202 "sll $b, $c, $dst">; 203def SLLri : F3_2<2, 0b100101, 204 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "sll">; 205def SRLrr : F3_1<2, 0b100110, 206 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 207 "srl $b, $c, $dst">; 208def SRLri : F3_2<2, 0b100110, 209 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "srl">; 210def SRArr : F3_1<2, 0b100111, 211 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 212 "sra $b, $c, $dst">; 213def SRAri : F3_2<2, 0b100111, 214 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "sra">; 215 216// Section B.13 - Add Instructions, p. 108 217def ADDrr : F3_1<2, 0b000000, 218 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 219 "add $b, $c, $dst">; 220def ADDri : F3_2<2, 0b000000, 221 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "add">; 222def ADDCCrr : F3_1<2, 0b010000, 223 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 224 "addcc $b, $c, $dst">; 225def ADDCCri : F3_2<2, 0b010000, 226 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "addcc">; 227def ADDXrr : F3_1<2, 0b001000, 228 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 229 "addx $b, $c, $dst">; 230def ADDXri : F3_2<2, 0b001000, 231 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "addx">; 232def ADDXCCrr: F3_1<2, 0b011000, 233 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 234 "addxcc $b, $c, $dst">; 235def ADDXCCri: F3_2<2, 0b011000, 236 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "addxcc">; 237 238// Section B.15 - Subtract Instructions, p. 110 239def SUBrr : F3_1<2, 0b000100, 240 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 241 "sub $b, $c, $dst">; 242def SUBri : F3_2<2, 0b000100, 243 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "sub">; 244def SUBCCrr : F3_1<2, 0b010100, 245 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 246 "subcc $b, $c, $dst">; 247def SUBCCri : F3_2<2, 0b010100, 248 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "subcc">; 249def SUBXrr : F3_1<2, 0b001100, 250 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 251 "subx $b, $c, $dst">; 252def SUBXri : F3_2<2, 0b001100, 253 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "subx">; 254def SUBXCCrr: F3_1<2, 0b011100, 255 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 256 "subxcc $b, $c, $dst">; 257def SUBXCCri: F3_2<2, 0b011100, 258 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "subxcc">; 259 260// Section B.18 - Multiply Instructions, p. 113 261def UMULrr : F3_1<2, 0b001010, 262 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 263 "umul $b, $c, $dst">; 264def UMULri : F3_2<2, 0b001010, 265 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "umul">; 266def SMULrr : F3_1<2, 0b001011, 267 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 268 "smul $b, $c, $dst">; 269def SMULri : F3_2<2, 0b001011, 270 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "smul">; 271def UMULCCrr: F3_1<2, 0b011010, 272 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 273 "umulcc $b, $c, $dst">; 274def UMULCCri: F3_2<2, 0b011010, 275 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "umulcc">; 276def SMULCCrr: F3_1<2, 0b011011, 277 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 278 "smulcc $b, $c, $dst">; 279def SMULCCri: F3_2<2, 0b011011, 280 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "smulcc">; 281 282// Section B.19 - Divide Instructions, p. 115 283def UDIVrr : F3_1<2, 0b001110, 284 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 285 "udiv $b, $c, $dst">; 286def UDIVri : F3_2<2, 0b001110, 287 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "udiv">; 288def SDIVrr : F3_1<2, 0b001111, 289 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 290 "sdiv $b, $c, $dst">; 291def SDIVri : F3_2<2, 0b001111, 292 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "sdiv">; 293def UDIVCCrr : F3_1<2, 0b011110, 294 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 295 "udivcc $b, $c, $dst">; 296def UDIVCCri : F3_2<2, 0b011110, 297 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "udivcc">; 298def SDIVCCrr : F3_1<2, 0b011111, 299 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 300 "sdivcc $b, $c, $dst">; 301def SDIVCCri : F3_2<2, 0b011111, 302 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "sdivcc">; 303 304// Section B.20 - SAVE and RESTORE, p. 117 305def SAVErr : F3_1<2, 0b111100, 306 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 307 "save $b, $c, $dst">; 308def SAVEri : F3_2<2, 0b111100, 309 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "save">; 310def RESTORErr : F3_1<2, 0b111101, 311 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 312 "restore $b, $c, $dst">; 313def RESTOREri : F3_2<2, 0b111101, 314 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "restore">; 315 316// Section B.21 - Branch on Integer Condition Codes Instructions, p. 119 317 318// conditional branch class: 319class BranchV8<bits<4> cc, string nm> : F2_2<cc, 0b010, nm> { 320 let isBranch = 1; 321 let isTerminator = 1; 322 let hasDelaySlot = 1; 323} 324 325let isBarrier = 1 in 326 def BA : BranchV8<0b1000, "ba">; 327def BN : BranchV8<0b0000, "bn">; 328def BNE : BranchV8<0b1001, "bne">; 329def BE : BranchV8<0b0001, "be">; 330def BG : BranchV8<0b1010, "bg">; 331def BLE : BranchV8<0b0010, "ble">; 332def BGE : BranchV8<0b1011, "bge">; 333def BL : BranchV8<0b0011, "bl">; 334def BGU : BranchV8<0b1100, "bgu">; 335def BLEU : BranchV8<0b0100, "bleu">; 336def BCC : BranchV8<0b1101, "bcc">; 337def BCS : BranchV8<0b0101, "bcs">; 338 339// Section B.22 - Branch on Floating-point Condition Codes Instructions, p. 121 340 341// floating-point conditional branch class: 342class FPBranchV8<bits<4> cc, string nm> : F2_2<cc, 0b110, nm> { 343 let isBranch = 1; 344 let isTerminator = 1; 345 let hasDelaySlot = 1; 346} 347 348def FBA : FPBranchV8<0b1000, "fba">; 349def FBN : FPBranchV8<0b0000, "fbn">; 350def FBU : FPBranchV8<0b0111, "fbu">; 351def FBG : FPBranchV8<0b0110, "fbg">; 352def FBUG : FPBranchV8<0b0101, "fbug">; 353def FBL : FPBranchV8<0b0100, "fbl">; 354def FBUL : FPBranchV8<0b0011, "fbul">; 355def FBLG : FPBranchV8<0b0010, "fblg">; 356def FBNE : FPBranchV8<0b0001, "fbne">; 357def FBE : FPBranchV8<0b1001, "fbe">; 358def FBUE : FPBranchV8<0b1010, "fbue">; 359def FBGE : FPBranchV8<0b1011, "fbge">; 360def FBUGE: FPBranchV8<0b1100, "fbuge">; 361def FBLE : FPBranchV8<0b1101, "fble">; 362def FBULE: FPBranchV8<0b1110, "fbule">; 363def FBO : FPBranchV8<0b1111, "fbo">; 364 365 366 367// Section B.24 - Call and Link Instruction, p. 125 368// This is the only Format 1 instruction 369let Uses = [O0, O1, O2, O3, O4, O5], hasDelaySlot = 1, isCall = 1 in { 370 // pc-relative call: 371 let Defs = [O0, O1, O2, O3, O4, O5, O7, G1, G2, G3, G4, G5, G6, G7, 372 D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15] in 373 def CALL : InstV8 { 374 bits<30> disp; 375 let op = 1; 376 let Inst{29-0} = disp; 377 let Name = "call"; 378 } 379 380 // indirect call (O7 is an EXPLICIT def in indirect calls, so it cannot also 381 // be an implicit def): 382 let Defs = [O0, O1, O2, O3, O4, O5, G1, G2, G3, G4, G5, G6, G7, 383 D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15] in 384 def JMPLrr : F3_1<2, 0b111000, 385 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 386 "jmpl $b+$c, $dst">; 387} 388 389// Section B.29 - Write State Register Instructions 390def WRrr : F3_1<2, 0b110000, 391 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 392 "wr $b, $c, $dst">; 393def WRri : F3_2<2, 0b110000, 394 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "wr">; // wr rs1, imm, rd 395 396// Convert Integer to Floating-point Instructions, p. 141 397def FITOS : F3_3<2, 0b110100, 0b011000100, "fitos">; 398def FITOD : F3_3<2, 0b110100, 0b011001000, "fitod">; 399 400// Convert Floating-point to Integer Instructions, p. 142 401def FSTOI : F3_3<2, 0b110100, 0b011010001, "fstoi">; 402def FDTOI : F3_3<2, 0b110100, 0b011010010, "fdtoi">; 403 404// Convert between Floating-point Formats Instructions, p. 143 405def FSTOD : F3_3<2, 0b110100, 0b011001001, "fstod">; 406def FDTOS : F3_3<2, 0b110100, 0b011000110, "fdtos">; 407 408// Floating-point Move Instructions, p. 144 409def FMOVS : F3_3<2, 0b110100, 0b000000001, "fmovs">; 410def FNEGS : F3_3<2, 0b110100, 0b000000101, "fnegs">; 411def FABSS : F3_3<2, 0b110100, 0b000001001, "fabss">; 412 413// Floating-point Add and Subtract Instructions, p. 146 414def FADDS : F3_3<2, 0b110100, 0b001000001, "fadds">; 415def FADDD : F3_3<2, 0b110100, 0b001000010, "faddd">; 416def FSUBS : F3_3<2, 0b110100, 0b001000101, "fsubs">; 417def FSUBD : F3_3<2, 0b110100, 0b001000110, "fsubd">; 418 419// Floating-point Multiply and Divide Instructions, p. 147 420def FMULS : F3_3<2, 0b110100, 0b001001001, "fmuls">; 421def FMULD : F3_3<2, 0b110100, 0b001001010, "fmuld">; 422def FSMULD : F3_3<2, 0b110100, 0b001101001, "fsmuld">; 423def FDIVS : F3_3<2, 0b110100, 0b001001101, "fdivs">; 424def FDIVD : F3_3<2, 0b110100, 0b001001110, "fdivd">; 425 426// Floating-point Compare Instructions, p. 148 427// Note: the 2nd template arg is different for these guys. 428// Note 2: the result of a FCMP is not available until the 2nd cycle 429// after the instr is retired, but there is no interlock. This behavior 430// is modelled as a delay slot. 431let hasDelaySlot = 1 in { 432 def FCMPS : F3_3<2, 0b110101, 0b001010001, "fcmps">; 433 def FCMPD : F3_3<2, 0b110101, 0b001010010, "fcmpd">; 434 def FCMPES : F3_3<2, 0b110101, 0b001010101, "fcmpes">; 435 def FCMPED : F3_3<2, 0b110101, 0b001010110, "fcmped">; 436} 437 438