SparcInstrInfo.td revision 1cefde83ffcfe869e86ef1976667f47856087dd3
1//===-- SparcInstrInfo.td - Target Description for Sparc Target -----------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the Sparc instructions in TableGen format. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// Instruction format superclass 16//===----------------------------------------------------------------------===// 17 18include "SparcInstrFormats.td" 19 20//===----------------------------------------------------------------------===// 21// Feature predicates. 22//===----------------------------------------------------------------------===// 23 24// True when generating 32-bit code. 25def Is32Bit : Predicate<"!Subtarget.is64Bit()">; 26 27// True when generating 64-bit code. This also implies HasV9. 28def Is64Bit : Predicate<"Subtarget.is64Bit()">; 29 30// HasV9 - This predicate is true when the target processor supports V9 31// instructions. Note that the machine may be running in 32-bit mode. 32def HasV9 : Predicate<"Subtarget.isV9()">; 33 34// HasNoV9 - This predicate is true when the target doesn't have V9 35// instructions. Use of this is just a hack for the isel not having proper 36// costs for V8 instructions that are more expensive than their V9 ones. 37def HasNoV9 : Predicate<"!Subtarget.isV9()">; 38 39// HasVIS - This is true when the target processor has VIS extensions. 40def HasVIS : Predicate<"Subtarget.isVIS()">; 41 42// HasHardQuad - This is true when the target processor supports quad floating 43// point instructions. 44def HasHardQuad : Predicate<"Subtarget.hasHardQuad()">; 45 46// UseDeprecatedInsts - This predicate is true when the target processor is a 47// V8, or when it is V9 but the V8 deprecated instructions are efficient enough 48// to use when appropriate. In either of these cases, the instruction selector 49// will pick deprecated instructions. 50def UseDeprecatedInsts : Predicate<"Subtarget.useDeprecatedV8Instructions()">; 51 52//===----------------------------------------------------------------------===// 53// Instruction Pattern Stuff 54//===----------------------------------------------------------------------===// 55 56def simm11 : PatLeaf<(imm), [{ return isInt<11>(N->getSExtValue()); }]>; 57 58def simm13 : PatLeaf<(imm), [{ return isInt<13>(N->getSExtValue()); }]>; 59 60def LO10 : SDNodeXForm<imm, [{ 61 return CurDAG->getTargetConstant((unsigned)N->getZExtValue() & 1023, 62 MVT::i32); 63}]>; 64 65def HI22 : SDNodeXForm<imm, [{ 66 // Transformation function: shift the immediate value down into the low bits. 67 return CurDAG->getTargetConstant((unsigned)N->getZExtValue() >> 10, MVT::i32); 68}]>; 69 70def SETHIimm : PatLeaf<(imm), [{ 71 return isShiftedUInt<22, 10>(N->getZExtValue()); 72}], HI22>; 73 74// Addressing modes. 75def ADDRrr : ComplexPattern<iPTR, 2, "SelectADDRrr", [], []>; 76def ADDRri : ComplexPattern<iPTR, 2, "SelectADDRri", [frameindex], []>; 77 78// Address operands 79def MEMrr : Operand<iPTR> { 80 let PrintMethod = "printMemOperand"; 81 let MIOperandInfo = (ops ptr_rc, ptr_rc); 82} 83def MEMri : Operand<iPTR> { 84 let PrintMethod = "printMemOperand"; 85 let MIOperandInfo = (ops ptr_rc, i32imm); 86} 87 88def TLSSym : Operand<iPTR>; 89 90// Branch targets have OtherVT type. 91def brtarget : Operand<OtherVT>; 92def calltarget : Operand<i32>; 93 94// Operand for printing out a condition code. 95let PrintMethod = "printCCOperand" in 96 def CCOp : Operand<i32>; 97 98def SDTSPcmpicc : 99SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>]>; 100def SDTSPcmpfcc : 101SDTypeProfile<0, 2, [SDTCisFP<0>, SDTCisSameAs<0, 1>]>; 102def SDTSPbrcc : 103SDTypeProfile<0, 2, [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>; 104def SDTSPselectcc : 105SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>]>; 106def SDTSPFTOI : 107SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisFP<1>]>; 108def SDTSPITOF : 109SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f32>]>; 110def SDTSPFTOX : 111SDTypeProfile<1, 1, [SDTCisVT<0, f64>, SDTCisFP<1>]>; 112def SDTSPXTOF : 113SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f64>]>; 114 115def SDTSPtlsadd : 116SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>, SDTCisPtrTy<2>]>; 117def SDTSPtlsld : 118SDTypeProfile<1, 2, [SDTCisPtrTy<0>, SDTCisPtrTy<1>]>; 119 120def SPcmpicc : SDNode<"SPISD::CMPICC", SDTSPcmpicc, [SDNPOutGlue]>; 121def SPcmpfcc : SDNode<"SPISD::CMPFCC", SDTSPcmpfcc, [SDNPOutGlue]>; 122def SPbricc : SDNode<"SPISD::BRICC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>; 123def SPbrxcc : SDNode<"SPISD::BRXCC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>; 124def SPbrfcc : SDNode<"SPISD::BRFCC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>; 125 126def SPhi : SDNode<"SPISD::Hi", SDTIntUnaryOp>; 127def SPlo : SDNode<"SPISD::Lo", SDTIntUnaryOp>; 128 129def SPftoi : SDNode<"SPISD::FTOI", SDTSPFTOI>; 130def SPitof : SDNode<"SPISD::ITOF", SDTSPITOF>; 131def SPftox : SDNode<"SPISD::FTOX", SDTSPFTOX>; 132def SPxtof : SDNode<"SPISD::XTOF", SDTSPXTOF>; 133 134def SPselecticc : SDNode<"SPISD::SELECT_ICC", SDTSPselectcc, [SDNPInGlue]>; 135def SPselectxcc : SDNode<"SPISD::SELECT_XCC", SDTSPselectcc, [SDNPInGlue]>; 136def SPselectfcc : SDNode<"SPISD::SELECT_FCC", SDTSPselectcc, [SDNPInGlue]>; 137 138// These are target-independent nodes, but have target-specific formats. 139def SDT_SPCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>; 140def SDT_SPCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, 141 SDTCisVT<1, i32> ]>; 142 143def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_SPCallSeqStart, 144 [SDNPHasChain, SDNPOutGlue]>; 145def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_SPCallSeqEnd, 146 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 147 148def SDT_SPCall : SDTypeProfile<0, -1, [SDTCisVT<0, i32>]>; 149def call : SDNode<"SPISD::CALL", SDT_SPCall, 150 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 151 SDNPVariadic]>; 152 153def SDT_SPRet : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>; 154def retflag : SDNode<"SPISD::RET_FLAG", SDT_SPRet, 155 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 156 157def flushw : SDNode<"SPISD::FLUSHW", SDTNone, 158 [SDNPHasChain, SDNPSideEffect, SDNPMayStore]>; 159 160def tlsadd : SDNode<"SPISD::TLS_ADD", SDTSPtlsadd>; 161def tlsld : SDNode<"SPISD::TLS_LD", SDTSPtlsld>; 162def tlscall : SDNode<"SPISD::TLS_CALL", SDT_SPCall, 163 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 164 SDNPVariadic]>; 165 166def getPCX : Operand<i32> { 167 let PrintMethod = "printGetPCX"; 168} 169 170//===----------------------------------------------------------------------===// 171// SPARC Flag Conditions 172//===----------------------------------------------------------------------===// 173 174// Note that these values must be kept in sync with the CCOp::CondCode enum 175// values. 176class ICC_VAL<int N> : PatLeaf<(i32 N)>; 177def ICC_NE : ICC_VAL< 9>; // Not Equal 178def ICC_E : ICC_VAL< 1>; // Equal 179def ICC_G : ICC_VAL<10>; // Greater 180def ICC_LE : ICC_VAL< 2>; // Less or Equal 181def ICC_GE : ICC_VAL<11>; // Greater or Equal 182def ICC_L : ICC_VAL< 3>; // Less 183def ICC_GU : ICC_VAL<12>; // Greater Unsigned 184def ICC_LEU : ICC_VAL< 4>; // Less or Equal Unsigned 185def ICC_CC : ICC_VAL<13>; // Carry Clear/Great or Equal Unsigned 186def ICC_CS : ICC_VAL< 5>; // Carry Set/Less Unsigned 187def ICC_POS : ICC_VAL<14>; // Positive 188def ICC_NEG : ICC_VAL< 6>; // Negative 189def ICC_VC : ICC_VAL<15>; // Overflow Clear 190def ICC_VS : ICC_VAL< 7>; // Overflow Set 191 192class FCC_VAL<int N> : PatLeaf<(i32 N)>; 193def FCC_U : FCC_VAL<23>; // Unordered 194def FCC_G : FCC_VAL<22>; // Greater 195def FCC_UG : FCC_VAL<21>; // Unordered or Greater 196def FCC_L : FCC_VAL<20>; // Less 197def FCC_UL : FCC_VAL<19>; // Unordered or Less 198def FCC_LG : FCC_VAL<18>; // Less or Greater 199def FCC_NE : FCC_VAL<17>; // Not Equal 200def FCC_E : FCC_VAL<25>; // Equal 201def FCC_UE : FCC_VAL<24>; // Unordered or Equal 202def FCC_GE : FCC_VAL<25>; // Greater or Equal 203def FCC_UGE : FCC_VAL<26>; // Unordered or Greater or Equal 204def FCC_LE : FCC_VAL<27>; // Less or Equal 205def FCC_ULE : FCC_VAL<28>; // Unordered or Less or Equal 206def FCC_O : FCC_VAL<29>; // Ordered 207 208//===----------------------------------------------------------------------===// 209// Instruction Class Templates 210//===----------------------------------------------------------------------===// 211 212/// F3_12 multiclass - Define a normal F3_1/F3_2 pattern in one shot. 213multiclass F3_12<string OpcStr, bits<6> Op3Val, SDNode OpNode> { 214 def rr : F3_1<2, Op3Val, 215 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c), 216 !strconcat(OpcStr, " $b, $c, $dst"), 217 [(set i32:$dst, (OpNode i32:$b, i32:$c))]>; 218 def ri : F3_2<2, Op3Val, 219 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c), 220 !strconcat(OpcStr, " $b, $c, $dst"), 221 [(set i32:$dst, (OpNode i32:$b, (i32 simm13:$c)))]>; 222} 223 224/// F3_12np multiclass - Define a normal F3_1/F3_2 pattern in one shot, with no 225/// pattern. 226multiclass F3_12np<string OpcStr, bits<6> Op3Val> { 227 def rr : F3_1<2, Op3Val, 228 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c), 229 !strconcat(OpcStr, " $b, $c, $dst"), []>; 230 def ri : F3_2<2, Op3Val, 231 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c), 232 !strconcat(OpcStr, " $b, $c, $dst"), []>; 233} 234 235//===----------------------------------------------------------------------===// 236// Instructions 237//===----------------------------------------------------------------------===// 238 239// Pseudo instructions. 240class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern> 241 : InstSP<outs, ins, asmstr, pattern>; 242 243// GETPCX for PIC 244let Defs = [O7] in { 245 def GETPCX : Pseudo<(outs getPCX:$getpcseq), (ins), "$getpcseq", [] >; 246} 247 248let Defs = [O6], Uses = [O6] in { 249def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt), 250 "!ADJCALLSTACKDOWN $amt", 251 [(callseq_start timm:$amt)]>; 252def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2), 253 "!ADJCALLSTACKUP $amt1", 254 [(callseq_end timm:$amt1, timm:$amt2)]>; 255} 256 257let hasSideEffects = 1, mayStore = 1 in { 258 let rd = 0, rs1 = 0, rs2 = 0 in 259 def FLUSHW : F3_1<0b10, 0b101011, (outs), (ins), 260 "flushw", 261 [(flushw)]>, Requires<[HasV9]>; 262 let rd = 0, rs1 = 1, simm13 = 3 in 263 def TA3 : F3_2<0b10, 0b111010, (outs), (ins), 264 "ta 3", 265 [(flushw)]>; 266} 267 268let rd = 0 in 269 def UNIMP : F2_1<0b000, (outs), (ins i32imm:$val), 270 "unimp $val", []>; 271 272// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after 273// instruction selection into a branch sequence. This has to handle all 274// permutations of selection between i32/f32/f64 on ICC and FCC. 275// Expanded after instruction selection. 276let Uses = [ICC], usesCustomInserter = 1 in { 277 def SELECT_CC_Int_ICC 278 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond), 279 "; SELECT_CC_Int_ICC PSEUDO!", 280 [(set i32:$dst, (SPselecticc i32:$T, i32:$F, imm:$Cond))]>; 281 def SELECT_CC_FP_ICC 282 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, i32imm:$Cond), 283 "; SELECT_CC_FP_ICC PSEUDO!", 284 [(set f32:$dst, (SPselecticc f32:$T, f32:$F, imm:$Cond))]>; 285 286 def SELECT_CC_DFP_ICC 287 : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, i32imm:$Cond), 288 "; SELECT_CC_DFP_ICC PSEUDO!", 289 [(set f64:$dst, (SPselecticc f64:$T, f64:$F, imm:$Cond))]>; 290 291 def SELECT_CC_QFP_ICC 292 : Pseudo<(outs QFPRegs:$dst), (ins QFPRegs:$T, QFPRegs:$F, i32imm:$Cond), 293 "; SELECT_CC_QFP_ICC PSEUDO!", 294 [(set f128:$dst, (SPselecticc f128:$T, f128:$F, imm:$Cond))]>; 295} 296 297let usesCustomInserter = 1, Uses = [FCC] in { 298 299 def SELECT_CC_Int_FCC 300 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond), 301 "; SELECT_CC_Int_FCC PSEUDO!", 302 [(set i32:$dst, (SPselectfcc i32:$T, i32:$F, imm:$Cond))]>; 303 304 def SELECT_CC_FP_FCC 305 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, i32imm:$Cond), 306 "; SELECT_CC_FP_FCC PSEUDO!", 307 [(set f32:$dst, (SPselectfcc f32:$T, f32:$F, imm:$Cond))]>; 308 def SELECT_CC_DFP_FCC 309 : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, i32imm:$Cond), 310 "; SELECT_CC_DFP_FCC PSEUDO!", 311 [(set f64:$dst, (SPselectfcc f64:$T, f64:$F, imm:$Cond))]>; 312 def SELECT_CC_QFP_FCC 313 : Pseudo<(outs QFPRegs:$dst), (ins QFPRegs:$T, QFPRegs:$F, i32imm:$Cond), 314 "; SELECT_CC_QFP_FCC PSEUDO!", 315 [(set f128:$dst, (SPselectfcc f128:$T, f128:$F, imm:$Cond))]>; 316} 317 318 319// Section A.3 - Synthetic Instructions, p. 85 320// special cases of JMPL: 321let isReturn = 1, isTerminator = 1, hasDelaySlot = 1, isBarrier = 1 in { 322 let rd = 0, rs1 = 15 in 323 def RETL: F3_2<2, 0b111000, (outs), (ins i32imm:$val), 324 "jmp %o7+$val", [(retflag simm13:$val)]>; 325 326 let rd = 0, rs1 = 31 in 327 def RET: F3_2<2, 0b111000, (outs), (ins i32imm:$val), 328 "jmp %i7+$val", []>; 329} 330 331// Section B.1 - Load Integer Instructions, p. 90 332def LDSBrr : F3_1<3, 0b001001, 333 (outs IntRegs:$dst), (ins MEMrr:$addr), 334 "ldsb [$addr], $dst", 335 [(set i32:$dst, (sextloadi8 ADDRrr:$addr))]>; 336def LDSBri : F3_2<3, 0b001001, 337 (outs IntRegs:$dst), (ins MEMri:$addr), 338 "ldsb [$addr], $dst", 339 [(set i32:$dst, (sextloadi8 ADDRri:$addr))]>; 340def LDSHrr : F3_1<3, 0b001010, 341 (outs IntRegs:$dst), (ins MEMrr:$addr), 342 "ldsh [$addr], $dst", 343 [(set i32:$dst, (sextloadi16 ADDRrr:$addr))]>; 344def LDSHri : F3_2<3, 0b001010, 345 (outs IntRegs:$dst), (ins MEMri:$addr), 346 "ldsh [$addr], $dst", 347 [(set i32:$dst, (sextloadi16 ADDRri:$addr))]>; 348def LDUBrr : F3_1<3, 0b000001, 349 (outs IntRegs:$dst), (ins MEMrr:$addr), 350 "ldub [$addr], $dst", 351 [(set i32:$dst, (zextloadi8 ADDRrr:$addr))]>; 352def LDUBri : F3_2<3, 0b000001, 353 (outs IntRegs:$dst), (ins MEMri:$addr), 354 "ldub [$addr], $dst", 355 [(set i32:$dst, (zextloadi8 ADDRri:$addr))]>; 356def LDUHrr : F3_1<3, 0b000010, 357 (outs IntRegs:$dst), (ins MEMrr:$addr), 358 "lduh [$addr], $dst", 359 [(set i32:$dst, (zextloadi16 ADDRrr:$addr))]>; 360def LDUHri : F3_2<3, 0b000010, 361 (outs IntRegs:$dst), (ins MEMri:$addr), 362 "lduh [$addr], $dst", 363 [(set i32:$dst, (zextloadi16 ADDRri:$addr))]>; 364def LDrr : F3_1<3, 0b000000, 365 (outs IntRegs:$dst), (ins MEMrr:$addr), 366 "ld [$addr], $dst", 367 [(set i32:$dst, (load ADDRrr:$addr))]>; 368def LDri : F3_2<3, 0b000000, 369 (outs IntRegs:$dst), (ins MEMri:$addr), 370 "ld [$addr], $dst", 371 [(set i32:$dst, (load ADDRri:$addr))]>; 372 373// Section B.2 - Load Floating-point Instructions, p. 92 374def LDFrr : F3_1<3, 0b100000, 375 (outs FPRegs:$dst), (ins MEMrr:$addr), 376 "ld [$addr], $dst", 377 [(set f32:$dst, (load ADDRrr:$addr))]>; 378def LDFri : F3_2<3, 0b100000, 379 (outs FPRegs:$dst), (ins MEMri:$addr), 380 "ld [$addr], $dst", 381 [(set f32:$dst, (load ADDRri:$addr))]>; 382def LDDFrr : F3_1<3, 0b100011, 383 (outs DFPRegs:$dst), (ins MEMrr:$addr), 384 "ldd [$addr], $dst", 385 [(set f64:$dst, (load ADDRrr:$addr))]>; 386def LDDFri : F3_2<3, 0b100011, 387 (outs DFPRegs:$dst), (ins MEMri:$addr), 388 "ldd [$addr], $dst", 389 [(set f64:$dst, (load ADDRri:$addr))]>; 390def LDQFrr : F3_1<3, 0b100010, 391 (outs QFPRegs:$dst), (ins MEMrr:$addr), 392 "ldq [$addr], $dst", 393 [(set f128:$dst, (load ADDRrr:$addr))]>, 394 Requires<[HasV9, HasHardQuad]>; 395def LDQFri : F3_2<3, 0b100010, 396 (outs QFPRegs:$dst), (ins MEMri:$addr), 397 "ldq [$addr], $dst", 398 [(set f128:$dst, (load ADDRri:$addr))]>, 399 Requires<[HasV9, HasHardQuad]>; 400 401// Section B.4 - Store Integer Instructions, p. 95 402def STBrr : F3_1<3, 0b000101, 403 (outs), (ins MEMrr:$addr, IntRegs:$rd), 404 "stb $rd, [$addr]", 405 [(truncstorei8 i32:$rd, ADDRrr:$addr)]>; 406def STBri : F3_2<3, 0b000101, 407 (outs), (ins MEMri:$addr, IntRegs:$rd), 408 "stb $rd, [$addr]", 409 [(truncstorei8 i32:$rd, ADDRri:$addr)]>; 410def STHrr : F3_1<3, 0b000110, 411 (outs), (ins MEMrr:$addr, IntRegs:$rd), 412 "sth $rd, [$addr]", 413 [(truncstorei16 i32:$rd, ADDRrr:$addr)]>; 414def STHri : F3_2<3, 0b000110, 415 (outs), (ins MEMri:$addr, IntRegs:$rd), 416 "sth $rd, [$addr]", 417 [(truncstorei16 i32:$rd, ADDRri:$addr)]>; 418def STrr : F3_1<3, 0b000100, 419 (outs), (ins MEMrr:$addr, IntRegs:$rd), 420 "st $rd, [$addr]", 421 [(store i32:$rd, ADDRrr:$addr)]>; 422def STri : F3_2<3, 0b000100, 423 (outs), (ins MEMri:$addr, IntRegs:$rd), 424 "st $rd, [$addr]", 425 [(store i32:$rd, ADDRri:$addr)]>; 426 427// Section B.5 - Store Floating-point Instructions, p. 97 428def STFrr : F3_1<3, 0b100100, 429 (outs), (ins MEMrr:$addr, FPRegs:$rd), 430 "st $rd, [$addr]", 431 [(store f32:$rd, ADDRrr:$addr)]>; 432def STFri : F3_2<3, 0b100100, 433 (outs), (ins MEMri:$addr, FPRegs:$rd), 434 "st $rd, [$addr]", 435 [(store f32:$rd, ADDRri:$addr)]>; 436def STDFrr : F3_1<3, 0b100111, 437 (outs), (ins MEMrr:$addr, DFPRegs:$rd), 438 "std $rd, [$addr]", 439 [(store f64:$rd, ADDRrr:$addr)]>; 440def STDFri : F3_2<3, 0b100111, 441 (outs), (ins MEMri:$addr, DFPRegs:$rd), 442 "std $rd, [$addr]", 443 [(store f64:$rd, ADDRri:$addr)]>; 444def STQFrr : F3_1<3, 0b100110, 445 (outs), (ins MEMrr:$addr, QFPRegs:$rd), 446 "stq $rd, [$addr]", 447 [(store f128:$rd, ADDRrr:$addr)]>, 448 Requires<[HasV9, HasHardQuad]>; 449def STQFri : F3_2<3, 0b100110, 450 (outs), (ins MEMri:$addr, QFPRegs:$rd), 451 "stq $rd, [$addr]", 452 [(store f128:$rd, ADDRri:$addr)]>, 453 Requires<[HasV9, HasHardQuad]>; 454 455// Section B.9 - SETHI Instruction, p. 104 456def SETHIi: F2_1<0b100, 457 (outs IntRegs:$rd), (ins i32imm:$imm22), 458 "sethi $imm22, $rd", 459 [(set i32:$rd, SETHIimm:$imm22)]>; 460 461// Section B.10 - NOP Instruction, p. 105 462// (It's a special case of SETHI) 463let rd = 0, imm22 = 0 in 464 def NOP : F2_1<0b100, (outs), (ins), "nop", []>; 465 466// Section B.11 - Logical Instructions, p. 106 467defm AND : F3_12<"and", 0b000001, and>; 468 469def ANDNrr : F3_1<2, 0b000101, 470 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c), 471 "andn $b, $c, $dst", 472 [(set i32:$dst, (and i32:$b, (not i32:$c)))]>; 473def ANDNri : F3_2<2, 0b000101, 474 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c), 475 "andn $b, $c, $dst", []>; 476 477defm OR : F3_12<"or", 0b000010, or>; 478 479def ORNrr : F3_1<2, 0b000110, 480 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c), 481 "orn $b, $c, $dst", 482 [(set i32:$dst, (or i32:$b, (not i32:$c)))]>; 483def ORNri : F3_2<2, 0b000110, 484 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c), 485 "orn $b, $c, $dst", []>; 486defm XOR : F3_12<"xor", 0b000011, xor>; 487 488def XNORrr : F3_1<2, 0b000111, 489 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c), 490 "xnor $b, $c, $dst", 491 [(set i32:$dst, (not (xor i32:$b, i32:$c)))]>; 492def XNORri : F3_2<2, 0b000111, 493 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c), 494 "xnor $b, $c, $dst", []>; 495 496// Section B.12 - Shift Instructions, p. 107 497defm SLL : F3_12<"sll", 0b100101, shl>; 498defm SRL : F3_12<"srl", 0b100110, srl>; 499defm SRA : F3_12<"sra", 0b100111, sra>; 500 501// Section B.13 - Add Instructions, p. 108 502defm ADD : F3_12<"add", 0b000000, add>; 503 504// "LEA" forms of add (patterns to make tblgen happy) 505let Predicates = [Is32Bit] in 506 def LEA_ADDri : F3_2<2, 0b000000, 507 (outs IntRegs:$dst), (ins MEMri:$addr), 508 "add ${addr:arith}, $dst", 509 [(set iPTR:$dst, ADDRri:$addr)]>; 510 511let Defs = [ICC] in 512 defm ADDCC : F3_12<"addcc", 0b010000, addc>; 513 514let Uses = [ICC], Defs = [ICC] in 515 defm ADDX : F3_12<"addxcc", 0b011000, adde>; 516 517// Section B.15 - Subtract Instructions, p. 110 518defm SUB : F3_12 <"sub" , 0b000100, sub>; 519let Uses = [ICC], Defs = [ICC] in 520 defm SUBX : F3_12 <"subxcc" , 0b011100, sube>; 521 522let Defs = [ICC] in 523 defm SUBCC : F3_12 <"subcc", 0b010100, subc>; 524 525let Defs = [ICC], rd = 0 in { 526 def CMPrr : F3_1<2, 0b010100, 527 (outs), (ins IntRegs:$b, IntRegs:$c), 528 "cmp $b, $c", 529 [(SPcmpicc i32:$b, i32:$c)]>; 530 def CMPri : F3_2<2, 0b010100, 531 (outs), (ins IntRegs:$b, i32imm:$c), 532 "cmp $b, $c", 533 [(SPcmpicc i32:$b, (i32 simm13:$c))]>; 534} 535 536let Uses = [ICC], Defs = [ICC] in 537 def SUBXCCrr: F3_1<2, 0b011100, 538 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c), 539 "subxcc $b, $c, $dst", []>; 540 541 542// Section B.18 - Multiply Instructions, p. 113 543let Defs = [Y] in { 544 defm UMUL : F3_12np<"umul", 0b001010>; 545 defm SMUL : F3_12 <"smul", 0b001011, mul>; 546} 547 548// Section B.19 - Divide Instructions, p. 115 549let Defs = [Y] in { 550 defm UDIV : F3_12np<"udiv", 0b001110>; 551 defm SDIV : F3_12np<"sdiv", 0b001111>; 552} 553 554// Section B.20 - SAVE and RESTORE, p. 117 555defm SAVE : F3_12np<"save" , 0b111100>; 556defm RESTORE : F3_12np<"restore", 0b111101>; 557 558// Section B.21 - Branch on Integer Condition Codes Instructions, p. 119 559 560// unconditional branch class. 561class BranchAlways<dag ins, string asmstr, list<dag> pattern> 562 : F2_2<0b010, (outs), ins, asmstr, pattern> { 563 let isBranch = 1; 564 let isTerminator = 1; 565 let hasDelaySlot = 1; 566 let isBarrier = 1; 567} 568 569let cond = 8 in 570 def BA : BranchAlways<(ins brtarget:$imm22), "ba $imm22", [(br bb:$imm22)]>; 571 572// conditional branch class: 573class BranchSP<dag ins, string asmstr, list<dag> pattern> 574 : F2_2<0b010, (outs), ins, asmstr, pattern> { 575 let isBranch = 1; 576 let isTerminator = 1; 577 let hasDelaySlot = 1; 578} 579 580// Indirect branch instructions. 581let isTerminator = 1, isBarrier = 1, 582 hasDelaySlot = 1, isBranch =1, 583 isIndirectBranch = 1, rd = 0 in { 584 def BINDrr : F3_1<2, 0b111000, 585 (outs), (ins MEMrr:$ptr), 586 "jmp $ptr", 587 [(brind ADDRrr:$ptr)]>; 588 def BINDri : F3_2<2, 0b111000, 589 (outs), (ins MEMri:$ptr), 590 "jmp $ptr", 591 [(brind ADDRri:$ptr)]>; 592} 593 594let Uses = [ICC] in 595 def BCOND : BranchSP<(ins brtarget:$imm22, CCOp:$cond), 596 "b$cond $imm22", 597 [(SPbricc bb:$imm22, imm:$cond)]>; 598 599// Section B.22 - Branch on Floating-point Condition Codes Instructions, p. 121 600 601// floating-point conditional branch class: 602class FPBranchSP<dag ins, string asmstr, list<dag> pattern> 603 : F2_2<0b110, (outs), ins, asmstr, pattern> { 604 let isBranch = 1; 605 let isTerminator = 1; 606 let hasDelaySlot = 1; 607} 608 609let Uses = [FCC] in 610 def FBCOND : FPBranchSP<(ins brtarget:$imm22, CCOp:$cond), 611 "fb$cond $imm22", 612 [(SPbrfcc bb:$imm22, imm:$cond)]>; 613 614 615// Section B.24 - Call and Link Instruction, p. 125 616// This is the only Format 1 instruction 617let Uses = [O6], 618 hasDelaySlot = 1, isCall = 1 in { 619 def CALL : InstSP<(outs), (ins calltarget:$dst, variable_ops), 620 "call $dst", []> { 621 bits<30> disp; 622 let op = 1; 623 let Inst{29-0} = disp; 624 } 625 626 // indirect calls 627 def JMPLrr : F3_1<2, 0b111000, 628 (outs), (ins MEMrr:$ptr, variable_ops), 629 "call $ptr", 630 [(call ADDRrr:$ptr)]> { let rd = 15; } 631 def JMPLri : F3_2<2, 0b111000, 632 (outs), (ins MEMri:$ptr, variable_ops), 633 "call $ptr", 634 [(call ADDRri:$ptr)]> { let rd = 15; } 635} 636 637// Section B.28 - Read State Register Instructions 638let Uses = [Y], rs1 = 0, rs2 = 0 in 639 def RDY : F3_1<2, 0b101000, 640 (outs IntRegs:$dst), (ins), 641 "rd %y, $dst", []>; 642 643// Section B.29 - Write State Register Instructions 644let Defs = [Y], rd = 0 in { 645 def WRYrr : F3_1<2, 0b110000, 646 (outs), (ins IntRegs:$b, IntRegs:$c), 647 "wr $b, $c, %y", []>; 648 def WRYri : F3_2<2, 0b110000, 649 (outs), (ins IntRegs:$b, i32imm:$c), 650 "wr $b, $c, %y", []>; 651} 652// Convert Integer to Floating-point Instructions, p. 141 653def FITOS : F3_3u<2, 0b110100, 0b011000100, 654 (outs FPRegs:$dst), (ins FPRegs:$src), 655 "fitos $src, $dst", 656 [(set FPRegs:$dst, (SPitof FPRegs:$src))]>; 657def FITOD : F3_3u<2, 0b110100, 0b011001000, 658 (outs DFPRegs:$dst), (ins FPRegs:$src), 659 "fitod $src, $dst", 660 [(set DFPRegs:$dst, (SPitof FPRegs:$src))]>; 661def FITOQ : F3_3u<2, 0b110100, 0b011001100, 662 (outs QFPRegs:$dst), (ins FPRegs:$src), 663 "fitoq $src, $dst", 664 [(set QFPRegs:$dst, (SPitof FPRegs:$src))]>, 665 Requires<[HasHardQuad]>; 666 667// Convert Floating-point to Integer Instructions, p. 142 668def FSTOI : F3_3u<2, 0b110100, 0b011010001, 669 (outs FPRegs:$dst), (ins FPRegs:$src), 670 "fstoi $src, $dst", 671 [(set FPRegs:$dst, (SPftoi FPRegs:$src))]>; 672def FDTOI : F3_3u<2, 0b110100, 0b011010010, 673 (outs FPRegs:$dst), (ins DFPRegs:$src), 674 "fdtoi $src, $dst", 675 [(set FPRegs:$dst, (SPftoi DFPRegs:$src))]>; 676def FQTOI : F3_3u<2, 0b110100, 0b011010011, 677 (outs FPRegs:$dst), (ins QFPRegs:$src), 678 "fqtoi $src, $dst", 679 [(set FPRegs:$dst, (SPftoi QFPRegs:$src))]>, 680 Requires<[HasHardQuad]>; 681 682// Convert between Floating-point Formats Instructions, p. 143 683def FSTOD : F3_3u<2, 0b110100, 0b011001001, 684 (outs DFPRegs:$dst), (ins FPRegs:$src), 685 "fstod $src, $dst", 686 [(set f64:$dst, (fextend f32:$src))]>; 687def FSTOQ : F3_3u<2, 0b110100, 0b011001101, 688 (outs QFPRegs:$dst), (ins FPRegs:$src), 689 "fstoq $src, $dst", 690 [(set f128:$dst, (fextend f32:$src))]>, 691 Requires<[HasHardQuad]>; 692def FDTOS : F3_3u<2, 0b110100, 0b011000110, 693 (outs FPRegs:$dst), (ins DFPRegs:$src), 694 "fdtos $src, $dst", 695 [(set f32:$dst, (fround f64:$src))]>; 696def FDTOQ : F3_3u<2, 0b110100, 0b01101110, 697 (outs QFPRegs:$dst), (ins DFPRegs:$src), 698 "fdtoq $src, $dst", 699 [(set f128:$dst, (fextend f64:$src))]>, 700 Requires<[HasHardQuad]>; 701def FQTOS : F3_3u<2, 0b110100, 0b011000111, 702 (outs FPRegs:$dst), (ins QFPRegs:$src), 703 "fqtos $src, $dst", 704 [(set f32:$dst, (fround f128:$src))]>, 705 Requires<[HasHardQuad]>; 706def FQTOD : F3_3u<2, 0b110100, 0b011001011, 707 (outs DFPRegs:$dst), (ins QFPRegs:$src), 708 "fqtod $src, $dst", 709 [(set f64:$dst, (fround f128:$src))]>, 710 Requires<[HasHardQuad]>; 711 712// Floating-point Move Instructions, p. 144 713def FMOVS : F3_3u<2, 0b110100, 0b000000001, 714 (outs FPRegs:$dst), (ins FPRegs:$src), 715 "fmovs $src, $dst", []>; 716def FNEGS : F3_3u<2, 0b110100, 0b000000101, 717 (outs FPRegs:$dst), (ins FPRegs:$src), 718 "fnegs $src, $dst", 719 [(set f32:$dst, (fneg f32:$src))]>; 720def FABSS : F3_3u<2, 0b110100, 0b000001001, 721 (outs FPRegs:$dst), (ins FPRegs:$src), 722 "fabss $src, $dst", 723 [(set f32:$dst, (fabs f32:$src))]>; 724 725 726// Floating-point Square Root Instructions, p.145 727def FSQRTS : F3_3u<2, 0b110100, 0b000101001, 728 (outs FPRegs:$dst), (ins FPRegs:$src), 729 "fsqrts $src, $dst", 730 [(set f32:$dst, (fsqrt f32:$src))]>; 731def FSQRTD : F3_3u<2, 0b110100, 0b000101010, 732 (outs DFPRegs:$dst), (ins DFPRegs:$src), 733 "fsqrtd $src, $dst", 734 [(set f64:$dst, (fsqrt f64:$src))]>; 735def FSQRTQ : F3_3u<2, 0b110100, 0b000101011, 736 (outs QFPRegs:$dst), (ins QFPRegs:$src), 737 "fsqrtq $src, $dst", 738 [(set f128:$dst, (fsqrt f128:$src))]>, 739 Requires<[HasHardQuad]>; 740 741 742 743// Floating-point Add and Subtract Instructions, p. 146 744def FADDS : F3_3<2, 0b110100, 0b001000001, 745 (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2), 746 "fadds $src1, $src2, $dst", 747 [(set f32:$dst, (fadd f32:$src1, f32:$src2))]>; 748def FADDD : F3_3<2, 0b110100, 0b001000010, 749 (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2), 750 "faddd $src1, $src2, $dst", 751 [(set f64:$dst, (fadd f64:$src1, f64:$src2))]>; 752def FADDQ : F3_3<2, 0b110100, 0b001000011, 753 (outs QFPRegs:$dst), (ins QFPRegs:$src1, QFPRegs:$src2), 754 "faddq $src1, $src2, $dst", 755 [(set f128:$dst, (fadd f128:$src1, f128:$src2))]>, 756 Requires<[HasHardQuad]>; 757 758def FSUBS : F3_3<2, 0b110100, 0b001000101, 759 (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2), 760 "fsubs $src1, $src2, $dst", 761 [(set f32:$dst, (fsub f32:$src1, f32:$src2))]>; 762def FSUBD : F3_3<2, 0b110100, 0b001000110, 763 (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2), 764 "fsubd $src1, $src2, $dst", 765 [(set f64:$dst, (fsub f64:$src1, f64:$src2))]>; 766def FSUBQ : F3_3<2, 0b110100, 0b001000111, 767 (outs QFPRegs:$dst), (ins QFPRegs:$src1, QFPRegs:$src2), 768 "fsubq $src1, $src2, $dst", 769 [(set f128:$dst, (fsub f128:$src1, f128:$src2))]>, 770 Requires<[HasHardQuad]>; 771 772 773// Floating-point Multiply and Divide Instructions, p. 147 774def FMULS : F3_3<2, 0b110100, 0b001001001, 775 (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2), 776 "fmuls $src1, $src2, $dst", 777 [(set f32:$dst, (fmul f32:$src1, f32:$src2))]>; 778def FMULD : F3_3<2, 0b110100, 0b001001010, 779 (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2), 780 "fmuld $src1, $src2, $dst", 781 [(set f64:$dst, (fmul f64:$src1, f64:$src2))]>; 782def FMULQ : F3_3<2, 0b110100, 0b001001011, 783 (outs QFPRegs:$dst), (ins QFPRegs:$src1, QFPRegs:$src2), 784 "fmulq $src1, $src2, $dst", 785 [(set f128:$dst, (fmul f128:$src1, f128:$src2))]>, 786 Requires<[HasHardQuad]>; 787 788def FSMULD : F3_3<2, 0b110100, 0b001101001, 789 (outs DFPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2), 790 "fsmuld $src1, $src2, $dst", 791 [(set f64:$dst, (fmul (fextend f32:$src1), 792 (fextend f32:$src2)))]>; 793def FDMULQ : F3_3<2, 0b110100, 0b001101110, 794 (outs QFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2), 795 "fdmulq $src1, $src2, $dst", 796 [(set f128:$dst, (fmul (fextend f64:$src1), 797 (fextend f64:$src2)))]>, 798 Requires<[HasHardQuad]>; 799 800def FDIVS : F3_3<2, 0b110100, 0b001001101, 801 (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2), 802 "fdivs $src1, $src2, $dst", 803 [(set f32:$dst, (fdiv f32:$src1, f32:$src2))]>; 804def FDIVD : F3_3<2, 0b110100, 0b001001110, 805 (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2), 806 "fdivd $src1, $src2, $dst", 807 [(set f64:$dst, (fdiv f64:$src1, f64:$src2))]>; 808def FDIVQ : F3_3<2, 0b110100, 0b001001111, 809 (outs QFPRegs:$dst), (ins QFPRegs:$src1, QFPRegs:$src2), 810 "fdivq $src1, $src2, $dst", 811 [(set f128:$dst, (fdiv f128:$src1, f128:$src2))]>, 812 Requires<[HasHardQuad]>; 813 814// Floating-point Compare Instructions, p. 148 815// Note: the 2nd template arg is different for these guys. 816// Note 2: the result of a FCMP is not available until the 2nd cycle 817// after the instr is retired, but there is no interlock in Sparc V8. 818// This behavior is modeled with a forced noop after the instruction in 819// DelaySlotFiller. 820 821let Defs = [FCC] in { 822 def FCMPS : F3_3c<2, 0b110101, 0b001010001, 823 (outs), (ins FPRegs:$src1, FPRegs:$src2), 824 "fcmps $src1, $src2", 825 [(SPcmpfcc f32:$src1, f32:$src2)]>; 826 def FCMPD : F3_3c<2, 0b110101, 0b001010010, 827 (outs), (ins DFPRegs:$src1, DFPRegs:$src2), 828 "fcmpd $src1, $src2", 829 [(SPcmpfcc f64:$src1, f64:$src2)]>; 830 def FCMPQ : F3_3c<2, 0b110101, 0b001010011, 831 (outs), (ins QFPRegs:$src1, QFPRegs:$src2), 832 "fcmpq $src1, $src2", 833 [(SPcmpfcc f128:$src1, f128:$src2)]>, 834 Requires<[HasHardQuad]>; 835} 836 837//===----------------------------------------------------------------------===// 838// Instructions for Thread Local Storage(TLS). 839//===----------------------------------------------------------------------===// 840 841def TLS_ADDrr : F3_1<2, 0b000000, 842 (outs IntRegs:$rd), 843 (ins IntRegs:$rs1, IntRegs:$rs2, TLSSym:$sym), 844 "add $rs1, $rs2, $rd, $sym", 845 [(set i32:$rd, 846 (tlsadd i32:$rs1, i32:$rs2, tglobaltlsaddr:$sym))]>; 847 848let mayLoad = 1 in 849 def TLS_LDrr : F3_1<3, 0b000000, 850 (outs IntRegs:$dst), (ins MEMrr:$addr, TLSSym:$sym), 851 "ld [$addr], $dst, $sym", 852 [(set i32:$dst, 853 (tlsld ADDRrr:$addr, tglobaltlsaddr:$sym))]>; 854 855let Uses = [O6], isCall = 1, hasDelaySlot = 1 in 856 def TLS_CALL : InstSP<(outs), 857 (ins calltarget:$disp, TLSSym:$sym, variable_ops), 858 "call $disp, $sym", 859 [(tlscall texternalsym:$disp, tglobaltlsaddr:$sym)]> { 860 bits<30> disp; 861 let op = 1; 862 let Inst{29-0} = disp; 863} 864 865//===----------------------------------------------------------------------===// 866// V9 Instructions 867//===----------------------------------------------------------------------===// 868 869// V9 Conditional Moves. 870let Predicates = [HasV9], Constraints = "$f = $rd" in { 871 // Move Integer Register on Condition (MOVcc) p. 194 of the V9 manual. 872 let Uses = [ICC], cc = 0b100 in { 873 def MOVICCrr 874 : F4_1<0b101100, (outs IntRegs:$rd), 875 (ins IntRegs:$rs2, IntRegs:$f, CCOp:$cond), 876 "mov$cond %icc, $rs2, $rd", 877 [(set i32:$rd, (SPselecticc i32:$rs2, i32:$f, imm:$cond))]>; 878 879 def MOVICCri 880 : F4_2<0b101100, (outs IntRegs:$rd), 881 (ins i32imm:$simm11, IntRegs:$f, CCOp:$cond), 882 "mov$cond %icc, $simm11, $rd", 883 [(set i32:$rd, 884 (SPselecticc simm11:$simm11, i32:$f, imm:$cond))]>; 885 } 886 887 let Uses = [FCC], cc = 0b000 in { 888 def MOVFCCrr 889 : F4_1<0b101100, (outs IntRegs:$rd), 890 (ins IntRegs:$rs2, IntRegs:$f, CCOp:$cond), 891 "mov$cond %fcc0, $rs2, $rd", 892 [(set i32:$rd, (SPselectfcc i32:$rs2, i32:$f, imm:$cond))]>; 893 def MOVFCCri 894 : F4_2<0b101100, (outs IntRegs:$rd), 895 (ins i32imm:$simm11, IntRegs:$f, CCOp:$cond), 896 "mov$cond %fcc0, $simm11, $rd", 897 [(set i32:$rd, 898 (SPselectfcc simm11:$simm11, i32:$f, imm:$cond))]>; 899 } 900 901 let Uses = [ICC], opf_cc = 0b100 in { 902 def FMOVS_ICC 903 : F4_3<0b110101, 0b000001, (outs FPRegs:$rd), 904 (ins FPRegs:$rs2, FPRegs:$f, CCOp:$cond), 905 "fmovs$cond %icc, $rs2, $rd", 906 [(set f32:$rd, (SPselecticc f32:$rs2, f32:$f, imm:$cond))]>; 907 def FMOVD_ICC 908 : F4_3<0b110101, 0b000010, (outs DFPRegs:$rd), 909 (ins DFPRegs:$rs2, DFPRegs:$f, CCOp:$cond), 910 "fmovd$cond %icc, $rs2, $rd", 911 [(set f64:$rd, (SPselecticc f64:$rs2, f64:$f, imm:$cond))]>; 912 def FMOVQ_ICC 913 : F4_3<0b110101, 0b000011, (outs QFPRegs:$rd), 914 (ins QFPRegs:$rs2, QFPRegs:$f, CCOp:$cond), 915 "fmovd$cond %icc, $rs2, $rd", 916 [(set f128:$rd, (SPselecticc f128:$rs2, f128:$f, imm:$cond))]>; 917 } 918 919 let Uses = [FCC], opf_cc = 0b000 in { 920 def FMOVS_FCC 921 : F4_3<0b110101, 0b000001, (outs FPRegs:$rd), 922 (ins FPRegs:$rs2, FPRegs:$f, CCOp:$cond), 923 "fmovs$cond %fcc0, $rs2, $rd", 924 [(set f32:$rd, (SPselectfcc f32:$rs2, f32:$f, imm:$cond))]>; 925 def FMOVD_FCC 926 : F4_3<0b110101, 0b000010, (outs DFPRegs:$rd), 927 (ins DFPRegs:$rs2, DFPRegs:$f, CCOp:$cond), 928 "fmovd$cond %fcc0, $rs2, $rd", 929 [(set f64:$rd, (SPselectfcc f64:$rs2, f64:$f, imm:$cond))]>; 930 def FMOVQ_FCC 931 : F4_3<0b110101, 0b000011, (outs QFPRegs:$rd), 932 (ins QFPRegs:$rs2, QFPRegs:$f, CCOp:$cond), 933 "fmovd$cond %fcc0, $rs2, $rd", 934 [(set f128:$rd, (SPselectfcc f128:$rs2, f128:$f, imm:$cond))]>; 935 } 936 937} 938 939// Floating-Point Move Instructions, p. 164 of the V9 manual. 940let Predicates = [HasV9] in { 941 def FMOVD : F3_3u<2, 0b110100, 0b000000010, 942 (outs DFPRegs:$dst), (ins DFPRegs:$src), 943 "fmovd $src, $dst", []>; 944 def FMOVQ : F3_3u<2, 0b110100, 0b000000011, 945 (outs QFPRegs:$dst), (ins QFPRegs:$src), 946 "fmovq $src, $dst", []>, 947 Requires<[HasHardQuad]>; 948 def FNEGD : F3_3u<2, 0b110100, 0b000000110, 949 (outs DFPRegs:$dst), (ins DFPRegs:$src), 950 "fnegd $src, $dst", 951 [(set f64:$dst, (fneg f64:$src))]>; 952 def FNEGQ : F3_3u<2, 0b110100, 0b000000111, 953 (outs QFPRegs:$dst), (ins QFPRegs:$src), 954 "fnegq $src, $dst", 955 [(set f128:$dst, (fneg f128:$src))]>, 956 Requires<[HasHardQuad]>; 957 def FABSD : F3_3u<2, 0b110100, 0b000001010, 958 (outs DFPRegs:$dst), (ins DFPRegs:$src), 959 "fabsd $src, $dst", 960 [(set f64:$dst, (fabs f64:$src))]>; 961 def FABSQ : F3_3u<2, 0b110100, 0b000001011, 962 (outs QFPRegs:$dst), (ins QFPRegs:$src), 963 "fabsq $src, $dst", 964 [(set f128:$dst, (fabs f128:$src))]>, 965 Requires<[HasHardQuad]>; 966} 967 968// POPCrr - This does a ctpop of a 64-bit register. As such, we have to clear 969// the top 32-bits before using it. To do this clearing, we use a SLLri X,0. 970let rs1 = 0 in 971 def POPCrr : F3_1<2, 0b101110, 972 (outs IntRegs:$dst), (ins IntRegs:$src), 973 "popc $src, $dst", []>, Requires<[HasV9]>; 974def : Pat<(ctpop i32:$src), 975 (POPCrr (SLLri $src, 0))>; 976 977//===----------------------------------------------------------------------===// 978// Non-Instruction Patterns 979//===----------------------------------------------------------------------===// 980 981// Small immediates. 982def : Pat<(i32 simm13:$val), 983 (ORri (i32 G0), imm:$val)>; 984// Arbitrary immediates. 985def : Pat<(i32 imm:$val), 986 (ORri (SETHIi (HI22 imm:$val)), (LO10 imm:$val))>; 987 988 989// Global addresses, constant pool entries 990def : Pat<(SPhi tglobaladdr:$in), (SETHIi tglobaladdr:$in)>; 991def : Pat<(SPlo tglobaladdr:$in), (ORri (i32 G0), tglobaladdr:$in)>; 992def : Pat<(SPhi tconstpool:$in), (SETHIi tconstpool:$in)>; 993def : Pat<(SPlo tconstpool:$in), (ORri (i32 G0), tconstpool:$in)>; 994 995// GlobalTLS addresses 996def : Pat<(SPhi tglobaltlsaddr:$in), (SETHIi tglobaltlsaddr:$in)>; 997def : Pat<(SPlo tglobaltlsaddr:$in), (ORri (i32 G0), tglobaltlsaddr:$in)>; 998def : Pat<(add (SPhi tglobaltlsaddr:$in1), (SPlo tglobaltlsaddr:$in2)), 999 (ADDri (SETHIi tglobaltlsaddr:$in1), (tglobaltlsaddr:$in2))>; 1000def : Pat<(xor (SPhi tglobaltlsaddr:$in1), (SPlo tglobaltlsaddr:$in2)), 1001 (XORri (SETHIi tglobaltlsaddr:$in1), (tglobaltlsaddr:$in2))>; 1002 1003// Blockaddress 1004def : Pat<(SPhi tblockaddress:$in), (SETHIi tblockaddress:$in)>; 1005def : Pat<(SPlo tblockaddress:$in), (ORri (i32 G0), tblockaddress:$in)>; 1006 1007// Add reg, lo. This is used when taking the addr of a global/constpool entry. 1008def : Pat<(add iPTR:$r, (SPlo tglobaladdr:$in)), (ADDri $r, tglobaladdr:$in)>; 1009def : Pat<(add iPTR:$r, (SPlo tconstpool:$in)), (ADDri $r, tconstpool:$in)>; 1010def : Pat<(add iPTR:$r, (SPlo tblockaddress:$in)), 1011 (ADDri $r, tblockaddress:$in)>; 1012 1013// Calls: 1014def : Pat<(call tglobaladdr:$dst), 1015 (CALL tglobaladdr:$dst)>; 1016def : Pat<(call texternalsym:$dst), 1017 (CALL texternalsym:$dst)>; 1018 1019// Map integer extload's to zextloads. 1020def : Pat<(i32 (extloadi1 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>; 1021def : Pat<(i32 (extloadi1 ADDRri:$src)), (LDUBri ADDRri:$src)>; 1022def : Pat<(i32 (extloadi8 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>; 1023def : Pat<(i32 (extloadi8 ADDRri:$src)), (LDUBri ADDRri:$src)>; 1024def : Pat<(i32 (extloadi16 ADDRrr:$src)), (LDUHrr ADDRrr:$src)>; 1025def : Pat<(i32 (extloadi16 ADDRri:$src)), (LDUHri ADDRri:$src)>; 1026 1027// zextload bool -> zextload byte 1028def : Pat<(i32 (zextloadi1 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>; 1029def : Pat<(i32 (zextloadi1 ADDRri:$src)), (LDUBri ADDRri:$src)>; 1030 1031// store 0, addr -> store %g0, addr 1032def : Pat<(store (i32 0), ADDRrr:$dst), (STrr ADDRrr:$dst, (i32 G0))>; 1033def : Pat<(store (i32 0), ADDRri:$dst), (STri ADDRri:$dst, (i32 G0))>; 1034 1035include "SparcInstr64Bit.td" 1036