SparcInstrInfo.td revision 2b4ea795a23ff9d900b9e1f26c92975ef78db1b6
1//===- SparcV8Instrs.td - Target Description for SparcV8 Target -----------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the SparcV8 instructions in TableGen format. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// Instruction format superclass 16//===----------------------------------------------------------------------===// 17 18include "SparcV8InstrFormats.td" 19 20//===----------------------------------------------------------------------===// 21// Instruction Pattern Stuff 22//===----------------------------------------------------------------------===// 23 24def simm13 : PatLeaf<(imm), [{ 25 // simm13 predicate - True if the imm fits in a 13-bit sign extended field. 26 return (((int)N->getValue() << (32-13)) >> (32-13)) == (int)N->getValue(); 27}]>; 28 29def LO10 : SDNodeXForm<imm, [{ 30 return CurDAG->getTargetConstant((unsigned)N->getValue() & 1023, MVT::i32); 31}]>; 32 33def HI22 : SDNodeXForm<imm, [{ 34 // Transformation function: shift the immediate value down into the low bits. 35 return CurDAG->getTargetConstant((unsigned)N->getValue() >> 10, MVT::i32); 36}]>; 37 38def SETHIimm : PatLeaf<(imm), [{ 39 return (((unsigned)N->getValue() >> 10) << 10) == (unsigned)N->getValue(); 40}], HI22>; 41 42// Addressing modes. 43def ADDRrr : ComplexPattern<i32, 2, "SelectADDRrr", []>; 44def ADDRri : ComplexPattern<i32, 2, "SelectADDRri", []>; 45 46// Address operands 47def MEMrr : Operand<i32> { 48 let PrintMethod = "printMemOperand"; 49 let NumMIOperands = 2; 50 let MIOperandInfo = (ops IntRegs, IntRegs); 51} 52def MEMri : Operand<i32> { 53 let PrintMethod = "printMemOperand"; 54 let NumMIOperands = 2; 55 let MIOperandInfo = (ops IntRegs, i32imm); 56} 57 58// Branch targets have OtherVT type. 59def brtarget : Operand<OtherVT>; 60def calltarget : Operand<i32>; 61 62def SDTV8cmpicc : 63SDTypeProfile<1, 2, [SDTCisVT<0, FlagVT>, SDTCisInt<1>, SDTCisSameAs<1, 2>]>; 64def SDTV8cmpfcc : 65SDTypeProfile<1, 2, [SDTCisVT<0, FlagVT>, SDTCisFP<1>, SDTCisSameAs<1, 2>]>; 66def SDTV8brcc : 67SDTypeProfile<0, 3, [SDTCisVT<0, OtherVT>, SDTCisVT<1, OtherVT>, 68 SDTCisVT<2, FlagVT>]>; 69def SDTV8selectcc : 70SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, 71 SDTCisVT<3, i32>, SDTCisVT<4, FlagVT>]>; 72def SDTV8FTOI : 73SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisFP<1>]>; 74def SDTV8ITOF : 75SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f32>]>; 76 77def V8cmpicc : SDNode<"V8ISD::CMPICC", SDTV8cmpicc>; 78def V8cmpfcc : SDNode<"V8ISD::CMPFCC", SDTV8cmpfcc>; 79def V8bricc : SDNode<"V8ISD::BRICC", SDTV8brcc, [SDNPHasChain]>; 80def V8brfcc : SDNode<"V8ISD::BRFCC", SDTV8brcc, [SDNPHasChain]>; 81 82def V8hi : SDNode<"V8ISD::Hi", SDTIntUnaryOp>; 83def V8lo : SDNode<"V8ISD::Lo", SDTIntUnaryOp>; 84 85def V8ftoi : SDNode<"V8ISD::FTOI", SDTV8FTOI>; 86def V8itof : SDNode<"V8ISD::ITOF", SDTV8ITOF>; 87 88def V8selecticc : SDNode<"V8ISD::SELECT_ICC", SDTV8selectcc>; 89def V8selectfcc : SDNode<"V8ISD::SELECT_FCC", SDTV8selectcc>; 90 91// These are target-independent nodes, but have target-specific formats. 92def SDT_V8CallSeq : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>; 93def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_V8CallSeq, [SDNPHasChain]>; 94def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_V8CallSeq, [SDNPHasChain]>; 95 96def SDT_V8Call : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>; 97def call : SDNode<"ISD::CALL", SDT_V8Call, [SDNPHasChain]>; 98 99def SDT_V8RetFlag : SDTypeProfile<0, 0, []>; 100def retflag : SDNode<"V8ISD::RET_FLAG", SDT_V8RetFlag, [SDNPHasChain]>; 101 102//===----------------------------------------------------------------------===// 103// Instructions 104//===----------------------------------------------------------------------===// 105 106// Pseudo instructions. 107class Pseudo<dag ops, string asmstr, list<dag> pattern> 108 : InstV8<ops, asmstr, pattern>; 109 110def PHI : Pseudo<(ops variable_ops), "PHI", []>; 111def ADJCALLSTACKDOWN : Pseudo<(ops i32imm:$amt), 112 "!ADJCALLSTACKDOWN $amt", 113 [(callseq_start imm:$amt)]>; 114def ADJCALLSTACKUP : Pseudo<(ops i32imm:$amt), 115 "!ADJCALLSTACKUP $amt", 116 [(callseq_end imm:$amt)]>; 117def IMPLICIT_DEF_Int : Pseudo<(ops IntRegs:$dst), 118 "!IMPLICIT_DEF $dst", 119 [(set IntRegs:$dst, (undef))]>; 120def IMPLICIT_DEF_FP : Pseudo<(ops FPRegs:$dst), "!IMPLICIT_DEF $dst", 121 [(set FPRegs:$dst, (undef))]>; 122def IMPLICIT_DEF_DFP : Pseudo<(ops DFPRegs:$dst), "!IMPLICIT_DEF $dst", 123 [(set DFPRegs:$dst, (undef))]>; 124 125// FpMOVD/FpNEGD/FpABSD - These are lowered to single-precision ops by the 126// fpmover pass. 127def FpMOVD : Pseudo<(ops DFPRegs:$dst, DFPRegs:$src), 128 "!FpMOVD $src, $dst", []>; // pseudo 64-bit double move 129def FpNEGD : Pseudo<(ops DFPRegs:$dst, DFPRegs:$src), 130 "!FpNEGD $src, $dst", 131 [(set DFPRegs:$dst, (fneg DFPRegs:$src))]>; 132def FpABSD : Pseudo<(ops DFPRegs:$dst, DFPRegs:$src), 133 "!FpABSD $src, $dst", 134 [(set DFPRegs:$dst, (fabs DFPRegs:$src))]>; 135 136// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded by the 137// scheduler into a branch sequence. This has to handle all permutations of 138// selection between i32/f32/f64 on ICC and FCC. 139let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler. 140 def SELECT_CC_Int_ICC 141 : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F, i32imm:$Cond), 142 "; SELECT_CC_Int_ICC PSEUDO!", 143 [(set IntRegs:$dst, (V8selecticc IntRegs:$T, IntRegs:$F, 144 imm:$Cond, ICC))]>; 145 def SELECT_CC_Int_FCC 146 : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F, i32imm:$Cond), 147 "; SELECT_CC_Int_FCC PSEUDO!", 148 [(set IntRegs:$dst, (V8selectfcc IntRegs:$T, IntRegs:$F, 149 imm:$Cond, FCC))]>; 150 def SELECT_CC_FP_ICC 151 : Pseudo<(ops FPRegs:$dst, FPRegs:$T, FPRegs:$F, i32imm:$Cond), 152 "; SELECT_CC_FP_ICC PSEUDO!", 153 [(set FPRegs:$dst, (V8selecticc FPRegs:$T, FPRegs:$F, 154 imm:$Cond, ICC))]>; 155 def SELECT_CC_FP_FCC 156 : Pseudo<(ops FPRegs:$dst, FPRegs:$T, FPRegs:$F, i32imm:$Cond), 157 "; SELECT_CC_FP_FCC PSEUDO!", 158 [(set FPRegs:$dst, (V8selectfcc FPRegs:$T, FPRegs:$F, 159 imm:$Cond, FCC))]>; 160 def SELECT_CC_DFP_ICC 161 : Pseudo<(ops DFPRegs:$dst, DFPRegs:$T, DFPRegs:$F, i32imm:$Cond), 162 "; SELECT_CC_DFP_ICC PSEUDO!", 163 [(set DFPRegs:$dst, (V8selecticc DFPRegs:$T, DFPRegs:$F, 164 imm:$Cond, ICC))]>; 165 def SELECT_CC_DFP_FCC 166 : Pseudo<(ops DFPRegs:$dst, DFPRegs:$T, DFPRegs:$F, i32imm:$Cond), 167 "; SELECT_CC_DFP_FCC PSEUDO!", 168 [(set DFPRegs:$dst, (V8selectfcc DFPRegs:$T, DFPRegs:$F, 169 imm:$Cond, FCC))]>; 170} 171 172// Section A.3 - Synthetic Instructions, p. 85 173// special cases of JMPL: 174let isReturn = 1, isTerminator = 1, hasDelaySlot = 1, noResults = 1 in { 175 let rd = O7.Num, rs1 = G0.Num, simm13 = 8 in 176 // FIXME: temporary workaround for return without an incoming flag. 177 def RETVOID: F3_2<2, 0b111000, (ops), "retl", [(ret)]>; 178 let hasInFlag = 1 in 179 def RETL: F3_2<2, 0b111000, (ops), "retl", []>; 180} 181 182// Section B.1 - Load Integer Instructions, p. 90 183def LDSBrr : F3_1<3, 0b001001, 184 (ops IntRegs:$dst, MEMrr:$addr), 185 "ldsb [$addr], $dst", 186 [(set IntRegs:$dst, (sextload ADDRrr:$addr, i8))]>; 187def LDSBri : F3_2<3, 0b001001, 188 (ops IntRegs:$dst, MEMri:$addr), 189 "ldsb [$addr], $dst", 190 [(set IntRegs:$dst, (sextload ADDRri:$addr, i8))]>; 191def LDSHrr : F3_1<3, 0b001010, 192 (ops IntRegs:$dst, MEMrr:$addr), 193 "ldsh [$addr], $dst", 194 [(set IntRegs:$dst, (sextload ADDRrr:$addr, i16))]>; 195def LDSHri : F3_2<3, 0b001010, 196 (ops IntRegs:$dst, MEMri:$addr), 197 "ldsh [$addr], $dst", 198 [(set IntRegs:$dst, (sextload ADDRri:$addr, i16))]>; 199def LDUBrr : F3_1<3, 0b000001, 200 (ops IntRegs:$dst, MEMrr:$addr), 201 "ldub [$addr], $dst", 202 [(set IntRegs:$dst, (zextload ADDRrr:$addr, i8))]>; 203def LDUBri : F3_2<3, 0b000001, 204 (ops IntRegs:$dst, MEMri:$addr), 205 "ldub [$addr], $dst", 206 [(set IntRegs:$dst, (zextload ADDRri:$addr, i8))]>; 207def LDUHrr : F3_1<3, 0b000010, 208 (ops IntRegs:$dst, MEMrr:$addr), 209 "lduh [$addr], $dst", 210 [(set IntRegs:$dst, (zextload ADDRrr:$addr, i16))]>; 211def LDUHri : F3_2<3, 0b000010, 212 (ops IntRegs:$dst, MEMri:$addr), 213 "lduh [$addr], $dst", 214 [(set IntRegs:$dst, (zextload ADDRri:$addr, i16))]>; 215def LDrr : F3_1<3, 0b000000, 216 (ops IntRegs:$dst, MEMrr:$addr), 217 "ld [$addr], $dst", 218 [(set IntRegs:$dst, (load ADDRrr:$addr))]>; 219def LDri : F3_2<3, 0b000000, 220 (ops IntRegs:$dst, MEMri:$addr), 221 "ld [$addr], $dst", 222 [(set IntRegs:$dst, (load ADDRri:$addr))]>; 223 224// Section B.2 - Load Floating-point Instructions, p. 92 225def LDFrr : F3_1<3, 0b100000, 226 (ops FPRegs:$dst, MEMrr:$addr), 227 "ld [$addr], $dst", 228 [(set FPRegs:$dst, (load ADDRrr:$addr))]>; 229def LDFri : F3_2<3, 0b100000, 230 (ops FPRegs:$dst, MEMri:$addr), 231 "ld [$addr], $dst", 232 [(set FPRegs:$dst, (load ADDRri:$addr))]>; 233def LDDFrr : F3_1<3, 0b100011, 234 (ops DFPRegs:$dst, MEMrr:$addr), 235 "ldd [$addr], $dst", 236 [(set DFPRegs:$dst, (load ADDRrr:$addr))]>; 237def LDDFri : F3_2<3, 0b100011, 238 (ops DFPRegs:$dst, MEMri:$addr), 239 "ldd [$addr], $dst", 240 [(set DFPRegs:$dst, (load ADDRri:$addr))]>; 241 242// Section B.4 - Store Integer Instructions, p. 95 243def STBrr : F3_1<3, 0b000101, 244 (ops MEMrr:$addr, IntRegs:$src), 245 "stb $src, [$addr]", 246 [(truncstore IntRegs:$src, ADDRrr:$addr, i8)]>; 247def STBri : F3_2<3, 0b000101, 248 (ops MEMri:$addr, IntRegs:$src), 249 "stb $src, [$addr]", 250 [(truncstore IntRegs:$src, ADDRri:$addr, i8)]>; 251def STHrr : F3_1<3, 0b000110, 252 (ops MEMrr:$addr, IntRegs:$src), 253 "sth $src, [$addr]", 254 [(truncstore IntRegs:$src, ADDRrr:$addr, i16)]>; 255def STHri : F3_2<3, 0b000110, 256 (ops MEMri:$addr, IntRegs:$src), 257 "sth $src, [$addr]", 258 [(truncstore IntRegs:$src, ADDRri:$addr, i16)]>; 259def STrr : F3_1<3, 0b000100, 260 (ops MEMrr:$addr, IntRegs:$src), 261 "st $src, [$addr]", 262 [(store IntRegs:$src, ADDRrr:$addr)]>; 263def STri : F3_2<3, 0b000100, 264 (ops MEMri:$addr, IntRegs:$src), 265 "st $src, [$addr]", 266 [(store IntRegs:$src, ADDRri:$addr)]>; 267 268// Section B.5 - Store Floating-point Instructions, p. 97 269def STFrr : F3_1<3, 0b100100, 270 (ops MEMrr:$addr, FPRegs:$src), 271 "st $src, [$addr]", 272 [(store FPRegs:$src, ADDRrr:$addr)]>; 273def STFri : F3_2<3, 0b100100, 274 (ops MEMri:$addr, FPRegs:$src), 275 "st $src, [$addr]", 276 [(store FPRegs:$src, ADDRri:$addr)]>; 277def STDFrr : F3_1<3, 0b100111, 278 (ops MEMrr:$addr, DFPRegs:$src), 279 "std $src, [$addr]", 280 [(store DFPRegs:$src, ADDRrr:$addr)]>; 281def STDFri : F3_2<3, 0b100111, 282 (ops MEMri:$addr, DFPRegs:$src), 283 "std $src, [$addr]", 284 [(store DFPRegs:$src, ADDRri:$addr)]>; 285 286// Section B.9 - SETHI Instruction, p. 104 287def SETHIi: F2_1<0b100, 288 (ops IntRegs:$dst, i32imm:$src), 289 "sethi $src, $dst", 290 [(set IntRegs:$dst, SETHIimm:$src)]>; 291 292// Section B.10 - NOP Instruction, p. 105 293// (It's a special case of SETHI) 294let rd = 0, imm22 = 0 in 295 def NOP : F2_1<0b100, (ops), "nop", []>; 296 297// Section B.11 - Logical Instructions, p. 106 298def ANDrr : F3_1<2, 0b000001, 299 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 300 "and $b, $c, $dst", 301 [(set IntRegs:$dst, (and IntRegs:$b, IntRegs:$c))]>; 302def ANDri : F3_2<2, 0b000001, 303 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 304 "and $b, $c, $dst", 305 [(set IntRegs:$dst, (and IntRegs:$b, simm13:$c))]>; 306def ANDNrr : F3_1<2, 0b000101, 307 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 308 "andn $b, $c, $dst", 309 [(set IntRegs:$dst, (and IntRegs:$b, (not IntRegs:$c)))]>; 310def ANDNri : F3_2<2, 0b000101, 311 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 312 "andn $b, $c, $dst", []>; 313def ORrr : F3_1<2, 0b000010, 314 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 315 "or $b, $c, $dst", 316 [(set IntRegs:$dst, (or IntRegs:$b, IntRegs:$c))]>; 317def ORri : F3_2<2, 0b000010, 318 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 319 "or $b, $c, $dst", 320 [(set IntRegs:$dst, (or IntRegs:$b, simm13:$c))]>; 321def ORNrr : F3_1<2, 0b000110, 322 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 323 "orn $b, $c, $dst", 324 [(set IntRegs:$dst, (or IntRegs:$b, (not IntRegs:$c)))]>; 325def ORNri : F3_2<2, 0b000110, 326 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 327 "orn $b, $c, $dst", []>; 328def XORrr : F3_1<2, 0b000011, 329 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 330 "xor $b, $c, $dst", 331 [(set IntRegs:$dst, (xor IntRegs:$b, IntRegs:$c))]>; 332def XORri : F3_2<2, 0b000011, 333 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 334 "xor $b, $c, $dst", 335 [(set IntRegs:$dst, (xor IntRegs:$b, simm13:$c))]>; 336def XNORrr : F3_1<2, 0b000111, 337 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 338 "xnor $b, $c, $dst", 339 [(set IntRegs:$dst, (xor IntRegs:$b, (not IntRegs:$c)))]>; 340def XNORri : F3_2<2, 0b000111, 341 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 342 "xnor $b, $c, $dst", []>; 343 344// Section B.12 - Shift Instructions, p. 107 345def SLLrr : F3_1<2, 0b100101, 346 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 347 "sll $b, $c, $dst", 348 [(set IntRegs:$dst, (shl IntRegs:$b, IntRegs:$c))]>; 349def SLLri : F3_2<2, 0b100101, 350 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 351 "sll $b, $c, $dst", 352 [(set IntRegs:$dst, (shl IntRegs:$b, simm13:$c))]>; 353def SRLrr : F3_1<2, 0b100110, 354 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 355 "srl $b, $c, $dst", 356 [(set IntRegs:$dst, (srl IntRegs:$b, IntRegs:$c))]>; 357def SRLri : F3_2<2, 0b100110, 358 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 359 "srl $b, $c, $dst", 360 [(set IntRegs:$dst, (srl IntRegs:$b, simm13:$c))]>; 361def SRArr : F3_1<2, 0b100111, 362 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 363 "sra $b, $c, $dst", 364 [(set IntRegs:$dst, (sra IntRegs:$b, IntRegs:$c))]>; 365def SRAri : F3_2<2, 0b100111, 366 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 367 "sra $b, $c, $dst", 368 [(set IntRegs:$dst, (sra IntRegs:$b, simm13:$c))]>; 369 370// Section B.13 - Add Instructions, p. 108 371def ADDrr : F3_1<2, 0b000000, 372 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 373 "add $b, $c, $dst", 374 [(set IntRegs:$dst, (add IntRegs:$b, IntRegs:$c))]>; 375def ADDri : F3_2<2, 0b000000, 376 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 377 "add $b, $c, $dst", 378 [(set IntRegs:$dst, (add IntRegs:$b, simm13:$c))]>; 379def ADDCCrr : F3_1<2, 0b010000, 380 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 381 "addcc $b, $c, $dst", []>; 382def ADDCCri : F3_2<2, 0b010000, 383 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 384 "addcc $b, $c, $dst", []>; 385def ADDXrr : F3_1<2, 0b001000, 386 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 387 "addx $b, $c, $dst", []>; 388def ADDXri : F3_2<2, 0b001000, 389 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 390 "addx $b, $c, $dst", []>; 391 392// Section B.15 - Subtract Instructions, p. 110 393def SUBrr : F3_1<2, 0b000100, 394 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 395 "sub $b, $c, $dst", 396 [(set IntRegs:$dst, (sub IntRegs:$b, IntRegs:$c))]>; 397def SUBri : F3_2<2, 0b000100, 398 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 399 "sub $b, $c, $dst", 400 [(set IntRegs:$dst, (sub IntRegs:$b, simm13:$c))]>; 401def SUBXrr : F3_1<2, 0b001100, 402 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 403 "subx $b, $c, $dst", []>; 404def SUBXri : F3_2<2, 0b001100, 405 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 406 "subx $b, $c, $dst", []>; 407def SUBCCrr : F3_1<2, 0b010100, 408 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 409 "subcc $b, $c, $dst", []>; 410def SUBCCri : F3_2<2, 0b010100, 411 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 412 "subcc $b, $c, $dst", []>; 413def SUBXCCrr: F3_1<2, 0b011100, 414 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 415 "subxcc $b, $c, $dst", []>; 416 417// Section B.18 - Multiply Instructions, p. 113 418def UMULrr : F3_1<2, 0b001010, 419 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 420 "umul $b, $c, $dst", []>; 421def UMULri : F3_2<2, 0b001010, 422 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 423 "umul $b, $c, $dst", []>; 424def SMULrr : F3_1<2, 0b001011, 425 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 426 "smul $b, $c, $dst", 427 [(set IntRegs:$dst, (mul IntRegs:$b, IntRegs:$c))]>; 428def SMULri : F3_2<2, 0b001011, 429 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 430 "smul $b, $c, $dst", 431 [(set IntRegs:$dst, (mul IntRegs:$b, simm13:$c))]>; 432 433// Section B.19 - Divide Instructions, p. 115 434def UDIVrr : F3_1<2, 0b001110, 435 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 436 "udiv $b, $c, $dst", []>; 437def UDIVri : F3_2<2, 0b001110, 438 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 439 "udiv $b, $c, $dst", []>; 440def SDIVrr : F3_1<2, 0b001111, 441 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 442 "sdiv $b, $c, $dst", []>; 443def SDIVri : F3_2<2, 0b001111, 444 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 445 "sdiv $b, $c, $dst", []>; 446 447// Section B.20 - SAVE and RESTORE, p. 117 448def SAVErr : F3_1<2, 0b111100, 449 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 450 "save $b, $c, $dst", []>; 451def SAVEri : F3_2<2, 0b111100, 452 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 453 "save $b, $c, $dst", []>; 454def RESTORErr : F3_1<2, 0b111101, 455 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 456 "restore $b, $c, $dst", []>; 457def RESTOREri : F3_2<2, 0b111101, 458 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 459 "restore $b, $c, $dst", []>; 460 461// Section B.21 - Branch on Integer Condition Codes Instructions, p. 119 462 463// conditional branch class: 464class BranchV8<bits<4> cc, dag ops, string asmstr, list<dag> pattern> 465 : F2_2<cc, 0b010, ops, asmstr, pattern> { 466 let isBranch = 1; 467 let isTerminator = 1; 468 let hasDelaySlot = 1; 469 let noResults = 1; 470} 471 472let isBarrier = 1 in 473 def BA : BranchV8<0b1000, (ops brtarget:$dst), 474 "ba $dst", 475 [(br bb:$dst)]>; 476def BNE : BranchV8<0b1001, (ops brtarget:$dst), 477 "bne $dst", 478 [(V8bricc bb:$dst, SETNE, ICC)]>; 479def BE : BranchV8<0b0001, (ops brtarget:$dst), 480 "be $dst", 481 [(V8bricc bb:$dst, SETEQ, ICC)]>; 482def BG : BranchV8<0b1010, (ops brtarget:$dst), 483 "bg $dst", 484 [(V8bricc bb:$dst, SETGT, ICC)]>; 485def BLE : BranchV8<0b0010, (ops brtarget:$dst), 486 "ble $dst", 487 [(V8bricc bb:$dst, SETLE, ICC)]>; 488def BGE : BranchV8<0b1011, (ops brtarget:$dst), 489 "bge $dst", 490 [(V8bricc bb:$dst, SETGE, ICC)]>; 491def BL : BranchV8<0b0011, (ops brtarget:$dst), 492 "bl $dst", 493 [(V8bricc bb:$dst, SETLT, ICC)]>; 494def BGU : BranchV8<0b1100, (ops brtarget:$dst), 495 "bgu $dst", 496 [(V8bricc bb:$dst, SETUGT, ICC)]>; 497def BLEU : BranchV8<0b0100, (ops brtarget:$dst), 498 "bleu $dst", 499 [(V8bricc bb:$dst, SETULE, ICC)]>; 500def BCC : BranchV8<0b1101, (ops brtarget:$dst), 501 "bcc $dst", 502 [(V8bricc bb:$dst, SETUGE, ICC)]>; 503def BCS : BranchV8<0b0101, (ops brtarget:$dst), 504 "bcs $dst", 505 [(V8bricc bb:$dst, SETULT, ICC)]>; 506 507// Section B.22 - Branch on Floating-point Condition Codes Instructions, p. 121 508 509// floating-point conditional branch class: 510class FPBranchV8<bits<4> cc, dag ops, string asmstr, list<dag> pattern> 511 : F2_2<cc, 0b110, ops, asmstr, pattern> { 512 let isBranch = 1; 513 let isTerminator = 1; 514 let hasDelaySlot = 1; 515 let noResults = 1; 516} 517 518def FBU : FPBranchV8<0b0111, (ops brtarget:$dst), 519 "fbu $dst", 520 [(V8brfcc bb:$dst, SETUO, FCC)]>; 521def FBG : FPBranchV8<0b0110, (ops brtarget:$dst), 522 "fbg $dst", 523 [(V8brfcc bb:$dst, SETGT, FCC)]>; 524def FBUG : FPBranchV8<0b0101, (ops brtarget:$dst), 525 "fbug $dst", 526 [(V8brfcc bb:$dst, SETUGT, FCC)]>; 527def FBL : FPBranchV8<0b0100, (ops brtarget:$dst), 528 "fbl $dst", 529 [(V8brfcc bb:$dst, SETLT, FCC)]>; 530def FBUL : FPBranchV8<0b0011, (ops brtarget:$dst), 531 "fbul $dst", 532 [(V8brfcc bb:$dst, SETULT, FCC)]>; 533def FBLG : FPBranchV8<0b0010, (ops brtarget:$dst), 534 "fblg $dst", 535 [(V8brfcc bb:$dst, SETONE, FCC)]>; 536def FBNE : FPBranchV8<0b0001, (ops brtarget:$dst), 537 "fbne $dst", 538 [(V8brfcc bb:$dst, SETNE, FCC)]>; 539def FBE : FPBranchV8<0b1001, (ops brtarget:$dst), 540 "fbe $dst", 541 [(V8brfcc bb:$dst, SETEQ, FCC)]>; 542def FBUE : FPBranchV8<0b1010, (ops brtarget:$dst), 543 "fbue $dst", 544 [(V8brfcc bb:$dst, SETUEQ, FCC)]>; 545def FBGE : FPBranchV8<0b1011, (ops brtarget:$dst), 546 "fbge $dst", 547 [(V8brfcc bb:$dst, SETGE, FCC)]>; 548def FBUGE: FPBranchV8<0b1100, (ops brtarget:$dst), 549 "fbuge $dst", 550 [(V8brfcc bb:$dst, SETUGE, FCC)]>; 551def FBLE : FPBranchV8<0b1101, (ops brtarget:$dst), 552 "fble $dst", 553 [(V8brfcc bb:$dst, SETLE, FCC)]>; 554def FBULE: FPBranchV8<0b1110, (ops brtarget:$dst), 555 "fbule $dst", 556 [(V8brfcc bb:$dst, SETULE, FCC)]>; 557def FBO : FPBranchV8<0b1111, (ops brtarget:$dst), 558 "fbo $dst", 559 [(V8brfcc bb:$dst, SETO, FCC)]>; 560 561 562 563// Section B.24 - Call and Link Instruction, p. 125 564// This is the only Format 1 instruction 565let Uses = [O0, O1, O2, O3, O4, O5], 566 hasDelaySlot = 1, isCall = 1, hasInFlag = 1, hasOutFlag = 1, noResults = 1, 567 Defs = [O0, O1, O2, O3, O4, O5, O7, G1, G2, G3, G4, G5, G6, G7, 568 D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15] in { 569 def CALL : InstV8<(ops calltarget:$dst), 570 "call $dst", []> { 571 bits<30> disp; 572 let op = 1; 573 let Inst{29-0} = disp; 574 } 575 576 // indirect calls 577 def JMPLrr : F3_1<2, 0b111000, 578 (ops MEMrr:$ptr), 579 "call $ptr", 580 [(call ADDRrr:$ptr)]>; 581 def JMPLri : F3_2<2, 0b111000, 582 (ops MEMri:$ptr), 583 "call $ptr", 584 [(call ADDRri:$ptr)]>; 585} 586 587// Section B.28 - Read State Register Instructions 588def RDY : F3_1<2, 0b101000, 589 (ops IntRegs:$dst), 590 "rd %y, $dst", []>; 591 592// Section B.29 - Write State Register Instructions 593def WRYrr : F3_1<2, 0b110000, 594 (ops IntRegs:$b, IntRegs:$c), 595 "wr $b, $c, %y", []>; 596def WRYri : F3_2<2, 0b110000, 597 (ops IntRegs:$b, i32imm:$c), 598 "wr $b, $c, %y", []>; 599 600// Convert Integer to Floating-point Instructions, p. 141 601def FITOS : F3_3<2, 0b110100, 0b011000100, 602 (ops FPRegs:$dst, FPRegs:$src), 603 "fitos $src, $dst", 604 [(set FPRegs:$dst, (V8itof FPRegs:$src))]>; 605def FITOD : F3_3<2, 0b110100, 0b011001000, 606 (ops DFPRegs:$dst, FPRegs:$src), 607 "fitod $src, $dst", 608 [(set DFPRegs:$dst, (V8itof FPRegs:$src))]>; 609 610// Convert Floating-point to Integer Instructions, p. 142 611def FSTOI : F3_3<2, 0b110100, 0b011010001, 612 (ops FPRegs:$dst, FPRegs:$src), 613 "fstoi $src, $dst", 614 [(set FPRegs:$dst, (V8ftoi FPRegs:$src))]>; 615def FDTOI : F3_3<2, 0b110100, 0b011010010, 616 (ops FPRegs:$dst, DFPRegs:$src), 617 "fdtoi $src, $dst", 618 [(set FPRegs:$dst, (V8ftoi DFPRegs:$src))]>; 619 620// Convert between Floating-point Formats Instructions, p. 143 621def FSTOD : F3_3<2, 0b110100, 0b011001001, 622 (ops DFPRegs:$dst, FPRegs:$src), 623 "fstod $src, $dst", 624 [(set DFPRegs:$dst, (fextend FPRegs:$src))]>; 625def FDTOS : F3_3<2, 0b110100, 0b011000110, 626 (ops FPRegs:$dst, DFPRegs:$src), 627 "fdtos $src, $dst", 628 [(set FPRegs:$dst, (fround DFPRegs:$src))]>; 629 630// Floating-point Move Instructions, p. 144 631def FMOVS : F3_3<2, 0b110100, 0b000000001, 632 (ops FPRegs:$dst, FPRegs:$src), 633 "fmovs $src, $dst", []>; 634def FNEGS : F3_3<2, 0b110100, 0b000000101, 635 (ops FPRegs:$dst, FPRegs:$src), 636 "fnegs $src, $dst", 637 [(set FPRegs:$dst, (fneg FPRegs:$src))]>; 638def FABSS : F3_3<2, 0b110100, 0b000001001, 639 (ops FPRegs:$dst, FPRegs:$src), 640 "fabss $src, $dst", 641 [(set FPRegs:$dst, (fabs FPRegs:$src))]>; 642 643 644// Floating-point Square Root Instructions, p.145 645def FSQRTS : F3_3<2, 0b110100, 0b000101001, 646 (ops FPRegs:$dst, FPRegs:$src), 647 "fsqrts $src, $dst", 648 [(set FPRegs:$dst, (fsqrt FPRegs:$src))]>; 649def FSQRTD : F3_3<2, 0b110100, 0b000101010, 650 (ops DFPRegs:$dst, DFPRegs:$src), 651 "fsqrtd $src, $dst", 652 [(set DFPRegs:$dst, (fsqrt DFPRegs:$src))]>; 653 654 655 656// Floating-point Add and Subtract Instructions, p. 146 657def FADDS : F3_3<2, 0b110100, 0b001000001, 658 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2), 659 "fadds $src1, $src2, $dst", 660 [(set FPRegs:$dst, (fadd FPRegs:$src1, FPRegs:$src2))]>; 661def FADDD : F3_3<2, 0b110100, 0b001000010, 662 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2), 663 "faddd $src1, $src2, $dst", 664 [(set DFPRegs:$dst, (fadd DFPRegs:$src1, DFPRegs:$src2))]>; 665def FSUBS : F3_3<2, 0b110100, 0b001000101, 666 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2), 667 "fsubs $src1, $src2, $dst", 668 [(set FPRegs:$dst, (fsub FPRegs:$src1, FPRegs:$src2))]>; 669def FSUBD : F3_3<2, 0b110100, 0b001000110, 670 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2), 671 "fsubd $src1, $src2, $dst", 672 [(set DFPRegs:$dst, (fsub DFPRegs:$src1, DFPRegs:$src2))]>; 673 674// Floating-point Multiply and Divide Instructions, p. 147 675def FMULS : F3_3<2, 0b110100, 0b001001001, 676 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2), 677 "fmuls $src1, $src2, $dst", 678 [(set FPRegs:$dst, (fmul FPRegs:$src1, FPRegs:$src2))]>; 679def FMULD : F3_3<2, 0b110100, 0b001001010, 680 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2), 681 "fmuld $src1, $src2, $dst", 682 [(set DFPRegs:$dst, (fmul DFPRegs:$src1, DFPRegs:$src2))]>; 683def FSMULD : F3_3<2, 0b110100, 0b001101001, 684 (ops DFPRegs:$dst, FPRegs:$src1, FPRegs:$src2), 685 "fsmuld $src1, $src2, $dst", 686 [(set DFPRegs:$dst, (fmul (fextend FPRegs:$src1), 687 (fextend FPRegs:$src2)))]>; 688def FDIVS : F3_3<2, 0b110100, 0b001001101, 689 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2), 690 "fdivs $src1, $src2, $dst", 691 [(set FPRegs:$dst, (fdiv FPRegs:$src1, FPRegs:$src2))]>; 692def FDIVD : F3_3<2, 0b110100, 0b001001110, 693 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2), 694 "fdivd $src1, $src2, $dst", 695 [(set DFPRegs:$dst, (fdiv DFPRegs:$src1, DFPRegs:$src2))]>; 696 697// Floating-point Compare Instructions, p. 148 698// Note: the 2nd template arg is different for these guys. 699// Note 2: the result of a FCMP is not available until the 2nd cycle 700// after the instr is retired, but there is no interlock. This behavior 701// is modelled with a forced noop after the instruction. 702def FCMPS : F3_3<2, 0b110101, 0b001010001, 703 (ops FPRegs:$src1, FPRegs:$src2), 704 "fcmps $src1, $src2\n\tnop", 705 [(set FCC, (V8cmpfcc FPRegs:$src1, FPRegs:$src2))]>; 706def FCMPD : F3_3<2, 0b110101, 0b001010010, 707 (ops DFPRegs:$src1, DFPRegs:$src2), 708 "fcmpd $src1, $src2\n\tnop", 709 [(set FCC, (V8cmpfcc DFPRegs:$src1, DFPRegs:$src2))]>; 710 711//===----------------------------------------------------------------------===// 712// Non-Instruction Patterns 713//===----------------------------------------------------------------------===// 714 715// Small immediates. 716def : Pat<(i32 simm13:$val), 717 (ORri G0, imm:$val)>; 718// Arbitrary immediates. 719def : Pat<(i32 imm:$val), 720 (ORri (SETHIi (HI22 imm:$val)), (LO10 imm:$val))>; 721 722// Global addresses, constant pool entries 723def : Pat<(V8hi tglobaladdr:$in), (SETHIi tglobaladdr:$in)>; 724def : Pat<(V8lo tglobaladdr:$in), (ORri G0, tglobaladdr:$in)>; 725def : Pat<(V8hi tconstpool:$in), (SETHIi tconstpool:$in)>; 726def : Pat<(V8lo tconstpool:$in), (ORri G0, tconstpool:$in)>; 727 728// Return of a value, which has an input flag. 729def : Pat<(retflag), (RETL)>; 730 731 732// Calls: 733def : Pat<(call tglobaladdr:$dst), 734 (CALL tglobaladdr:$dst)>; 735def : Pat<(call externalsym:$dst), 736 (CALL externalsym:$dst)>; 737 738 739// Map integer extload's to zextloads. 740def : Pat<(i32 (extload ADDRrr:$src, i1)), (LDUBrr ADDRrr:$src)>; 741def : Pat<(i32 (extload ADDRri:$src, i1)), (LDUBri ADDRri:$src)>; 742def : Pat<(i32 (extload ADDRrr:$src, i8)), (LDUBrr ADDRrr:$src)>; 743def : Pat<(i32 (extload ADDRri:$src, i8)), (LDUBri ADDRri:$src)>; 744def : Pat<(i32 (extload ADDRrr:$src, i16)), (LDUHrr ADDRrr:$src)>; 745def : Pat<(i32 (extload ADDRri:$src, i16)), (LDUHri ADDRri:$src)>; 746 747// zextload bool -> zextload byte 748def : Pat<(i32 (zextload ADDRrr:$src, i1)), (LDUBrr ADDRrr:$src)>; 749def : Pat<(i32 (zextload ADDRri:$src, i1)), (LDUBri ADDRri:$src)>; 750 751// truncstore bool -> truncstore byte. 752def : Pat<(truncstore IntRegs:$src, ADDRrr:$addr, i1), 753 (STBrr ADDRrr:$addr, IntRegs:$src)>; 754def : Pat<(truncstore IntRegs:$src, ADDRri:$addr, i1), 755 (STBri ADDRri:$addr, IntRegs:$src)>; 756