SparcInstrInfo.td revision 2f17d0facf6a489a051c86c015453c2b102e5c37
1cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Project//===-- SparcInstrInfo.td - Target Description for Sparc Target -----------===// 205436638acc7c010349a69c3395f1a57c642dc62Ying Wang// 305436638acc7c010349a69c3395f1a57c642dc62Ying Wang// The LLVM Compiler Infrastructure 4cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Project// 5cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Project// This file is distributed under the University of Illinois Open Source 605436638acc7c010349a69c3395f1a57c642dc62Ying Wang// License. See LICENSE.TXT for details. 7cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Project// 805436638acc7c010349a69c3395f1a57c642dc62Ying Wang//===----------------------------------------------------------------------===// 905436638acc7c010349a69c3395f1a57c642dc62Ying Wang// 10cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Project// This file describes the Sparc instructions in TableGen format. 11cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Project// 12cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Project//===----------------------------------------------------------------------===// 13cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Project 14cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Project//===----------------------------------------------------------------------===// 15cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Project// Instruction format superclass 1605436638acc7c010349a69c3395f1a57c642dc62Ying Wang//===----------------------------------------------------------------------===// 1705436638acc7c010349a69c3395f1a57c642dc62Ying Wang 18cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Projectinclude "SparcInstrFormats.td" 1905436638acc7c010349a69c3395f1a57c642dc62Ying Wang 2005436638acc7c010349a69c3395f1a57c642dc62Ying Wang//===----------------------------------------------------------------------===// 2105436638acc7c010349a69c3395f1a57c642dc62Ying Wang// Feature predicates. 2205436638acc7c010349a69c3395f1a57c642dc62Ying Wang//===----------------------------------------------------------------------===// 2305436638acc7c010349a69c3395f1a57c642dc62Ying Wang 2405436638acc7c010349a69c3395f1a57c642dc62Ying Wang// True when generating 32-bit code. 2505436638acc7c010349a69c3395f1a57c642dc62Ying Wangdef Is32Bit : Predicate<"!Subtarget.is64Bit()">; 2605436638acc7c010349a69c3395f1a57c642dc62Ying Wang 2705436638acc7c010349a69c3395f1a57c642dc62Ying Wang// True when generating 64-bit code. This also implies HasV9. 2805436638acc7c010349a69c3395f1a57c642dc62Ying Wangdef Is64Bit : Predicate<"Subtarget.is64Bit()">; 2905436638acc7c010349a69c3395f1a57c642dc62Ying Wang 3005436638acc7c010349a69c3395f1a57c642dc62Ying Wang// HasV9 - This predicate is true when the target processor supports V9 3105436638acc7c010349a69c3395f1a57c642dc62Ying Wang// instructions. Note that the machine may be running in 32-bit mode. 3205436638acc7c010349a69c3395f1a57c642dc62Ying Wangdef HasV9 : Predicate<"Subtarget.isV9()">; 3305436638acc7c010349a69c3395f1a57c642dc62Ying Wang 3405436638acc7c010349a69c3395f1a57c642dc62Ying Wang// HasNoV9 - This predicate is true when the target doesn't have V9 3505436638acc7c010349a69c3395f1a57c642dc62Ying Wang// instructions. Use of this is just a hack for the isel not having proper 36cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Project// costs for V8 instructions that are more expensive than their V9 ones. 37cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Projectdef HasNoV9 : Predicate<"!Subtarget.isV9()">; 3805436638acc7c010349a69c3395f1a57c642dc62Ying Wang 39cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Project// HasVIS - This is true when the target processor has VIS extensions. 40cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Projectdef HasVIS : Predicate<"Subtarget.isVIS()">; 41cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Project 42cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Project// HasHardQuad - This is true when the target processor supports quad floating 43cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Project// point instructions. 44cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Projectdef HasHardQuad : Predicate<"Subtarget.hasHardQuad()">; 4505436638acc7c010349a69c3395f1a57c642dc62Ying Wang 4605436638acc7c010349a69c3395f1a57c642dc62Ying Wang// UseDeprecatedInsts - This predicate is true when the target processor is a 47cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Project// V8, or when it is V9 but the V8 deprecated instructions are efficient enough 48cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Project// to use when appropriate. In either of these cases, the instruction selector 49cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Project// will pick deprecated instructions. 50cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Projectdef UseDeprecatedInsts : Predicate<"Subtarget.useDeprecatedV8Instructions()">; 5105436638acc7c010349a69c3395f1a57c642dc62Ying Wang 5205436638acc7c010349a69c3395f1a57c642dc62Ying Wang//===----------------------------------------------------------------------===// 5305436638acc7c010349a69c3395f1a57c642dc62Ying Wang// Instruction Pattern Stuff 5405436638acc7c010349a69c3395f1a57c642dc62Ying Wang//===----------------------------------------------------------------------===// 5505436638acc7c010349a69c3395f1a57c642dc62Ying Wang 56cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Projectdef simm11 : PatLeaf<(imm), [{ return isInt<11>(N->getSExtValue()); }]>; 57cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Project 58cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Projectdef simm13 : PatLeaf<(imm), [{ return isInt<13>(N->getSExtValue()); }]>; 59cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Project 60cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Projectdef LO10 : SDNodeXForm<imm, [{ 61cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Project return CurDAG->getTargetConstant((unsigned)N->getZExtValue() & 1023, 62cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Project MVT::i32); 63cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Project}]>; 6405436638acc7c010349a69c3395f1a57c642dc62Ying Wang 65cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Projectdef HI22 : SDNodeXForm<imm, [{ 66cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Project // Transformation function: shift the immediate value down into the low bits. 67cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Project return CurDAG->getTargetConstant((unsigned)N->getZExtValue() >> 10, MVT::i32); 68cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Project}]>; 69cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Project 70cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Projectdef SETHIimm : PatLeaf<(imm), [{ 71cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Project return isShiftedUInt<22, 10>(N->getZExtValue()); 72cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Project}], HI22>; 73cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Project 74cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Project// Addressing modes. 7505436638acc7c010349a69c3395f1a57c642dc62Ying Wangdef ADDRrr : ComplexPattern<iPTR, 2, "SelectADDRrr", [], []>; 7605436638acc7c010349a69c3395f1a57c642dc62Ying Wangdef ADDRri : ComplexPattern<iPTR, 2, "SelectADDRri", [frameindex], []>; 77cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Project 78cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Project// Address operands 79cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Projectdef MEMrr : Operand<iPTR> { 80cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Project let PrintMethod = "printMemOperand"; 81cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Project let MIOperandInfo = (ops ptr_rc, ptr_rc); 82cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Project} 83cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Projectdef MEMri : Operand<iPTR> { 84cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Project let PrintMethod = "printMemOperand"; 8505436638acc7c010349a69c3395f1a57c642dc62Ying Wang let MIOperandInfo = (ops ptr_rc, i32imm); 86cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Project} 87cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Project 88cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Project// Branch targets have OtherVT type. 89cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Projectdef brtarget : Operand<OtherVT>; 90cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Projectdef calltarget : Operand<i32>; 91cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Project 92cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Project// Operand for printing out a condition code. 93cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Projectlet PrintMethod = "printCCOperand" in 94cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Project def CCOp : Operand<i32>; 95cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Project 96cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Projectdef SDTSPcmpicc : 97cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source ProjectSDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>]>; 98cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Projectdef SDTSPcmpfcc : 99cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source ProjectSDTypeProfile<0, 2, [SDTCisFP<0>, SDTCisSameAs<0, 1>]>; 100cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Projectdef SDTSPbrcc : 101cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source ProjectSDTypeProfile<0, 2, [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>; 102cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Projectdef SDTSPselectcc : 103cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source ProjectSDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>]>; 104cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Projectdef SDTSPFTOI : 105cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source ProjectSDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisFP<1>]>; 106cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Projectdef SDTSPITOF : 107cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source ProjectSDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f32>]>; 108cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Project 109cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Projectdef SPcmpicc : SDNode<"SPISD::CMPICC", SDTSPcmpicc, [SDNPOutGlue]>; 110cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Projectdef SPcmpfcc : SDNode<"SPISD::CMPFCC", SDTSPcmpfcc, [SDNPOutGlue]>; 111cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Projectdef SPbricc : SDNode<"SPISD::BRICC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>; 112cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Projectdef SPbrxcc : SDNode<"SPISD::BRXCC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>; 113cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Projectdef SPbrfcc : SDNode<"SPISD::BRFCC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>; 114cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Project 115cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Projectdef SPhi : SDNode<"SPISD::Hi", SDTIntUnaryOp>; 116cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Projectdef SPlo : SDNode<"SPISD::Lo", SDTIntUnaryOp>; 117cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Project 118cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Projectdef SPftoi : SDNode<"SPISD::FTOI", SDTSPFTOI>; 11905436638acc7c010349a69c3395f1a57c642dc62Ying Wangdef SPitof : SDNode<"SPISD::ITOF", SDTSPITOF>; 120cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Project 121cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Projectdef SPselecticc : SDNode<"SPISD::SELECT_ICC", SDTSPselectcc, [SDNPInGlue]>; 122cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Projectdef SPselectxcc : SDNode<"SPISD::SELECT_XCC", SDTSPselectcc, [SDNPInGlue]>; 123cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Projectdef SPselectfcc : SDNode<"SPISD::SELECT_FCC", SDTSPselectcc, [SDNPInGlue]>; 124cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Project 12505436638acc7c010349a69c3395f1a57c642dc62Ying Wang// These are target-independent nodes, but have target-specific formats. 12605436638acc7c010349a69c3395f1a57c642dc62Ying Wangdef SDT_SPCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>; 12705436638acc7c010349a69c3395f1a57c642dc62Ying Wangdef SDT_SPCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, 128cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Project SDTCisVT<1, i32> ]>; 129cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Project 130cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Projectdef callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_SPCallSeqStart, 13105436638acc7c010349a69c3395f1a57c642dc62Ying Wang [SDNPHasChain, SDNPOutGlue]>; 13205436638acc7c010349a69c3395f1a57c642dc62Ying Wangdef callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_SPCallSeqEnd, 133cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Project [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 13405436638acc7c010349a69c3395f1a57c642dc62Ying Wang 135cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Projectdef SDT_SPCall : SDTypeProfile<0, -1, [SDTCisVT<0, i32>]>; 136cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Projectdef call : SDNode<"SPISD::CALL", SDT_SPCall, 137cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Project [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 138cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Project SDNPVariadic]>; 139cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Project 140cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Projectdef SDT_SPRet : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>; 14105436638acc7c010349a69c3395f1a57c642dc62Ying Wangdef retflag : SDNode<"SPISD::RET_FLAG", SDT_SPRet, 142cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Project [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 14305436638acc7c010349a69c3395f1a57c642dc62Ying Wang 144cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Projectdef flushw : SDNode<"SPISD::FLUSHW", SDTNone, 14505436638acc7c010349a69c3395f1a57c642dc62Ying Wang [SDNPHasChain, SDNPSideEffect, SDNPMayStore]>; 146cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Project 147cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Projectdef getPCX : Operand<i32> { 14805436638acc7c010349a69c3395f1a57c642dc62Ying Wang let PrintMethod = "printGetPCX"; 149cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Project} 150cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Project 151cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Project//===----------------------------------------------------------------------===// 152cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Project// SPARC Flag Conditions 15305436638acc7c010349a69c3395f1a57c642dc62Ying Wang//===----------------------------------------------------------------------===// 154cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Project 155cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Project// Note that these values must be kept in sync with the CCOp::CondCode enum 156cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Project// values. 157cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Projectclass ICC_VAL<int N> : PatLeaf<(i32 N)>; 158cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Projectdef ICC_NE : ICC_VAL< 9>; // Not Equal 159cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Projectdef ICC_E : ICC_VAL< 1>; // Equal 160cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Projectdef ICC_G : ICC_VAL<10>; // Greater 161cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Projectdef ICC_LE : ICC_VAL< 2>; // Less or Equal 162cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Projectdef ICC_GE : ICC_VAL<11>; // Greater or Equal 163cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Projectdef ICC_L : ICC_VAL< 3>; // Less 164cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Projectdef ICC_GU : ICC_VAL<12>; // Greater Unsigned 16505436638acc7c010349a69c3395f1a57c642dc62Ying Wangdef ICC_LEU : ICC_VAL< 4>; // Less or Equal Unsigned 166cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Projectdef ICC_CC : ICC_VAL<13>; // Carry Clear/Great or Equal Unsigned 167cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Projectdef ICC_CS : ICC_VAL< 5>; // Carry Set/Less Unsigned 16805436638acc7c010349a69c3395f1a57c642dc62Ying Wangdef ICC_POS : ICC_VAL<14>; // Positive 16905436638acc7c010349a69c3395f1a57c642dc62Ying Wangdef ICC_NEG : ICC_VAL< 6>; // Negative 17005436638acc7c010349a69c3395f1a57c642dc62Ying Wangdef ICC_VC : ICC_VAL<15>; // Overflow Clear 17105436638acc7c010349a69c3395f1a57c642dc62Ying Wangdef ICC_VS : ICC_VAL< 7>; // Overflow Set 172cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Project 17305436638acc7c010349a69c3395f1a57c642dc62Ying Wangclass FCC_VAL<int N> : PatLeaf<(i32 N)>; 17405436638acc7c010349a69c3395f1a57c642dc62Ying Wangdef FCC_U : FCC_VAL<23>; // Unordered 175cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Projectdef FCC_G : FCC_VAL<22>; // Greater 176cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Projectdef FCC_UG : FCC_VAL<21>; // Unordered or Greater 17705436638acc7c010349a69c3395f1a57c642dc62Ying Wangdef FCC_L : FCC_VAL<20>; // Less 17805436638acc7c010349a69c3395f1a57c642dc62Ying Wangdef FCC_UL : FCC_VAL<19>; // Unordered or Less 17905436638acc7c010349a69c3395f1a57c642dc62Ying Wangdef FCC_LG : FCC_VAL<18>; // Less or Greater 180cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Projectdef FCC_NE : FCC_VAL<17>; // Not Equal 18105436638acc7c010349a69c3395f1a57c642dc62Ying Wangdef FCC_E : FCC_VAL<25>; // Equal 18205436638acc7c010349a69c3395f1a57c642dc62Ying Wangdef FCC_UE : FCC_VAL<24>; // Unordered or Equal 183cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Projectdef FCC_GE : FCC_VAL<25>; // Greater or Equal 18405436638acc7c010349a69c3395f1a57c642dc62Ying Wangdef FCC_UGE : FCC_VAL<26>; // Unordered or Greater or Equal 185cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Projectdef FCC_LE : FCC_VAL<27>; // Less or Equal 186cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Projectdef FCC_ULE : FCC_VAL<28>; // Unordered or Less or Equal 187cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Projectdef FCC_O : FCC_VAL<29>; // Ordered 188cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Project 189cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Project//===----------------------------------------------------------------------===// 190cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Project// Instruction Class Templates 191cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Project//===----------------------------------------------------------------------===// 192cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Project 193cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Project/// F3_12 multiclass - Define a normal F3_1/F3_2 pattern in one shot. 19405436638acc7c010349a69c3395f1a57c642dc62Ying Wangmulticlass F3_12<string OpcStr, bits<6> Op3Val, SDNode OpNode> { 19505436638acc7c010349a69c3395f1a57c642dc62Ying Wang def rr : F3_1<2, Op3Val, 196cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Project (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c), 19705436638acc7c010349a69c3395f1a57c642dc62Ying Wang !strconcat(OpcStr, " $b, $c, $dst"), 198cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Project [(set i32:$dst, (OpNode i32:$b, i32:$c))]>; 19905436638acc7c010349a69c3395f1a57c642dc62Ying Wang def ri : F3_2<2, Op3Val, 20005436638acc7c010349a69c3395f1a57c642dc62Ying Wang (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c), 20105436638acc7c010349a69c3395f1a57c642dc62Ying Wang !strconcat(OpcStr, " $b, $c, $dst"), 20205436638acc7c010349a69c3395f1a57c642dc62Ying Wang [(set i32:$dst, (OpNode i32:$b, (i32 simm13:$c)))]>; 203cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Project} 204cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Project 205cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Project/// F3_12np multiclass - Define a normal F3_1/F3_2 pattern in one shot, with no 206cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Project/// pattern. 207cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Projectmulticlass F3_12np<string OpcStr, bits<6> Op3Val> { 208cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Project def rr : F3_1<2, Op3Val, 209cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Project (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c), 210cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Project !strconcat(OpcStr, " $b, $c, $dst"), []>; 21105436638acc7c010349a69c3395f1a57c642dc62Ying Wang def ri : F3_2<2, Op3Val, 212cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Project (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c), 213cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Project !strconcat(OpcStr, " $b, $c, $dst"), []>; 214cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Project} 215cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Project 21605436638acc7c010349a69c3395f1a57c642dc62Ying Wang//===----------------------------------------------------------------------===// 217cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Project// Instructions 218cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Project//===----------------------------------------------------------------------===// 21905436638acc7c010349a69c3395f1a57c642dc62Ying Wang 220cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Project// Pseudo instructions. 22105436638acc7c010349a69c3395f1a57c642dc62Ying Wangclass Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern> 22205436638acc7c010349a69c3395f1a57c642dc62Ying Wang : InstSP<outs, ins, asmstr, pattern>; 223cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Project 224cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Project// GETPCX for PIC 22505436638acc7c010349a69c3395f1a57c642dc62Ying Wanglet Defs = [O7] in { 22605436638acc7c010349a69c3395f1a57c642dc62Ying Wang def GETPCX : Pseudo<(outs getPCX:$getpcseq), (ins), "$getpcseq", [] >; 22705436638acc7c010349a69c3395f1a57c642dc62Ying Wang} 22805436638acc7c010349a69c3395f1a57c642dc62Ying Wang 229cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Projectlet Defs = [O6], Uses = [O6] in { 230cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Projectdef ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt), 23105436638acc7c010349a69c3395f1a57c642dc62Ying Wang "!ADJCALLSTACKDOWN $amt", 232cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Project [(callseq_start timm:$amt)]>; 233cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Projectdef ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2), 234cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Project "!ADJCALLSTACKUP $amt1", 23505436638acc7c010349a69c3395f1a57c642dc62Ying Wang [(callseq_end timm:$amt1, timm:$amt2)]>; 23605436638acc7c010349a69c3395f1a57c642dc62Ying Wang} 23705436638acc7c010349a69c3395f1a57c642dc62Ying Wang 238cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Projectlet hasSideEffects = 1, mayStore = 1 in { 23905436638acc7c010349a69c3395f1a57c642dc62Ying Wang let rd = 0, rs1 = 0, rs2 = 0 in 24005436638acc7c010349a69c3395f1a57c642dc62Ying Wang def FLUSHW : F3_1<0b10, 0b101011, (outs), (ins), 24105436638acc7c010349a69c3395f1a57c642dc62Ying Wang "flushw", 242cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Project [(flushw)]>, Requires<[HasV9]>; 243cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Project let rd = 0, rs1 = 1, simm13 = 3 in 244cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Project def TA3 : F3_2<0b10, 0b111010, (outs), (ins), 24505436638acc7c010349a69c3395f1a57c642dc62Ying Wang "ta 3", 246cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Project [(flushw)]>; 247cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Project} 248cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Project 249cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Projectdef UNIMP : F2_1<0b000, (outs), (ins i32imm:$val), 250cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Project "unimp $val", []>; 251cea198a11f15a2eb071d98491ca9a8bc8cebfbc4The Android Open Source Project 25205436638acc7c010349a69c3395f1a57c642dc62Ying Wang// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after 25305436638acc7c010349a69c3395f1a57c642dc62Ying Wang// instruction selection into a branch sequence. This has to handle all 254// permutations of selection between i32/f32/f64 on ICC and FCC. 255// Expanded after instruction selection. 256let Uses = [ICC], usesCustomInserter = 1 in { 257 def SELECT_CC_Int_ICC 258 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond), 259 "; SELECT_CC_Int_ICC PSEUDO!", 260 [(set i32:$dst, (SPselecticc i32:$T, i32:$F, imm:$Cond))]>; 261 def SELECT_CC_FP_ICC 262 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, i32imm:$Cond), 263 "; SELECT_CC_FP_ICC PSEUDO!", 264 [(set f32:$dst, (SPselecticc f32:$T, f32:$F, imm:$Cond))]>; 265 266 def SELECT_CC_DFP_ICC 267 : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, i32imm:$Cond), 268 "; SELECT_CC_DFP_ICC PSEUDO!", 269 [(set f64:$dst, (SPselecticc f64:$T, f64:$F, imm:$Cond))]>; 270} 271 272let usesCustomInserter = 1, Uses = [FCC] in { 273 274 def SELECT_CC_Int_FCC 275 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond), 276 "; SELECT_CC_Int_FCC PSEUDO!", 277 [(set i32:$dst, (SPselectfcc i32:$T, i32:$F, imm:$Cond))]>; 278 279 def SELECT_CC_FP_FCC 280 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, i32imm:$Cond), 281 "; SELECT_CC_FP_FCC PSEUDO!", 282 [(set f32:$dst, (SPselectfcc f32:$T, f32:$F, imm:$Cond))]>; 283 def SELECT_CC_DFP_FCC 284 : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, i32imm:$Cond), 285 "; SELECT_CC_DFP_FCC PSEUDO!", 286 [(set f64:$dst, (SPselectfcc f64:$T, f64:$F, imm:$Cond))]>; 287} 288 289 290// Section A.3 - Synthetic Instructions, p. 85 291// special cases of JMPL: 292let isReturn = 1, isTerminator = 1, hasDelaySlot = 1, isBarrier = 1 in { 293 let rd = 0, rs1 = 15 in 294 def RETL: F3_2<2, 0b111000, (outs), (ins i32imm:$val), 295 "jmp %o7+$val", [(retflag simm13:$val)]>; 296 297 let rd = 0, rs1 = 31 in 298 def RET: F3_2<2, 0b111000, (outs), (ins i32imm:$val), 299 "jmp %i7+$val", []>; 300} 301 302// Section B.1 - Load Integer Instructions, p. 90 303def LDSBrr : F3_1<3, 0b001001, 304 (outs IntRegs:$dst), (ins MEMrr:$addr), 305 "ldsb [$addr], $dst", 306 [(set i32:$dst, (sextloadi8 ADDRrr:$addr))]>; 307def LDSBri : F3_2<3, 0b001001, 308 (outs IntRegs:$dst), (ins MEMri:$addr), 309 "ldsb [$addr], $dst", 310 [(set i32:$dst, (sextloadi8 ADDRri:$addr))]>; 311def LDSHrr : F3_1<3, 0b001010, 312 (outs IntRegs:$dst), (ins MEMrr:$addr), 313 "ldsh [$addr], $dst", 314 [(set i32:$dst, (sextloadi16 ADDRrr:$addr))]>; 315def LDSHri : F3_2<3, 0b001010, 316 (outs IntRegs:$dst), (ins MEMri:$addr), 317 "ldsh [$addr], $dst", 318 [(set i32:$dst, (sextloadi16 ADDRri:$addr))]>; 319def LDUBrr : F3_1<3, 0b000001, 320 (outs IntRegs:$dst), (ins MEMrr:$addr), 321 "ldub [$addr], $dst", 322 [(set i32:$dst, (zextloadi8 ADDRrr:$addr))]>; 323def LDUBri : F3_2<3, 0b000001, 324 (outs IntRegs:$dst), (ins MEMri:$addr), 325 "ldub [$addr], $dst", 326 [(set i32:$dst, (zextloadi8 ADDRri:$addr))]>; 327def LDUHrr : F3_1<3, 0b000010, 328 (outs IntRegs:$dst), (ins MEMrr:$addr), 329 "lduh [$addr], $dst", 330 [(set i32:$dst, (zextloadi16 ADDRrr:$addr))]>; 331def LDUHri : F3_2<3, 0b000010, 332 (outs IntRegs:$dst), (ins MEMri:$addr), 333 "lduh [$addr], $dst", 334 [(set i32:$dst, (zextloadi16 ADDRri:$addr))]>; 335def LDrr : F3_1<3, 0b000000, 336 (outs IntRegs:$dst), (ins MEMrr:$addr), 337 "ld [$addr], $dst", 338 [(set i32:$dst, (load ADDRrr:$addr))]>; 339def LDri : F3_2<3, 0b000000, 340 (outs IntRegs:$dst), (ins MEMri:$addr), 341 "ld [$addr], $dst", 342 [(set i32:$dst, (load ADDRri:$addr))]>; 343 344// Section B.2 - Load Floating-point Instructions, p. 92 345def LDFrr : F3_1<3, 0b100000, 346 (outs FPRegs:$dst), (ins MEMrr:$addr), 347 "ld [$addr], $dst", 348 [(set f32:$dst, (load ADDRrr:$addr))]>; 349def LDFri : F3_2<3, 0b100000, 350 (outs FPRegs:$dst), (ins MEMri:$addr), 351 "ld [$addr], $dst", 352 [(set f32:$dst, (load ADDRri:$addr))]>; 353def LDDFrr : F3_1<3, 0b100011, 354 (outs DFPRegs:$dst), (ins MEMrr:$addr), 355 "ldd [$addr], $dst", 356 [(set f64:$dst, (load ADDRrr:$addr))]>; 357def LDDFri : F3_2<3, 0b100011, 358 (outs DFPRegs:$dst), (ins MEMri:$addr), 359 "ldd [$addr], $dst", 360 [(set f64:$dst, (load ADDRri:$addr))]>; 361def LDQFrr : F3_1<3, 0b100010, 362 (outs QFPRegs:$dst), (ins MEMrr:$addr), 363 "ldq [$addr], $dst", 364 [(set f128:$dst, (load ADDRrr:$addr))]>, 365 Requires<[HasV9, HasHardQuad]>; 366def LDQFri : F3_2<3, 0b100010, 367 (outs QFPRegs:$dst), (ins MEMri:$addr), 368 "ldq [$addr], $dst", 369 [(set f128:$dst, (load ADDRri:$addr))]>, 370 Requires<[HasV9, HasHardQuad]>; 371 372// Section B.4 - Store Integer Instructions, p. 95 373def STBrr : F3_1<3, 0b000101, 374 (outs), (ins MEMrr:$addr, IntRegs:$src), 375 "stb $src, [$addr]", 376 [(truncstorei8 i32:$src, ADDRrr:$addr)]>; 377def STBri : F3_2<3, 0b000101, 378 (outs), (ins MEMri:$addr, IntRegs:$src), 379 "stb $src, [$addr]", 380 [(truncstorei8 i32:$src, ADDRri:$addr)]>; 381def STHrr : F3_1<3, 0b000110, 382 (outs), (ins MEMrr:$addr, IntRegs:$src), 383 "sth $src, [$addr]", 384 [(truncstorei16 i32:$src, ADDRrr:$addr)]>; 385def STHri : F3_2<3, 0b000110, 386 (outs), (ins MEMri:$addr, IntRegs:$src), 387 "sth $src, [$addr]", 388 [(truncstorei16 i32:$src, ADDRri:$addr)]>; 389def STrr : F3_1<3, 0b000100, 390 (outs), (ins MEMrr:$addr, IntRegs:$src), 391 "st $src, [$addr]", 392 [(store i32:$src, ADDRrr:$addr)]>; 393def STri : F3_2<3, 0b000100, 394 (outs), (ins MEMri:$addr, IntRegs:$src), 395 "st $src, [$addr]", 396 [(store i32:$src, ADDRri:$addr)]>; 397 398// Section B.5 - Store Floating-point Instructions, p. 97 399def STFrr : F3_1<3, 0b100100, 400 (outs), (ins MEMrr:$addr, FPRegs:$src), 401 "st $src, [$addr]", 402 [(store f32:$src, ADDRrr:$addr)]>; 403def STFri : F3_2<3, 0b100100, 404 (outs), (ins MEMri:$addr, FPRegs:$src), 405 "st $src, [$addr]", 406 [(store f32:$src, ADDRri:$addr)]>; 407def STDFrr : F3_1<3, 0b100111, 408 (outs), (ins MEMrr:$addr, DFPRegs:$src), 409 "std $src, [$addr]", 410 [(store f64:$src, ADDRrr:$addr)]>; 411def STDFri : F3_2<3, 0b100111, 412 (outs), (ins MEMri:$addr, DFPRegs:$src), 413 "std $src, [$addr]", 414 [(store f64:$src, ADDRri:$addr)]>; 415def STQFrr : F3_1<3, 0b100110, 416 (outs), (ins MEMrr:$addr, QFPRegs:$src), 417 "stq $src, [$addr]", 418 [(store f128:$src, ADDRrr:$addr)]>, 419 Requires<[HasV9, HasHardQuad]>; 420def STQFri : F3_2<3, 0b100110, 421 (outs), (ins MEMri:$addr, QFPRegs:$src), 422 "stq $src, [$addr]", 423 [(store f128:$src, ADDRri:$addr)]>, 424 Requires<[HasV9, HasHardQuad]>; 425 426// Section B.9 - SETHI Instruction, p. 104 427def SETHIi: F2_1<0b100, 428 (outs IntRegs:$dst), (ins i32imm:$src), 429 "sethi $src, $dst", 430 [(set i32:$dst, SETHIimm:$src)]>; 431 432// Section B.10 - NOP Instruction, p. 105 433// (It's a special case of SETHI) 434let rd = 0, imm22 = 0 in 435 def NOP : F2_1<0b100, (outs), (ins), "nop", []>; 436 437// Section B.11 - Logical Instructions, p. 106 438defm AND : F3_12<"and", 0b000001, and>; 439 440def ANDNrr : F3_1<2, 0b000101, 441 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c), 442 "andn $b, $c, $dst", 443 [(set i32:$dst, (and i32:$b, (not i32:$c)))]>; 444def ANDNri : F3_2<2, 0b000101, 445 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c), 446 "andn $b, $c, $dst", []>; 447 448defm OR : F3_12<"or", 0b000010, or>; 449 450def ORNrr : F3_1<2, 0b000110, 451 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c), 452 "orn $b, $c, $dst", 453 [(set i32:$dst, (or i32:$b, (not i32:$c)))]>; 454def ORNri : F3_2<2, 0b000110, 455 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c), 456 "orn $b, $c, $dst", []>; 457defm XOR : F3_12<"xor", 0b000011, xor>; 458 459def XNORrr : F3_1<2, 0b000111, 460 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c), 461 "xnor $b, $c, $dst", 462 [(set i32:$dst, (not (xor i32:$b, i32:$c)))]>; 463def XNORri : F3_2<2, 0b000111, 464 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c), 465 "xnor $b, $c, $dst", []>; 466 467// Section B.12 - Shift Instructions, p. 107 468defm SLL : F3_12<"sll", 0b100101, shl>; 469defm SRL : F3_12<"srl", 0b100110, srl>; 470defm SRA : F3_12<"sra", 0b100111, sra>; 471 472// Section B.13 - Add Instructions, p. 108 473defm ADD : F3_12<"add", 0b000000, add>; 474 475// "LEA" forms of add (patterns to make tblgen happy) 476def LEA_ADDri : F3_2<2, 0b000000, 477 (outs IntRegs:$dst), (ins MEMri:$addr), 478 "add ${addr:arith}, $dst", 479 [(set iPTR:$dst, ADDRri:$addr)]>; 480 481let Defs = [ICC] in 482 defm ADDCC : F3_12<"addcc", 0b010000, addc>; 483 484let Uses = [ICC] in 485 defm ADDX : F3_12<"addx", 0b001000, adde>; 486 487// Section B.15 - Subtract Instructions, p. 110 488defm SUB : F3_12 <"sub" , 0b000100, sub>; 489let Uses = [ICC] in 490 defm SUBX : F3_12 <"subx" , 0b001100, sube>; 491 492let Defs = [ICC] in { 493 defm SUBCC : F3_12 <"subcc", 0b010100, subc>; 494 495 def CMPrr : F3_1<2, 0b010100, 496 (outs), (ins IntRegs:$b, IntRegs:$c), 497 "cmp $b, $c", 498 [(SPcmpicc i32:$b, i32:$c)]>; 499 def CMPri : F3_1<2, 0b010100, 500 (outs), (ins IntRegs:$b, i32imm:$c), 501 "cmp $b, $c", 502 [(SPcmpicc i32:$b, (i32 simm13:$c))]>; 503} 504 505let Uses = [ICC], Defs = [ICC] in 506 def SUBXCCrr: F3_1<2, 0b011100, 507 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c), 508 "subxcc $b, $c, $dst", []>; 509 510 511// Section B.18 - Multiply Instructions, p. 113 512let Defs = [Y] in { 513 defm UMUL : F3_12np<"umul", 0b001010>; 514 defm SMUL : F3_12 <"smul", 0b001011, mul>; 515} 516 517// Section B.19 - Divide Instructions, p. 115 518let Defs = [Y] in { 519 defm UDIV : F3_12np<"udiv", 0b001110>; 520 defm SDIV : F3_12np<"sdiv", 0b001111>; 521} 522 523// Section B.20 - SAVE and RESTORE, p. 117 524defm SAVE : F3_12np<"save" , 0b111100>; 525defm RESTORE : F3_12np<"restore", 0b111101>; 526 527// Section B.21 - Branch on Integer Condition Codes Instructions, p. 119 528 529// conditional branch class: 530class BranchSP<bits<4> cc, dag ins, string asmstr, list<dag> pattern> 531 : F2_2<cc, 0b010, (outs), ins, asmstr, pattern> { 532 let isBranch = 1; 533 let isTerminator = 1; 534 let hasDelaySlot = 1; 535} 536 537let isBarrier = 1 in 538 def BA : BranchSP<0b1000, (ins brtarget:$dst), 539 "ba $dst", 540 [(br bb:$dst)]>; 541 542// Indirect branch instructions. 543let isTerminator = 1, isBarrier = 1, 544 hasDelaySlot = 1, isBranch =1, 545 isIndirectBranch = 1 in { 546 def BINDrr : F3_1<2, 0b111000, 547 (outs), (ins MEMrr:$ptr), 548 "jmp $ptr", 549 [(brind ADDRrr:$ptr)]>; 550 def BINDri : F3_2<2, 0b111000, 551 (outs), (ins MEMri:$ptr), 552 "jmp $ptr", 553 [(brind ADDRri:$ptr)]>; 554} 555 556// FIXME: the encoding for the JIT should look at the condition field. 557let Uses = [ICC] in 558 def BCOND : BranchSP<0, (ins brtarget:$dst, CCOp:$cc), 559 "b$cc $dst", 560 [(SPbricc bb:$dst, imm:$cc)]>; 561 562 563// Section B.22 - Branch on Floating-point Condition Codes Instructions, p. 121 564 565// floating-point conditional branch class: 566class FPBranchSP<bits<4> cc, dag ins, string asmstr, list<dag> pattern> 567 : F2_2<cc, 0b110, (outs), ins, asmstr, pattern> { 568 let isBranch = 1; 569 let isTerminator = 1; 570 let hasDelaySlot = 1; 571} 572 573// FIXME: the encoding for the JIT should look at the condition field. 574let Uses = [FCC] in 575 def FBCOND : FPBranchSP<0, (ins brtarget:$dst, CCOp:$cc), 576 "fb$cc $dst", 577 [(SPbrfcc bb:$dst, imm:$cc)]>; 578 579 580// Section B.24 - Call and Link Instruction, p. 125 581// This is the only Format 1 instruction 582let Uses = [O6], 583 hasDelaySlot = 1, isCall = 1 in { 584 def CALL : InstSP<(outs), (ins calltarget:$dst, variable_ops), 585 "call $dst", []> { 586 bits<30> disp; 587 let op = 1; 588 let Inst{29-0} = disp; 589 } 590 591 // indirect calls 592 def JMPLrr : F3_1<2, 0b111000, 593 (outs), (ins MEMrr:$ptr, variable_ops), 594 "call $ptr", 595 [(call ADDRrr:$ptr)]>; 596 def JMPLri : F3_2<2, 0b111000, 597 (outs), (ins MEMri:$ptr, variable_ops), 598 "call $ptr", 599 [(call ADDRri:$ptr)]>; 600} 601 602// Section B.28 - Read State Register Instructions 603let Uses = [Y] in 604 def RDY : F3_1<2, 0b101000, 605 (outs IntRegs:$dst), (ins), 606 "rd %y, $dst", []>; 607 608// Section B.29 - Write State Register Instructions 609let Defs = [Y] in { 610 def WRYrr : F3_1<2, 0b110000, 611 (outs), (ins IntRegs:$b, IntRegs:$c), 612 "wr $b, $c, %y", []>; 613 def WRYri : F3_2<2, 0b110000, 614 (outs), (ins IntRegs:$b, i32imm:$c), 615 "wr $b, $c, %y", []>; 616} 617// Convert Integer to Floating-point Instructions, p. 141 618def FITOS : F3_3<2, 0b110100, 0b011000100, 619 (outs FPRegs:$dst), (ins FPRegs:$src), 620 "fitos $src, $dst", 621 [(set FPRegs:$dst, (SPitof FPRegs:$src))]>; 622def FITOD : F3_3<2, 0b110100, 0b011001000, 623 (outs DFPRegs:$dst), (ins FPRegs:$src), 624 "fitod $src, $dst", 625 [(set DFPRegs:$dst, (SPitof FPRegs:$src))]>; 626def FITOQ : F3_3<2, 0b110100, 0b011001100, 627 (outs QFPRegs:$dst), (ins FPRegs:$src), 628 "fitoq $src, $dst", 629 [(set QFPRegs:$dst, (SPitof FPRegs:$src))]>, 630 Requires<[HasHardQuad]>; 631 632// Convert Floating-point to Integer Instructions, p. 142 633def FSTOI : F3_3<2, 0b110100, 0b011010001, 634 (outs FPRegs:$dst), (ins FPRegs:$src), 635 "fstoi $src, $dst", 636 [(set FPRegs:$dst, (SPftoi FPRegs:$src))]>; 637def FDTOI : F3_3<2, 0b110100, 0b011010010, 638 (outs FPRegs:$dst), (ins DFPRegs:$src), 639 "fdtoi $src, $dst", 640 [(set FPRegs:$dst, (SPftoi DFPRegs:$src))]>; 641def FQTOI : F3_3<2, 0b110100, 0b011010011, 642 (outs FPRegs:$dst), (ins QFPRegs:$src), 643 "fqtoi $src, $dst", 644 [(set FPRegs:$dst, (SPftoi QFPRegs:$src))]>, 645 Requires<[HasHardQuad]>; 646 647// Convert between Floating-point Formats Instructions, p. 143 648def FSTOD : F3_3<2, 0b110100, 0b011001001, 649 (outs DFPRegs:$dst), (ins FPRegs:$src), 650 "fstod $src, $dst", 651 [(set f64:$dst, (fextend f32:$src))]>; 652def FSTOQ : F3_3<2, 0b110100, 0b011001101, 653 (outs QFPRegs:$dst), (ins FPRegs:$src), 654 "fstoq $src, $dst", 655 [(set f128:$dst, (fextend f32:$src))]>, 656 Requires<[HasHardQuad]>; 657def FDTOS : F3_3<2, 0b110100, 0b011000110, 658 (outs FPRegs:$dst), (ins DFPRegs:$src), 659 "fdtos $src, $dst", 660 [(set f32:$dst, (fround f64:$src))]>; 661def FDTOQ : F3_3<2, 0b110100, 0b01101110, 662 (outs QFPRegs:$dst), (ins DFPRegs:$src), 663 "fdtoq $src, $dst", 664 [(set f128:$dst, (fextend f64:$src))]>, 665 Requires<[HasHardQuad]>; 666def FQTOS : F3_3<2, 0b110100, 0b011000111, 667 (outs FPRegs:$dst), (ins QFPRegs:$src), 668 "fqtos $src, $dst", 669 [(set f32:$dst, (fround f128:$src))]>, 670 Requires<[HasHardQuad]>; 671def FQTOD : F3_3<2, 0b110100, 0b011001011, 672 (outs DFPRegs:$dst), (ins QFPRegs:$src), 673 "fqtod $src, $dst", 674 [(set f64:$dst, (fround f128:$src))]>, 675 Requires<[HasHardQuad]>; 676 677// Floating-point Move Instructions, p. 144 678def FMOVS : F3_3<2, 0b110100, 0b000000001, 679 (outs FPRegs:$dst), (ins FPRegs:$src), 680 "fmovs $src, $dst", []>; 681def FNEGS : F3_3<2, 0b110100, 0b000000101, 682 (outs FPRegs:$dst), (ins FPRegs:$src), 683 "fnegs $src, $dst", 684 [(set f32:$dst, (fneg f32:$src))]>; 685def FABSS : F3_3<2, 0b110100, 0b000001001, 686 (outs FPRegs:$dst), (ins FPRegs:$src), 687 "fabss $src, $dst", 688 [(set f32:$dst, (fabs f32:$src))]>; 689 690 691// Floating-point Square Root Instructions, p.145 692def FSQRTS : F3_3<2, 0b110100, 0b000101001, 693 (outs FPRegs:$dst), (ins FPRegs:$src), 694 "fsqrts $src, $dst", 695 [(set f32:$dst, (fsqrt f32:$src))]>; 696def FSQRTD : F3_3<2, 0b110100, 0b000101010, 697 (outs DFPRegs:$dst), (ins DFPRegs:$src), 698 "fsqrtd $src, $dst", 699 [(set f64:$dst, (fsqrt f64:$src))]>; 700def FSQRTQ : F3_3<2, 0b110100, 0b000101011, 701 (outs QFPRegs:$dst), (ins QFPRegs:$src), 702 "fsqrtq $src, $dst", 703 [(set f128:$dst, (fsqrt f128:$src))]>, 704 Requires<[HasHardQuad]>; 705 706 707 708// Floating-point Add and Subtract Instructions, p. 146 709def FADDS : F3_3<2, 0b110100, 0b001000001, 710 (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2), 711 "fadds $src1, $src2, $dst", 712 [(set f32:$dst, (fadd f32:$src1, f32:$src2))]>; 713def FADDD : F3_3<2, 0b110100, 0b001000010, 714 (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2), 715 "faddd $src1, $src2, $dst", 716 [(set f64:$dst, (fadd f64:$src1, f64:$src2))]>; 717def FADDQ : F3_3<2, 0b110100, 0b001000011, 718 (outs QFPRegs:$dst), (ins QFPRegs:$src1, QFPRegs:$src2), 719 "faddq $src1, $src2, $dst", 720 [(set f128:$dst, (fadd f128:$src1, f128:$src2))]>, 721 Requires<[HasHardQuad]>; 722 723def FSUBS : F3_3<2, 0b110100, 0b001000101, 724 (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2), 725 "fsubs $src1, $src2, $dst", 726 [(set f32:$dst, (fsub f32:$src1, f32:$src2))]>; 727def FSUBD : F3_3<2, 0b110100, 0b001000110, 728 (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2), 729 "fsubd $src1, $src2, $dst", 730 [(set f64:$dst, (fsub f64:$src1, f64:$src2))]>; 731def FSUBQ : F3_3<2, 0b110100, 0b001000111, 732 (outs QFPRegs:$dst), (ins QFPRegs:$src1, QFPRegs:$src2), 733 "fsubq $src1, $src2, $dst", 734 [(set f128:$dst, (fsub f128:$src1, f128:$src2))]>, 735 Requires<[HasHardQuad]>; 736 737 738// Floating-point Multiply and Divide Instructions, p. 147 739def FMULS : F3_3<2, 0b110100, 0b001001001, 740 (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2), 741 "fmuls $src1, $src2, $dst", 742 [(set f32:$dst, (fmul f32:$src1, f32:$src2))]>; 743def FMULD : F3_3<2, 0b110100, 0b001001010, 744 (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2), 745 "fmuld $src1, $src2, $dst", 746 [(set f64:$dst, (fmul f64:$src1, f64:$src2))]>; 747def FMULQ : F3_3<2, 0b110100, 0b001001011, 748 (outs QFPRegs:$dst), (ins QFPRegs:$src1, QFPRegs:$src2), 749 "fmulq $src1, $src2, $dst", 750 [(set f128:$dst, (fmul f128:$src1, f128:$src2))]>, 751 Requires<[HasHardQuad]>; 752 753def FSMULD : F3_3<2, 0b110100, 0b001101001, 754 (outs DFPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2), 755 "fsmuld $src1, $src2, $dst", 756 [(set f64:$dst, (fmul (fextend f32:$src1), 757 (fextend f32:$src2)))]>; 758def FDMULQ : F3_3<2, 0b110100, 0b001101110, 759 (outs QFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2), 760 "fdmulq $src1, $src2, $dst", 761 [(set f128:$dst, (fmul (fextend f64:$src1), 762 (fextend f64:$src2)))]>, 763 Requires<[HasHardQuad]>; 764 765def FDIVS : F3_3<2, 0b110100, 0b001001101, 766 (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2), 767 "fdivs $src1, $src2, $dst", 768 [(set f32:$dst, (fdiv f32:$src1, f32:$src2))]>; 769def FDIVD : F3_3<2, 0b110100, 0b001001110, 770 (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2), 771 "fdivd $src1, $src2, $dst", 772 [(set f64:$dst, (fdiv f64:$src1, f64:$src2))]>; 773def FDIVQ : F3_3<2, 0b110100, 0b001001111, 774 (outs QFPRegs:$dst), (ins QFPRegs:$src1, QFPRegs:$src2), 775 "fdivq $src1, $src2, $dst", 776 [(set f128:$dst, (fdiv f128:$src1, f128:$src2))]>, 777 Requires<[HasHardQuad]>; 778 779// Floating-point Compare Instructions, p. 148 780// Note: the 2nd template arg is different for these guys. 781// Note 2: the result of a FCMP is not available until the 2nd cycle 782// after the instr is retired, but there is no interlock. This behavior 783// is modelled with a forced noop after the instruction. 784let Defs = [FCC] in { 785 def FCMPS : F3_3<2, 0b110101, 0b001010001, 786 (outs), (ins FPRegs:$src1, FPRegs:$src2), 787 "fcmps $src1, $src2\n\tnop", 788 [(SPcmpfcc f32:$src1, f32:$src2)]>; 789 def FCMPD : F3_3<2, 0b110101, 0b001010010, 790 (outs), (ins DFPRegs:$src1, DFPRegs:$src2), 791 "fcmpd $src1, $src2\n\tnop", 792 [(SPcmpfcc f64:$src1, f64:$src2)]>; 793 def FCMPQ : F3_3<2, 0b110101, 0b001010011, 794 (outs), (ins QFPRegs:$src1, QFPRegs:$src2), 795 "fcmpq $src1, $src2\n\tnop", 796 [(SPcmpfcc f128:$src1, f128:$src2)]>, 797 Requires<[HasHardQuad]>; 798} 799 800//===----------------------------------------------------------------------===// 801// V9 Instructions 802//===----------------------------------------------------------------------===// 803 804// V9 Conditional Moves. 805let Predicates = [HasV9], Constraints = "$f = $rd" in { 806 // Move Integer Register on Condition (MOVcc) p. 194 of the V9 manual. 807 // FIXME: Add instruction encodings for the JIT some day. 808 let Uses = [ICC] in { 809 def MOVICCrr 810 : Pseudo<(outs IntRegs:$rd), (ins IntRegs:$rs2, IntRegs:$f, CCOp:$cc), 811 "mov$cc %icc, $rs2, $rd", 812 [(set i32:$rd, (SPselecticc i32:$rs2, i32:$f, imm:$cc))]>; 813 def MOVICCri 814 : Pseudo<(outs IntRegs:$rd), (ins i32imm:$i, IntRegs:$f, CCOp:$cc), 815 "mov$cc %icc, $i, $rd", 816 [(set i32:$rd, (SPselecticc simm11:$i, i32:$f, imm:$cc))]>; 817 } 818 819 let Uses = [FCC] in { 820 def MOVFCCrr 821 : Pseudo<(outs IntRegs:$rd), (ins IntRegs:$rs2, IntRegs:$f, CCOp:$cc), 822 "mov$cc %fcc0, $rs2, $rd", 823 [(set i32:$rd, (SPselectfcc i32:$rs2, i32:$f, imm:$cc))]>; 824 def MOVFCCri 825 : Pseudo<(outs IntRegs:$rd), (ins i32imm:$i, IntRegs:$f, CCOp:$cc), 826 "mov$cc %fcc0, $i, $rd", 827 [(set i32:$rd, (SPselectfcc simm11:$i, i32:$f, imm:$cc))]>; 828 } 829 830 let Uses = [ICC] in { 831 def FMOVS_ICC 832 : Pseudo<(outs FPRegs:$rd), (ins FPRegs:$rs2, FPRegs:$f, CCOp:$cc), 833 "fmovs$cc %icc, $rs2, $rd", 834 [(set f32:$rd, (SPselecticc f32:$rs2, f32:$f, imm:$cc))]>; 835 def FMOVD_ICC 836 : Pseudo<(outs DFPRegs:$rd), (ins DFPRegs:$rs2, DFPRegs:$f, CCOp:$cc), 837 "fmovd$cc %icc, $rs2, $rd", 838 [(set f64:$rd, (SPselecticc f64:$rs2, f64:$f, imm:$cc))]>; 839 } 840 841 let Uses = [FCC] in { 842 def FMOVS_FCC 843 : Pseudo<(outs FPRegs:$rd), (ins FPRegs:$rs2, FPRegs:$f, CCOp:$cc), 844 "fmovs$cc %fcc0, $rs2, $rd", 845 [(set f32:$rd, (SPselectfcc f32:$rs2, f32:$f, imm:$cc))]>; 846 def FMOVD_FCC 847 : Pseudo<(outs DFPRegs:$rd), (ins DFPRegs:$rs2, DFPRegs:$f, CCOp:$cc), 848 "fmovd$cc %fcc0, $rs2, $rd", 849 [(set f64:$rd, (SPselectfcc f64:$rs2, f64:$f, imm:$cc))]>; 850 } 851 852} 853 854// Floating-Point Move Instructions, p. 164 of the V9 manual. 855let Predicates = [HasV9] in { 856 def FMOVD : F3_3<2, 0b110100, 0b000000010, 857 (outs DFPRegs:$dst), (ins DFPRegs:$src), 858 "fmovd $src, $dst", []>; 859 def FMOVQ : F3_3<2, 0b110100, 0b000000011, 860 (outs QFPRegs:$dst), (ins QFPRegs:$src), 861 "fmovq $src, $dst", []>, 862 Requires<[HasHardQuad]>; 863 def FNEGD : F3_3<2, 0b110100, 0b000000110, 864 (outs DFPRegs:$dst), (ins DFPRegs:$src), 865 "fnegd $src, $dst", 866 [(set f64:$dst, (fneg f64:$src))]>; 867 def FNEGQ : F3_3<2, 0b110100, 0b000000111, 868 (outs QFPRegs:$dst), (ins QFPRegs:$src), 869 "fnegq $src, $dst", 870 [(set f128:$dst, (fneg f128:$src))]>, 871 Requires<[HasHardQuad]>; 872 def FABSD : F3_3<2, 0b110100, 0b000001010, 873 (outs DFPRegs:$dst), (ins DFPRegs:$src), 874 "fabsd $src, $dst", 875 [(set f64:$dst, (fabs f64:$src))]>; 876 def FABSQ : F3_3<2, 0b110100, 0b000001011, 877 (outs QFPRegs:$dst), (ins QFPRegs:$src), 878 "fabsq $src, $dst", 879 [(set f128:$dst, (fabs f128:$src))]>, 880 Requires<[HasHardQuad]>; 881} 882 883// POPCrr - This does a ctpop of a 64-bit register. As such, we have to clear 884// the top 32-bits before using it. To do this clearing, we use a SLLri X,0. 885def POPCrr : F3_1<2, 0b101110, 886 (outs IntRegs:$dst), (ins IntRegs:$src), 887 "popc $src, $dst", []>, Requires<[HasV9]>; 888def : Pat<(ctpop i32:$src), 889 (POPCrr (SLLri $src, 0))>; 890 891//===----------------------------------------------------------------------===// 892// Non-Instruction Patterns 893//===----------------------------------------------------------------------===// 894 895// Small immediates. 896def : Pat<(i32 simm13:$val), 897 (ORri (i32 G0), imm:$val)>; 898// Arbitrary immediates. 899def : Pat<(i32 imm:$val), 900 (ORri (SETHIi (HI22 imm:$val)), (LO10 imm:$val))>; 901 902 903// Global addresses, constant pool entries 904def : Pat<(SPhi tglobaladdr:$in), (SETHIi tglobaladdr:$in)>; 905def : Pat<(SPlo tglobaladdr:$in), (ORri (i32 G0), tglobaladdr:$in)>; 906def : Pat<(SPhi tconstpool:$in), (SETHIi tconstpool:$in)>; 907def : Pat<(SPlo tconstpool:$in), (ORri (i32 G0), tconstpool:$in)>; 908 909// Blockaddress 910def : Pat<(SPhi tblockaddress:$in), (SETHIi tblockaddress:$in)>; 911def : Pat<(SPlo tblockaddress:$in), (ORri (i32 G0), tblockaddress:$in)>; 912 913// Add reg, lo. This is used when taking the addr of a global/constpool entry. 914def : Pat<(add iPTR:$r, (SPlo tglobaladdr:$in)), (ADDri $r, tglobaladdr:$in)>; 915def : Pat<(add iPTR:$r, (SPlo tconstpool:$in)), (ADDri $r, tconstpool:$in)>; 916def : Pat<(add iPTR:$r, (SPlo tblockaddress:$in)), 917 (ADDri $r, tblockaddress:$in)>; 918 919// Calls: 920def : Pat<(call tglobaladdr:$dst), 921 (CALL tglobaladdr:$dst)>; 922def : Pat<(call texternalsym:$dst), 923 (CALL texternalsym:$dst)>; 924 925// Map integer extload's to zextloads. 926def : Pat<(i32 (extloadi1 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>; 927def : Pat<(i32 (extloadi1 ADDRri:$src)), (LDUBri ADDRri:$src)>; 928def : Pat<(i32 (extloadi8 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>; 929def : Pat<(i32 (extloadi8 ADDRri:$src)), (LDUBri ADDRri:$src)>; 930def : Pat<(i32 (extloadi16 ADDRrr:$src)), (LDUHrr ADDRrr:$src)>; 931def : Pat<(i32 (extloadi16 ADDRri:$src)), (LDUHri ADDRri:$src)>; 932 933// zextload bool -> zextload byte 934def : Pat<(i32 (zextloadi1 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>; 935def : Pat<(i32 (zextloadi1 ADDRri:$src)), (LDUBri ADDRri:$src)>; 936 937// store 0, addr -> store %g0, addr 938def : Pat<(store (i32 0), ADDRrr:$dst), (STrr ADDRrr:$dst, (i32 G0))>; 939def : Pat<(store (i32 0), ADDRri:$dst), (STri ADDRri:$dst, (i32 G0))>; 940 941include "SparcInstr64Bit.td" 942