SparcInstrInfo.td revision 3ff57516839433131dd537ed2708a3e23f88ae77
1//===- SparcV8Instrs.td - Target Description for SparcV8 Target -----------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the SparcV8 instructions in TableGen format. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// Instruction format superclass 16//===----------------------------------------------------------------------===// 17 18class InstV8 : Instruction { // SparcV8 instruction baseline 19 field bits<32> Inst; 20 21 let Namespace = "V8"; 22 23 bits<2> op; 24 let Inst{31-30} = op; // Top two bits are the 'op' field 25 26 // Bit attributes specific to SparcV8 instructions 27 bit isPasi = 0; // Does this instruction affect an alternate addr space? 28 bit isPrivileged = 0; // Is this a privileged instruction? 29} 30 31include "SparcV8InstrFormats.td" 32 33//===----------------------------------------------------------------------===// 34// Instructions 35//===----------------------------------------------------------------------===// 36 37// Pseudo instructions. 38class PseudoInstV8<string nm, dag ops> : InstV8 { 39 let Name = nm; 40 dag OperandList = ops; 41} 42def PHI : PseudoInstV8<"PHI", (ops variable_ops)>; 43def ADJCALLSTACKDOWN : PseudoInstV8<"ADJCALLSTACKDOWN", (ops variable_ops)>; 44def ADJCALLSTACKUP : PseudoInstV8<"ADJCALLSTACKUP", (ops variable_ops)>; 45def IMPLICIT_USE : PseudoInstV8<"IMPLICIT_USE", (ops variable_ops)>; 46def IMPLICIT_DEF : PseudoInstV8<"IMPLICIT_DEF", (ops variable_ops)>; 47def FpMOVD : PseudoInstV8<"FpMOVD", (ops)>; // pseudo 64-bit double move 48 49// Section A.3 - Synthetic Instructions, p. 85 50// special cases of JMPL: 51let isReturn = 1, isTerminator = 1, hasDelaySlot = 1 in { 52 let rd = I7.Num, rs1 = G0.Num, simm13 = 8 in 53 def RET : F3_2<2, 0b111000, "ret">; 54 let rd = O7.Num, rs1 = G0.Num, simm13 = 8 in 55 def RETL: F3_2<2, 0b111000, "retl">; 56} 57// CMP is a special case of SUBCC where destination is ignored, by setting it to 58// %g0 (hardwired zero). 59// FIXME: should keep track of the fact that it defs the integer condition codes 60let rd = 0 in 61 def CMPri: F3_2<2, 0b010100, "cmp">; 62 63// Section B.1 - Load Integer Instructions, p. 90 64def LDSB: F3_2<3, 0b001001, "ldsb">; 65def LDSH: F3_2<3, 0b001010, "ldsh">; 66def LDUB: F3_2<3, 0b000001, "ldub">; 67def LDUH: F3_2<3, 0b000010, "lduh">; 68def LD : F3_2<3, 0b000000, "ld">; 69def LDD : F3_2<3, 0b000011, "ldd">; 70 71// Section B.2 - Load Floating-point Instructions, p. 92 72def LDFrr : F3_1<3, 0b100000, "ld">; 73def LDFri : F3_2<3, 0b100000, "ld">; 74def LDDFrr : F3_1<3, 0b100011, "ldd">; 75def LDDFri : F3_2<3, 0b100011, "ldd">; 76def LDFSRrr: F3_1<3, 0b100001, "ld">; 77def LDFSRri: F3_2<3, 0b100001, "ld">; 78 79// Section B.4 - Store Integer Instructions, p. 95 80def STB : F3_2<3, 0b000101, "stb">; 81def STH : F3_2<3, 0b000110, "sth">; 82def ST : F3_2<3, 0b000100, "st">; 83def STD : F3_2<3, 0b000111, "std">; 84 85// Section B.5 - Store Floating-point Instructions, p. 97 86def STFrr : F3_1<3, 0b100100, "st">; 87def STFri : F3_2<3, 0b100100, "st">; 88def STDFrr : F3_1<3, 0b100111, "std">; 89def STDFri : F3_2<3, 0b100111, "std">; 90def STFSRrr : F3_1<3, 0b100101, "st">; 91def STFSRri : F3_2<3, 0b100101, "st">; 92def STDFQrr : F3_1<3, 0b100110, "std">; 93def STDFQri : F3_2<3, 0b100110, "std">; 94 95// Section B.9 - SETHI Instruction, p. 104 96def SETHIi: F2_1<0b100, "sethi">; 97 98// Section B.10 - NOP Instruction, p. 105 99// (It's a special case of SETHI) 100let rd = 0, imm22 = 0 in 101 def NOP : F2_1<0b100, "nop">; 102 103// Section B.11 - Logical Instructions, p. 106 104def ANDrr : F3_1<2, 0b000001, "and">; 105def ANDri : F3_2<2, 0b000001, "and">; 106def ANDCCrr : F3_1<2, 0b010001, "andcc">; 107def ANDCCri : F3_2<2, 0b010001, "andcc">; 108def ANDNrr : F3_1<2, 0b000101, "andn">; 109def ANDNri : F3_2<2, 0b000101, "andn">; 110def ANDNCCrr: F3_1<2, 0b010101, "andncc">; 111def ANDNCCri: F3_2<2, 0b010101, "andncc">; 112def ORrr : F3_1<2, 0b000010, "or">; 113def ORri : F3_2<2, 0b000010, "or">; 114def ORCCrr : F3_1<2, 0b010010, "orcc">; 115def ORCCri : F3_2<2, 0b010010, "orcc">; 116def ORNrr : F3_1<2, 0b000110, "orn">; 117def ORNri : F3_2<2, 0b000110, "orn">; 118def ORNCCrr : F3_1<2, 0b010110, "orncc">; 119def ORNCCri : F3_2<2, 0b010110, "orncc">; 120def XORrr : F3_1<2, 0b000011, "xor">; 121def XORri : F3_2<2, 0b000011, "xor">; 122def XORCCrr : F3_1<2, 0b010011, "xorcc">; 123def XORCCri : F3_2<2, 0b010011, "xorcc">; 124def XNORrr : F3_1<2, 0b000111, "xnor">; 125def XNORri : F3_2<2, 0b000111, "xnor">; 126def XNORCCrr: F3_1<2, 0b010111, "xnorcc">; 127def XNORCCri: F3_2<2, 0b010111, "xnorcc">; 128 129// Section B.12 - Shift Instructions, p. 107 130def SLLrr : F3_1<2, 0b100101, "sll">; 131def SLLri : F3_2<2, 0b100101, "sll">; 132def SRLrr : F3_1<2, 0b100110, "srl">; 133def SRLri : F3_2<2, 0b100110, "srl">; 134def SRArr : F3_1<2, 0b100111, "sra">; 135def SRAri : F3_2<2, 0b100111, "sra">; 136 137// Section B.13 - Add Instructions, p. 108 138def ADDrr : F3_1<2, 0b000000, "add">; 139def ADDri : F3_2<2, 0b000000, "add">; 140def ADDCCrr : F3_1<2, 0b010000, "addcc">; 141def ADDCCri : F3_2<2, 0b010000, "addcc">; 142def ADDXrr : F3_1<2, 0b001000, "addx">; 143def ADDXri : F3_2<2, 0b001000, "addx">; 144def ADDXCCrr: F3_1<2, 0b011000, "addxcc">; 145def ADDXCCri: F3_2<2, 0b011000, "addxcc">; 146 147// Section B.15 - Subtract Instructions, p. 110 148def SUBrr : F3_1<2, 0b000100, "sub">; 149def SUBri : F3_2<2, 0b000100, "sub">; 150def SUBCCrr : F3_1<2, 0b010100, "subcc">; 151def SUBCCri : F3_2<2, 0b010100, "subcc">; 152def SUBXrr : F3_1<2, 0b001100, "subx">; 153def SUBXri : F3_2<2, 0b001100, "subx">; 154def SUBXCCrr: F3_1<2, 0b011100, "subxcc">; 155def SUBXCCri: F3_2<2, 0b011100, "subxcc">; 156 157// Section B.18 - Multiply Instructions, p. 113 158def UMULrr : F3_1<2, 0b001010, "umul">; 159def UMULri : F3_2<2, 0b001010, "umul">; 160def SMULrr : F3_1<2, 0b001011, "smul">; 161def SMULri : F3_2<2, 0b001011, "smul">; 162def UMULCCrr: F3_1<2, 0b011010, "umulcc">; 163def UMULCCri: F3_2<2, 0b011010, "umulcc">; 164def SMULCCrr: F3_1<2, 0b011011, "smulcc">; 165def SMULCCri: F3_2<2, 0b011011, "smulcc">; 166 167// Section B.19 - Divide Instructions, p. 115 168def UDIVrr : F3_1<2, 0b001110, "udiv">; 169def UDIVri : F3_2<2, 0b001110, "udiv">; 170def SDIVrr : F3_1<2, 0b001111, "sdiv">; 171def SDIVri : F3_2<2, 0b001111, "sdiv">; 172def UDIVCCrr : F3_1<2, 0b011110, "udivcc">; 173def UDIVCCri : F3_2<2, 0b011110, "udivcc">; 174def SDIVCCrr : F3_1<2, 0b011111, "sdivcc">; 175def SDIVCCri : F3_2<2, 0b011111, "sdivcc">; 176 177// Section B.20 - SAVE and RESTORE, p. 117 178def SAVErr : F3_1<2, 0b111100, "save">; // save r, r, r 179def SAVEri : F3_2<2, 0b111100, "save">; // save r, i, r 180def RESTORErr : F3_1<2, 0b111101, "restore">; // restore r, r, r 181def RESTOREri : F3_2<2, 0b111101, "restore">; // restore r, i, r 182 183// Section B.21 - Branch on Integer Condition Codes Instructions, p. 119 184 185// conditional branch class: 186class BranchV8<bits<4> cc, string nm> : F2_2<cc, 0b010, nm> { 187 let isBranch = 1; 188 let isTerminator = 1; 189 let hasDelaySlot = 1; 190} 191 192let isBarrier = 1 in 193 def BA : BranchV8<0b1000, "ba">; 194def BN : BranchV8<0b0000, "bn">; 195def BNE : BranchV8<0b1001, "bne">; 196def BE : BranchV8<0b0001, "be">; 197def BG : BranchV8<0b1010, "bg">; 198def BLE : BranchV8<0b0010, "ble">; 199def BGE : BranchV8<0b1011, "bge">; 200def BL : BranchV8<0b0011, "bl">; 201def BGU : BranchV8<0b1100, "bgu">; 202def BLEU : BranchV8<0b0100, "bleu">; 203def BCC : BranchV8<0b1101, "bcc">; 204def BCS : BranchV8<0b0101, "bcs">; 205 206// Section B.22 - Branch on Floating-point Condition Codes Instructions, p. 121 207 208// floating-point conditional branch class: 209class FPBranchV8<bits<4> cc, string nm> : F2_2<cc, 0b110, nm> { 210 let isBranch = 1; 211 let isTerminator = 1; 212 let hasDelaySlot = 1; 213} 214 215def FBA : FPBranchV8<0b1000, "fba">; 216def FBN : FPBranchV8<0b0000, "fbn">; 217def FBU : FPBranchV8<0b0111, "fbu">; 218def FBG : FPBranchV8<0b0110, "fbg">; 219def FBUG : FPBranchV8<0b0101, "fbug">; 220def FBL : FPBranchV8<0b0100, "fbl">; 221def FBUL : FPBranchV8<0b0011, "fbul">; 222def FBLG : FPBranchV8<0b0010, "fblg">; 223def FBNE : FPBranchV8<0b0001, "fbne">; 224def FBE : FPBranchV8<0b1001, "fbe">; 225def FBUE : FPBranchV8<0b1010, "fbue">; 226def FBGE : FPBranchV8<0b1011, "fbge">; 227def FBUGE: FPBranchV8<0b1100, "fbuge">; 228def FBLE : FPBranchV8<0b1101, "fble">; 229def FBULE: FPBranchV8<0b1110, "fbule">; 230def FBO : FPBranchV8<0b1111, "fbo">; 231 232 233 234// Section B.24 - Call and Link Instruction, p. 125 235// This is the only Format 1 instruction 236let Uses = [O0, O1, O2, O3, O4, O5], hasDelaySlot = 1, isCall = 1 in { 237 // pc-relative call: 238 let Defs = [O0, O1, O2, O3, O4, O5, O7, G1, G2, G3, G4, G5, G6, G7, 239 D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15] in 240 def CALL : InstV8 { 241 bits<30> disp; 242 let op = 1; 243 let Inst{29-0} = disp; 244 let Name = "call"; 245 } 246 247 // indirect call (O7 is an EXPLICIT def in indirect calls, so it cannot also 248 // be an implicit def): 249 let Defs = [O0, O1, O2, O3, O4, O5, G1, G2, G3, G4, G5, G6, G7, 250 D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15] in 251 def JMPLrr : F3_1<2, 0b111000, "jmpl">; // jmpl [rs1+rs2], rd 252} 253 254// Section B.29 - Write State Register Instructions 255def WRrr : F3_1<2, 0b110000, "wr">; // wr rs1, rs2, rd 256def WRri : F3_2<2, 0b110000, "wr">; // wr rs1, imm, rd 257 258// Convert Integer to Floating-point Instructions, p. 141 259def FITOS : F3_3<2, 0b110100, 0b011000100, "fitos">; 260def FITOD : F3_3<2, 0b110100, 0b011001000, "fitod">; 261 262// Convert Floating-point to Integer Instructions, p. 142 263def FSTOI : F3_3<2, 0b110100, 0b011010001, "fstoi">; 264def FDTOI : F3_3<2, 0b110100, 0b011010010, "fdtoi">; 265 266// Convert between Floating-point Formats Instructions, p. 143 267def FSTOD : F3_3<2, 0b110100, 0b011001001, "fstod">; 268def FDTOS : F3_3<2, 0b110100, 0b011000110, "fdtos">; 269 270// Floating-point Move Instructions, p. 144 271def FMOVS : F3_3<2, 0b110100, 0b000000001, "fmovs">; 272def FNEGS : F3_3<2, 0b110100, 0b000000101, "fnegs">; 273def FABSS : F3_3<2, 0b110100, 0b000001001, "fabss">; 274 275// Floating-point Add and Subtract Instructions, p. 146 276def FADDS : F3_3<2, 0b110100, 0b001000001, "fadds">; 277def FADDD : F3_3<2, 0b110100, 0b001000010, "faddd">; 278def FSUBS : F3_3<2, 0b110100, 0b001000101, "fsubs">; 279def FSUBD : F3_3<2, 0b110100, 0b001000110, "fsubd">; 280 281// Floating-point Multiply and Divide Instructions, p. 147 282def FMULS : F3_3<2, 0b110100, 0b001001001, "fmuls">; 283def FMULD : F3_3<2, 0b110100, 0b001001010, "fmuld">; 284def FSMULD : F3_3<2, 0b110100, 0b001101001, "fsmuld">; 285def FDIVS : F3_3<2, 0b110100, 0b001001101, "fdivs">; 286def FDIVD : F3_3<2, 0b110100, 0b001001110, "fdivd">; 287 288// Floating-point Compare Instructions, p. 148 289// Note: the 2nd template arg is different for these guys. 290// Note 2: the result of a FCMP is not available until the 2nd cycle 291// after the instr is retired, but there is no interlock. This behavior 292// is modelled as a delay slot. 293let hasDelaySlot = 1 in { 294 def FCMPS : F3_3<2, 0b110101, 0b001010001, "fcmps">; 295 def FCMPD : F3_3<2, 0b110101, 0b001010010, "fcmpd">; 296 def FCMPES : F3_3<2, 0b110101, 0b001010101, "fcmpes">; 297 def FCMPED : F3_3<2, 0b110101, 0b001010110, "fcmped">; 298} 299 300