SparcInstrInfo.td revision 456b9400dc7aecc6875f521fd4bc87d25c32865b
1//===- SparcV8Instrs.td - Target Description for SparcV8 Target -----------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the SparcV8 instructions in TableGen format. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// Instruction format superclass 16//===----------------------------------------------------------------------===// 17 18class InstV8 : Instruction { // SparcV8 instruction baseline 19 field bits<32> Inst; 20 21 let Namespace = "V8"; 22 23 bits<2> op; 24 let Inst{31-30} = op; // Top two bits are the 'op' field 25 26 // Bit attributes specific to SparcV8 instructions 27 bit isPasi = 0; // Does this instruction affect an alternate addr space? 28 bit isPrivileged = 0; // Is this a privileged instruction? 29} 30 31include "SparcV8InstrFormats.td" 32 33//===----------------------------------------------------------------------===// 34// Instruction Pattern Stuff 35//===----------------------------------------------------------------------===// 36 37def simm13 : PatLeaf<(imm), [{ 38 // simm13 predicate - True if the imm fits in a 13-bit sign extended field. 39 return (((int)N->getValue() << (32-13)) >> (32-13)) == (int)N->getValue(); 40}]>; 41 42def LO10 : SDNodeXForm<imm, [{ 43 return CurDAG->getTargetConstant((unsigned)N->getValue() & 1023, MVT::i32); 44}]>; 45 46def HI22 : SDNodeXForm<imm, [{ 47 // Transformation function: shift the immediate value down into the low bits. 48 return CurDAG->getTargetConstant((unsigned)N->getValue() >> 10, MVT::i32); 49}]>; 50 51def SETHIimm : PatLeaf<(imm), [{ 52 return (((unsigned)N->getValue() >> 10) << 10) == (unsigned)N->getValue(); 53}], HI22>; 54 55// Addressing modes. 56def ADDRrr : ComplexPattern<i32, 2, "SelectADDRrr", []>; 57def ADDRri : ComplexPattern<i32, 2, "SelectADDRri", []>; 58 59// Address operands 60def MEMrr : Operand<i32> { 61 let PrintMethod = "printMemOperand"; 62 let NumMIOperands = 2; 63 let MIOperandInfo = (ops IntRegs, IntRegs); 64} 65def MEMri : Operand<i32> { 66 let PrintMethod = "printMemOperand"; 67 let NumMIOperands = 2; 68 let MIOperandInfo = (ops IntRegs, i32imm); 69} 70 71def SDTV8cmpicc : 72SDTypeProfile<1, 2, [SDTCisVT<0, FlagVT>, SDTCisInt<1>, SDTCisSameAs<1, 2>]>; 73def SDTV8cmpfcc : 74SDTypeProfile<1, 2, [SDTCisVT<0, FlagVT>, SDTCisFP<1>, SDTCisSameAs<1, 2>]>; 75def SDTV8brcc : 76SDTypeProfile<0, 3, [SDTCisInt<0>, SDTCisVT<1, OtherVT>, SDTCisVT<2, FlagVT>]>; 77 78def V8cmpicc : SDNode<"V8ISD::CMPICC", SDTV8cmpicc>; 79def V8cmpfcc : SDNode<"V8ISD::CMPFCC", SDTV8cmpfcc>; 80def V8bricc : SDNode<"V8ISD::BRICC", SDTV8brcc, [SDNPHasChain]>; 81def V8brfcc : SDNode<"V8ISD::BRFCC", SDTV8brcc, [SDNPHasChain]>; 82 83 84//===----------------------------------------------------------------------===// 85// Instructions 86//===----------------------------------------------------------------------===// 87 88// Pseudo instructions. 89class PseudoInstV8<string asmstr, dag ops> : InstV8 { 90 let AsmString = asmstr; 91 dag OperandList = ops; 92} 93def PHI : PseudoInstV8<"PHI", (ops variable_ops)>; 94def ADJCALLSTACKDOWN : PseudoInstV8<"!ADJCALLSTACKDOWN $amt", 95 (ops i32imm:$amt)>; 96def ADJCALLSTACKUP : PseudoInstV8<"!ADJCALLSTACKUP $amt", 97 (ops i32imm:$amt)>; 98//def IMPLICIT_USE : PseudoInstV8<"!IMPLICIT_USE",(ops variable_ops)>; 99def IMPLICIT_DEF : PseudoInstV8<"!IMPLICIT_DEF $dst", 100 (ops IntRegs:$dst)>; 101def FpMOVD : PseudoInstV8<"!FpMOVD", (ops)>; // pseudo 64-bit double move 102 103// Section A.3 - Synthetic Instructions, p. 85 104// special cases of JMPL: 105let isReturn = 1, isTerminator = 1, hasDelaySlot = 1 in { 106 let rd = O7.Num, rs1 = G0.Num, simm13 = 8 in 107 def RETL: F3_2<2, 0b111000, (ops), 108 "retl", [(ret)]>; 109} 110 111// Section B.1 - Load Integer Instructions, p. 90 112def LDSBrr : F3_1<3, 0b001001, 113 (ops IntRegs:$dst, MEMrr:$addr), 114 "ldsb [$addr], $dst", 115 [(set IntRegs:$dst, (sextload ADDRrr:$addr, i8))]>; 116def LDSBri : F3_2<3, 0b001001, 117 (ops IntRegs:$dst, MEMri:$addr), 118 "ldsb [$addr], $dst", 119 [(set IntRegs:$dst, (sextload ADDRri:$addr, i8))]>; 120def LDSHrr : F3_1<3, 0b001010, 121 (ops IntRegs:$dst, MEMrr:$addr), 122 "ldsh [$addr], $dst", 123 [(set IntRegs:$dst, (sextload ADDRrr:$addr, i16))]>; 124def LDSHri : F3_2<3, 0b001010, 125 (ops IntRegs:$dst, MEMri:$addr), 126 "ldsh [$addr], $dst", 127 [(set IntRegs:$dst, (sextload ADDRri:$addr, i16))]>; 128def LDUBrr : F3_1<3, 0b000001, 129 (ops IntRegs:$dst, MEMrr:$addr), 130 "ldub [$addr], $dst", 131 [(set IntRegs:$dst, (zextload ADDRrr:$addr, i8))]>; 132def LDUBri : F3_2<3, 0b000001, 133 (ops IntRegs:$dst, MEMri:$addr), 134 "ldub [$addr], $dst", 135 [(set IntRegs:$dst, (zextload ADDRri:$addr, i8))]>; 136def LDUHrr : F3_1<3, 0b000010, 137 (ops IntRegs:$dst, MEMrr:$addr), 138 "lduh [$addr], $dst", 139 [(set IntRegs:$dst, (zextload ADDRrr:$addr, i16))]>; 140def LDUHri : F3_2<3, 0b000010, 141 (ops IntRegs:$dst, MEMri:$addr), 142 "lduh [$addr], $dst", 143 [(set IntRegs:$dst, (zextload ADDRri:$addr, i16))]>; 144def LDrr : F3_1<3, 0b000000, 145 (ops IntRegs:$dst, MEMrr:$addr), 146 "ld [$addr], $dst", 147 [(set IntRegs:$dst, (load ADDRrr:$addr))]>; 148def LDri : F3_2<3, 0b000000, 149 (ops IntRegs:$dst, MEMri:$addr), 150 "ld [$addr], $dst", 151 [(set IntRegs:$dst, (load ADDRri:$addr))]>; 152def LDDrr : F3_1<3, 0b000011, 153 (ops IntRegs:$dst, MEMrr:$addr), 154 "ldd [$addr], $dst", []>; 155def LDDri : F3_2<3, 0b000011, 156 (ops IntRegs:$dst, MEMri:$addr), 157 "ldd [$addr], $dst", []>; 158 159// Section B.2 - Load Floating-point Instructions, p. 92 160def LDFrr : F3_1<3, 0b100000, 161 (ops FPRegs:$dst, MEMrr:$addr), 162 "ld [$addr], $dst", 163 [(set FPRegs:$dst, (load ADDRrr:$addr))]>; 164def LDFri : F3_2<3, 0b100000, 165 (ops FPRegs:$dst, MEMri:$addr), 166 "ld [$addr], $dst", 167 [(set FPRegs:$dst, (load ADDRri:$addr))]>; 168def LDDFrr : F3_1<3, 0b100011, 169 (ops DFPRegs:$dst, MEMrr:$addr), 170 "ldd [$addr], $dst", 171 [(set DFPRegs:$dst, (load ADDRrr:$addr))]>; 172def LDDFri : F3_2<3, 0b100011, 173 (ops DFPRegs:$dst, MEMri:$addr), 174 "ldd [$addr], $dst", 175 [(set DFPRegs:$dst, (load ADDRri:$addr))]>; 176 177// Section B.4 - Store Integer Instructions, p. 95 178def STBrr : F3_1<3, 0b000101, 179 (ops MEMrr:$addr, IntRegs:$src), 180 "stb $src, [$addr]", 181 [(truncstore IntRegs:$src, ADDRrr:$addr, i8)]>; 182def STBri : F3_2<3, 0b000101, 183 (ops MEMri:$addr, IntRegs:$src), 184 "stb $src, [$addr]", 185 [(truncstore IntRegs:$src, ADDRri:$addr, i8)]>; 186def STHrr : F3_1<3, 0b000110, 187 (ops MEMrr:$addr, IntRegs:$src), 188 "sth $src, [$addr]", 189 [(truncstore IntRegs:$src, ADDRrr:$addr, i16)]>; 190def STHri : F3_2<3, 0b000110, 191 (ops MEMri:$addr, IntRegs:$src), 192 "sth $src, [$addr]", 193 [(truncstore IntRegs:$src, ADDRri:$addr, i16)]>; 194def STrr : F3_1<3, 0b000100, 195 (ops MEMrr:$addr, IntRegs:$src), 196 "st $src, [$addr]", 197 [(store IntRegs:$src, ADDRrr:$addr)]>; 198def STri : F3_2<3, 0b000100, 199 (ops MEMri:$addr, IntRegs:$src), 200 "st $src, [$addr]", 201 [(store IntRegs:$src, ADDRri:$addr)]>; 202def STDrr : F3_1<3, 0b000111, 203 (ops MEMrr:$addr, IntRegs:$src), 204 "std $src, [$addr]", []>; 205def STDri : F3_2<3, 0b000111, 206 (ops MEMri:$addr, IntRegs:$src), 207 "std $src, [$addr]", []>; 208 209// Section B.5 - Store Floating-point Instructions, p. 97 210def STFrr : F3_1<3, 0b100100, 211 (ops MEMrr:$addr, FPRegs:$src), 212 "st $src, [$addr]", 213 [(store FPRegs:$src, ADDRrr:$addr)]>; 214def STFri : F3_2<3, 0b100100, 215 (ops MEMri:$addr, FPRegs:$src), 216 "st $src, [$addr]", 217 [(store FPRegs:$src, ADDRri:$addr)]>; 218def STDFrr : F3_1<3, 0b100111, 219 (ops MEMrr:$addr, DFPRegs:$src), 220 "std $src, [$addr]", 221 [(store DFPRegs:$src, ADDRrr:$addr)]>; 222def STDFri : F3_2<3, 0b100111, 223 (ops MEMri:$addr, DFPRegs:$src), 224 "std $src, [$addr]", 225 [(store DFPRegs:$src, ADDRri:$addr)]>; 226 227// Section B.9 - SETHI Instruction, p. 104 228def SETHIi: F2_1<0b100, 229 (ops IntRegs:$dst, i32imm:$src), 230 "sethi $src, $dst", 231 [(set IntRegs:$dst, SETHIimm:$src)]>; 232 233// Section B.10 - NOP Instruction, p. 105 234// (It's a special case of SETHI) 235let rd = 0, imm22 = 0 in 236 def NOP : F2_1<0b100, (ops), "nop", []>; 237 238// Section B.11 - Logical Instructions, p. 106 239def ANDrr : F3_1<2, 0b000001, 240 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 241 "and $b, $c, $dst", 242 [(set IntRegs:$dst, (and IntRegs:$b, IntRegs:$c))]>; 243def ANDri : F3_2<2, 0b000001, 244 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 245 "and $b, $c, $dst", 246 [(set IntRegs:$dst, (and IntRegs:$b, simm13:$c))]>; 247def ANDNrr : F3_1<2, 0b000101, 248 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 249 "andn $b, $c, $dst", 250 [(set IntRegs:$dst, (and IntRegs:$b, (not IntRegs:$c)))]>; 251def ANDNri : F3_2<2, 0b000101, 252 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 253 "andn $b, $c, $dst", []>; 254def ORrr : F3_1<2, 0b000010, 255 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 256 "or $b, $c, $dst", 257 [(set IntRegs:$dst, (or IntRegs:$b, IntRegs:$c))]>; 258def ORri : F3_2<2, 0b000010, 259 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 260 "or $b, $c, $dst", 261 [(set IntRegs:$dst, (or IntRegs:$b, simm13:$c))]>; 262def ORNrr : F3_1<2, 0b000110, 263 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 264 "orn $b, $c, $dst", 265 [(set IntRegs:$dst, (or IntRegs:$b, (not IntRegs:$c)))]>; 266def ORNri : F3_2<2, 0b000110, 267 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 268 "orn $b, $c, $dst", []>; 269def XORrr : F3_1<2, 0b000011, 270 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 271 "xor $b, $c, $dst", 272 [(set IntRegs:$dst, (xor IntRegs:$b, IntRegs:$c))]>; 273def XORri : F3_2<2, 0b000011, 274 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 275 "xor $b, $c, $dst", 276 [(set IntRegs:$dst, (xor IntRegs:$b, simm13:$c))]>; 277def XNORrr : F3_1<2, 0b000111, 278 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 279 "xnor $b, $c, $dst", 280 [(set IntRegs:$dst, (xor IntRegs:$b, (not IntRegs:$c)))]>; 281def XNORri : F3_2<2, 0b000111, 282 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 283 "xnor $b, $c, $dst", []>; 284 285// Section B.12 - Shift Instructions, p. 107 286def SLLrr : F3_1<2, 0b100101, 287 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 288 "sll $b, $c, $dst", 289 [(set IntRegs:$dst, (shl IntRegs:$b, IntRegs:$c))]>; 290def SLLri : F3_2<2, 0b100101, 291 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 292 "sll $b, $c, $dst", 293 [(set IntRegs:$dst, (shl IntRegs:$b, simm13:$c))]>; 294def SRLrr : F3_1<2, 0b100110, 295 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 296 "srl $b, $c, $dst", 297 [(set IntRegs:$dst, (srl IntRegs:$b, IntRegs:$c))]>; 298def SRLri : F3_2<2, 0b100110, 299 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 300 "srl $b, $c, $dst", 301 [(set IntRegs:$dst, (srl IntRegs:$b, simm13:$c))]>; 302def SRArr : F3_1<2, 0b100111, 303 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 304 "sra $b, $c, $dst", 305 [(set IntRegs:$dst, (sra IntRegs:$b, IntRegs:$c))]>; 306def SRAri : F3_2<2, 0b100111, 307 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 308 "sra $b, $c, $dst", 309 [(set IntRegs:$dst, (sra IntRegs:$b, simm13:$c))]>; 310 311// Section B.13 - Add Instructions, p. 108 312def ADDrr : F3_1<2, 0b000000, 313 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 314 "add $b, $c, $dst", 315 [(set IntRegs:$dst, (add IntRegs:$b, IntRegs:$c))]>; 316def ADDri : F3_2<2, 0b000000, 317 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 318 "add $b, $c, $dst", 319 [(set IntRegs:$dst, (add IntRegs:$b, simm13:$c))]>; 320def ADDCCrr : F3_1<2, 0b010000, 321 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 322 "addcc $b, $c, $dst", []>; 323def ADDCCri : F3_2<2, 0b010000, 324 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 325 "addcc $b, $c, $dst", []>; 326def ADDXrr : F3_1<2, 0b001000, 327 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 328 "addx $b, $c, $dst", []>; 329def ADDXri : F3_2<2, 0b001000, 330 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 331 "addx $b, $c, $dst", []>; 332 333// Section B.15 - Subtract Instructions, p. 110 334def SUBrr : F3_1<2, 0b000100, 335 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 336 "sub $b, $c, $dst", 337 [(set IntRegs:$dst, (sub IntRegs:$b, IntRegs:$c))]>; 338def SUBri : F3_2<2, 0b000100, 339 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 340 "sub $b, $c, $dst", 341 [(set IntRegs:$dst, (sub IntRegs:$b, simm13:$c))]>; 342def SUBXrr : F3_1<2, 0b001100, 343 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 344 "subx $b, $c, $dst", []>; 345def SUBXri : F3_2<2, 0b001100, 346 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 347 "subx $b, $c, $dst", []>; 348def SUBCCrr : F3_1<2, 0b010100, 349 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 350 "subcc $b, $c, $dst", []>; 351def SUBCCri : F3_2<2, 0b010100, 352 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 353 "subcc $b, $c, $dst", []>; 354def SUBXCCrr: F3_1<2, 0b011100, 355 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 356 "subxcc $b, $c, $dst", []>; 357 358// Section B.18 - Multiply Instructions, p. 113 359def UMULrr : F3_1<2, 0b001010, 360 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 361 "umul $b, $c, $dst", []>; 362def UMULri : F3_2<2, 0b001010, 363 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 364 "umul $b, $c, $dst", []>; 365def SMULrr : F3_1<2, 0b001011, 366 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 367 "smul $b, $c, $dst", 368 [(set IntRegs:$dst, (mul IntRegs:$b, IntRegs:$c))]>; 369def SMULri : F3_2<2, 0b001011, 370 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 371 "smul $b, $c, $dst", 372 [(set IntRegs:$dst, (mul IntRegs:$b, simm13:$c))]>; 373 374// Section B.19 - Divide Instructions, p. 115 375def UDIVrr : F3_1<2, 0b001110, 376 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 377 "udiv $b, $c, $dst", []>; 378def UDIVri : F3_2<2, 0b001110, 379 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 380 "udiv $b, $c, $dst", []>; 381def SDIVrr : F3_1<2, 0b001111, 382 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 383 "sdiv $b, $c, $dst", []>; 384def SDIVri : F3_2<2, 0b001111, 385 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 386 "sdiv $b, $c, $dst", []>; 387 388// Section B.20 - SAVE and RESTORE, p. 117 389def SAVErr : F3_1<2, 0b111100, 390 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 391 "save $b, $c, $dst", []>; 392def SAVEri : F3_2<2, 0b111100, 393 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 394 "save $b, $c, $dst", []>; 395def RESTORErr : F3_1<2, 0b111101, 396 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 397 "restore $b, $c, $dst", []>; 398def RESTOREri : F3_2<2, 0b111101, 399 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 400 "restore $b, $c, $dst", []>; 401 402// Section B.21 - Branch on Integer Condition Codes Instructions, p. 119 403 404// conditional branch class: 405class BranchV8<bits<4> cc, dag ops, string asmstr, list<dag> pattern> 406 : F2_2<cc, 0b010, ops, asmstr, pattern> { 407 let isBranch = 1; 408 let isTerminator = 1; 409 let hasDelaySlot = 1; 410} 411 412let isBarrier = 1 in 413 def BA : BranchV8<0b1000, (ops IntRegs:$dst), 414 "ba $dst", []>; 415def BNE : BranchV8<0b1001, (ops IntRegs:$dst), 416 "bne $dst", 417 [(V8bricc IntRegs:$dst, SETNE, ICC)]>; 418def BE : BranchV8<0b0001, (ops IntRegs:$dst), 419 "be $dst", 420 [(V8bricc IntRegs:$dst, SETEQ, ICC)]>; 421def BG : BranchV8<0b1010, (ops IntRegs:$dst), 422 "bg $dst", 423 [(V8bricc IntRegs:$dst, SETGT, ICC)]>; 424def BLE : BranchV8<0b0010, (ops IntRegs:$dst), 425 "ble $dst", 426 [(V8bricc IntRegs:$dst, SETLE, ICC)]>; 427def BGE : BranchV8<0b1011, (ops IntRegs:$dst), 428 "bge $dst", 429 [(V8bricc IntRegs:$dst, SETGE, ICC)]>; 430def BL : BranchV8<0b0011, (ops IntRegs:$dst), 431 "bl $dst", 432 [(V8bricc IntRegs:$dst, SETLT, ICC)]>; 433def BGU : BranchV8<0b1100, (ops IntRegs:$dst), 434 "bgu $dst", 435 [(V8bricc IntRegs:$dst, SETUGT, ICC)]>; 436def BLEU : BranchV8<0b0100, (ops IntRegs:$dst), 437 "bleu $dst", 438 [(V8bricc IntRegs:$dst, SETULE, ICC)]>; 439def BCC : BranchV8<0b1101, (ops IntRegs:$dst), 440 "bcc $dst", 441 [(V8bricc IntRegs:$dst, SETUGE, ICC)]>; 442def BCS : BranchV8<0b0101, (ops IntRegs:$dst), 443 "bcs $dst", 444 [(V8bricc IntRegs:$dst, SETULT, ICC)]>; 445 446// Section B.22 - Branch on Floating-point Condition Codes Instructions, p. 121 447 448// floating-point conditional branch class: 449class FPBranchV8<bits<4> cc, dag ops, string asmstr, list<dag> pattern> 450 : F2_2<cc, 0b110, ops, asmstr, pattern> { 451 let isBranch = 1; 452 let isTerminator = 1; 453 let hasDelaySlot = 1; 454} 455 456def FBU : FPBranchV8<0b0111, (ops IntRegs:$dst), 457 "fbu $dst", 458 [(V8brfcc IntRegs:$dst, SETUO, FCC)]>; 459def FBG : FPBranchV8<0b0110, (ops IntRegs:$dst), 460 "fbg $dst", 461 [(V8brfcc IntRegs:$dst, SETGT, FCC)]>; 462def FBUG : FPBranchV8<0b0101, (ops IntRegs:$dst), 463 "fbug $dst", 464 [(V8brfcc IntRegs:$dst, SETUGT, FCC)]>; 465def FBL : FPBranchV8<0b0100, (ops IntRegs:$dst), 466 "fbl $dst", 467 [(V8brfcc IntRegs:$dst, SETLT, FCC)]>; 468def FBUL : FPBranchV8<0b0011, (ops IntRegs:$dst), 469 "fbul $dst", 470 [(V8brfcc IntRegs:$dst, SETULT, FCC)]>; 471def FBLG : FPBranchV8<0b0010, (ops IntRegs:$dst), 472 "fblg $dst", 473 [(V8brfcc IntRegs:$dst, SETONE, FCC)]>; 474def FBNE : FPBranchV8<0b0001, (ops IntRegs:$dst), 475 "fbne $dst", 476 [(V8brfcc IntRegs:$dst, SETNE, FCC)]>; 477def FBE : FPBranchV8<0b1001, (ops IntRegs:$dst), 478 "fbe $dst", 479 [(V8brfcc IntRegs:$dst, SETEQ, FCC)]>; 480def FBUE : FPBranchV8<0b1010, (ops IntRegs:$dst), 481 "fbue $dst", 482 [(V8brfcc IntRegs:$dst, SETUEQ, FCC)]>; 483def FBGE : FPBranchV8<0b1011, (ops IntRegs:$dst), 484 "fbge $dst", 485 [(V8brfcc IntRegs:$dst, SETGE, FCC)]>; 486def FBUGE: FPBranchV8<0b1100, (ops IntRegs:$dst), 487 "fbuge $dst", 488 [(V8brfcc IntRegs:$dst, SETUGE, FCC)]>; 489def FBLE : FPBranchV8<0b1101, (ops IntRegs:$dst), 490 "fble $dst", 491 [(V8brfcc IntRegs:$dst, SETLE, FCC)]>; 492def FBULE: FPBranchV8<0b1110, (ops IntRegs:$dst), 493 "fbule $dst", 494 [(V8brfcc IntRegs:$dst, SETULE, FCC)]>; 495def FBO : FPBranchV8<0b1111, (ops IntRegs:$dst), 496 "fbo $dst", 497 [(V8brfcc IntRegs:$dst, SETO, FCC)]>; 498 499 500 501// Section B.24 - Call and Link Instruction, p. 125 502// This is the only Format 1 instruction 503let Uses = [O0, O1, O2, O3, O4, O5], hasDelaySlot = 1, isCall = 1 in { 504 // pc-relative call: 505 let Defs = [O0, O1, O2, O3, O4, O5, O7, G1, G2, G3, G4, G5, G6, G7, 506 D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15] in 507 def CALL : InstV8 { 508 let OperandList = (ops IntRegs:$dst); 509 bits<30> disp; 510 let op = 1; 511 let Inst{29-0} = disp; 512 let AsmString = "call $dst"; 513 } 514 515 // indirect call (O7 is an EXPLICIT def in indirect calls, so it cannot also 516 // be an implicit def): 517 let Defs = [O0, O1, O2, O3, O4, O5, G1, G2, G3, G4, G5, G6, G7, 518 D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15] in 519 def JMPLrr : F3_1<2, 0b111000, 520 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 521 "jmpl $b+$c, $dst", []>; 522} 523 524// Section B.28 - Read State Register Instructions 525def RDY : F3_1<2, 0b101000, 526 (ops IntRegs:$dst), 527 "rdy $dst", []>; 528 529// Section B.29 - Write State Register Instructions 530def WRYrr : F3_1<2, 0b110000, 531 (ops IntRegs:$b, IntRegs:$c), 532 "wr $b, $c, %y", []>; 533def WRYri : F3_2<2, 0b110000, 534 (ops IntRegs:$b, i32imm:$c), 535 "wr $b, $c, %y", []>; 536 537// Convert Integer to Floating-point Instructions, p. 141 538def FITOS : F3_3<2, 0b110100, 0b011000100, 539 (ops FPRegs:$dst, FPRegs:$src), 540 "fitos $src, $dst", []>; 541def FITOD : F3_3<2, 0b110100, 0b011001000, 542 (ops DFPRegs:$dst, DFPRegs:$src), 543 "fitod $src, $dst", []>; 544 545// Convert Floating-point to Integer Instructions, p. 142 546def FSTOI : F3_3<2, 0b110100, 0b011010001, 547 (ops FPRegs:$dst, FPRegs:$src), 548 "fstoi $src, $dst", []>; 549def FDTOI : F3_3<2, 0b110100, 0b011010010, 550 (ops DFPRegs:$dst, DFPRegs:$src), 551 "fdtoi $src, $dst", []>; 552 553// Convert between Floating-point Formats Instructions, p. 143 554def FSTOD : F3_3<2, 0b110100, 0b011001001, 555 (ops DFPRegs:$dst, FPRegs:$src), 556 "fstod $src, $dst", 557 [(set DFPRegs:$dst, (fextend FPRegs:$src))]>; 558def FDTOS : F3_3<2, 0b110100, 0b011000110, 559 (ops FPRegs:$dst, DFPRegs:$src), 560 "fdtos $src, $dst", 561 [(set FPRegs:$dst, (fround DFPRegs:$src))]>; 562 563// Floating-point Move Instructions, p. 144 564def FMOVS : F3_3<2, 0b110100, 0b000000001, 565 (ops FPRegs:$dst, FPRegs:$src), 566 "fmovs $src, $dst", []>; 567def FNEGS : F3_3<2, 0b110100, 0b000000101, 568 (ops FPRegs:$dst, FPRegs:$src), 569 "fnegs $src, $dst", 570 [(set FPRegs:$dst, (fneg FPRegs:$src))]>; 571def FABSS : F3_3<2, 0b110100, 0b000001001, 572 (ops FPRegs:$dst, FPRegs:$src), 573 "fabss $src, $dst", 574 [(set FPRegs:$dst, (fabs FPRegs:$src))]>; 575// FIXME: ADD FNEGD/FABSD pseudo instructions. 576 577 578// Floating-point Square Root Instructions, p.145 579def FSQRTS : F3_3<2, 0b110100, 0b000101001, 580 (ops FPRegs:$dst, FPRegs:$src), 581 "fsqrts $src, $dst", 582 [(set FPRegs:$dst, (fsqrt FPRegs:$src))]>; 583def FSQRTD : F3_3<2, 0b110100, 0b000101010, 584 (ops DFPRegs:$dst, DFPRegs:$src), 585 "fsqrtd $src, $dst", 586 [(set DFPRegs:$dst, (fsqrt DFPRegs:$src))]>; 587 588 589 590// Floating-point Add and Subtract Instructions, p. 146 591def FADDS : F3_3<2, 0b110100, 0b001000001, 592 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2), 593 "fadds $src1, $src2, $dst", 594 [(set FPRegs:$dst, (fadd FPRegs:$src1, FPRegs:$src2))]>; 595def FADDD : F3_3<2, 0b110100, 0b001000010, 596 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2), 597 "faddd $src1, $src2, $dst", 598 [(set DFPRegs:$dst, (fadd DFPRegs:$src1, DFPRegs:$src2))]>; 599def FSUBS : F3_3<2, 0b110100, 0b001000101, 600 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2), 601 "fsubs $src1, $src2, $dst", 602 [(set FPRegs:$dst, (fsub FPRegs:$src1, FPRegs:$src2))]>; 603def FSUBD : F3_3<2, 0b110100, 0b001000110, 604 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2), 605 "fsubd $src1, $src2, $dst", 606 [(set DFPRegs:$dst, (fsub DFPRegs:$src1, DFPRegs:$src2))]>; 607 608// Floating-point Multiply and Divide Instructions, p. 147 609def FMULS : F3_3<2, 0b110100, 0b001001001, 610 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2), 611 "fmuls $src1, $src2, $dst", 612 [(set FPRegs:$dst, (fmul FPRegs:$src1, FPRegs:$src2))]>; 613def FMULD : F3_3<2, 0b110100, 0b001001010, 614 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2), 615 "fmuld $src1, $src2, $dst", 616 [(set DFPRegs:$dst, (fmul DFPRegs:$src1, DFPRegs:$src2))]>; 617def FSMULD : F3_3<2, 0b110100, 0b001101001, 618 (ops DFPRegs:$dst, FPRegs:$src1, FPRegs:$src2), 619 "fsmuld $src1, $src2, $dst", 620 [(set DFPRegs:$dst, (fmul (fextend FPRegs:$src1), 621 (fextend FPRegs:$src2)))]>; 622def FDIVS : F3_3<2, 0b110100, 0b001001101, 623 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2), 624 "fdivs $src1, $src2, $dst", 625 [(set FPRegs:$dst, (fdiv FPRegs:$src1, FPRegs:$src2))]>; 626def FDIVD : F3_3<2, 0b110100, 0b001001110, 627 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2), 628 "fdivd $src1, $src2, $dst", 629 [(set DFPRegs:$dst, (fdiv DFPRegs:$src1, DFPRegs:$src2))]>; 630 631// Floating-point Compare Instructions, p. 148 632// Note: the 2nd template arg is different for these guys. 633// Note 2: the result of a FCMP is not available until the 2nd cycle 634// after the instr is retired, but there is no interlock. This behavior 635// is modelled with a forced noop after the instruction. 636def FCMPS : F3_3<2, 0b110101, 0b001010001, 637 (ops FPRegs:$src1, FPRegs:$src2), 638 "fcmps $src1, $src2\n\tnop", 639 [(set FCC, (V8cmpfcc FPRegs:$src1, FPRegs:$src2))]>; 640def FCMPD : F3_3<2, 0b110101, 0b001010010, 641 (ops DFPRegs:$src1, DFPRegs:$src2), 642 "fcmpd $src1, $src2\n\tnop", 643 [(set FCC, (V8cmpfcc DFPRegs:$src1, DFPRegs:$src2))]>; 644 645//===----------------------------------------------------------------------===// 646// Non-Instruction Patterns 647//===----------------------------------------------------------------------===// 648 649// Small immediates. 650def : Pat<(i32 simm13:$val), 651 (ORri G0, imm:$val)>; 652// Arbitrary immediates. 653def : Pat<(i32 imm:$val), 654 (ORri (SETHIi (HI22 imm:$val)), (LO10 imm:$val))>; 655