SparcInstrInfo.td revision 466685d41a9ea4905b9486fea38e83802e46f196
1//===- SparcInstrInfo.td - Target Description for Sparc Target ------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the Sparc instructions in TableGen format. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// Instruction format superclass 16//===----------------------------------------------------------------------===// 17 18include "SparcInstrFormats.td" 19 20//===----------------------------------------------------------------------===// 21// Feature predicates. 22//===----------------------------------------------------------------------===// 23 24// HasV9 - This predicate is true when the target processor supports V9 25// instructions. Note that the machine may be running in 32-bit mode. 26def HasV9 : Predicate<"Subtarget.isV9()">; 27 28// HasNoV9 - This predicate is true when the target doesn't have V9 29// instructions. Use of this is just a hack for the isel not having proper 30// costs for V8 instructions that are more expensive than their V9 ones. 31def HasNoV9 : Predicate<"!Subtarget.isV9()">; 32 33// HasVIS - This is true when the target processor has VIS extensions. 34def HasVIS : Predicate<"Subtarget.isVIS()">; 35 36// UseDeprecatedInsts - This predicate is true when the target processor is a 37// V8, or when it is V9 but the V8 deprecated instructions are efficient enough 38// to use when appropriate. In either of these cases, the instruction selector 39// will pick deprecated instructions. 40def UseDeprecatedInsts : Predicate<"Subtarget.useDeprecatedV8Instructions()">; 41 42//===----------------------------------------------------------------------===// 43// Instruction Pattern Stuff 44//===----------------------------------------------------------------------===// 45 46def simm11 : PatLeaf<(imm), [{ 47 // simm11 predicate - True if the imm fits in a 11-bit sign extended field. 48 return (((int)N->getValue() << (32-11)) >> (32-11)) == (int)N->getValue(); 49}]>; 50 51def simm13 : PatLeaf<(imm), [{ 52 // simm13 predicate - True if the imm fits in a 13-bit sign extended field. 53 return (((int)N->getValue() << (32-13)) >> (32-13)) == (int)N->getValue(); 54}]>; 55 56def LO10 : SDNodeXForm<imm, [{ 57 return CurDAG->getTargetConstant((unsigned)N->getValue() & 1023, MVT::i32); 58}]>; 59 60def HI22 : SDNodeXForm<imm, [{ 61 // Transformation function: shift the immediate value down into the low bits. 62 return CurDAG->getTargetConstant((unsigned)N->getValue() >> 10, MVT::i32); 63}]>; 64 65def SETHIimm : PatLeaf<(imm), [{ 66 return (((unsigned)N->getValue() >> 10) << 10) == (unsigned)N->getValue(); 67}], HI22>; 68 69// Addressing modes. 70def ADDRrr : ComplexPattern<i32, 2, "SelectADDRrr", []>; 71def ADDRri : ComplexPattern<i32, 2, "SelectADDRri", [frameindex]>; 72 73// Address operands 74def MEMrr : Operand<i32> { 75 let PrintMethod = "printMemOperand"; 76 let NumMIOperands = 2; 77 let MIOperandInfo = (ops IntRegs, IntRegs); 78} 79def MEMri : Operand<i32> { 80 let PrintMethod = "printMemOperand"; 81 let NumMIOperands = 2; 82 let MIOperandInfo = (ops IntRegs, i32imm); 83} 84 85// Branch targets have OtherVT type. 86def brtarget : Operand<OtherVT>; 87def calltarget : Operand<i32>; 88 89// Operand for printing out a condition code. 90let PrintMethod = "printCCOperand" in 91 def CCOp : Operand<i32>; 92 93def SDTSPcmpfcc : 94SDTypeProfile<0, 2, [SDTCisFP<0>, SDTCisSameAs<0, 1>]>; 95def SDTSPbrcc : 96SDTypeProfile<0, 2, [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>; 97def SDTSPselectcc : 98SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>]>; 99def SDTSPFTOI : 100SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisFP<1>]>; 101def SDTSPITOF : 102SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f32>]>; 103 104def SPcmpicc : SDNode<"SPISD::CMPICC", SDTIntBinOp, [SDNPOutFlag]>; 105def SPcmpfcc : SDNode<"SPISD::CMPFCC", SDTSPcmpfcc, [SDNPOutFlag]>; 106def SPbricc : SDNode<"SPISD::BRICC", SDTSPbrcc, [SDNPHasChain, SDNPInFlag]>; 107def SPbrfcc : SDNode<"SPISD::BRFCC", SDTSPbrcc, [SDNPHasChain, SDNPInFlag]>; 108 109def SPhi : SDNode<"SPISD::Hi", SDTIntUnaryOp>; 110def SPlo : SDNode<"SPISD::Lo", SDTIntUnaryOp>; 111 112def SPftoi : SDNode<"SPISD::FTOI", SDTSPFTOI>; 113def SPitof : SDNode<"SPISD::ITOF", SDTSPITOF>; 114 115def SPselecticc : SDNode<"SPISD::SELECT_ICC", SDTSPselectcc, [SDNPInFlag]>; 116def SPselectfcc : SDNode<"SPISD::SELECT_FCC", SDTSPselectcc, [SDNPInFlag]>; 117 118// These are target-independent nodes, but have target-specific formats. 119def SDT_SPCallSeq : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>; 120def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_SPCallSeq, 121 [SDNPHasChain, SDNPOutFlag]>; 122def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_SPCallSeq, 123 [SDNPHasChain, SDNPOutFlag]>; 124 125def SDT_SPCall : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>; 126def call : SDNode<"SPISD::CALL", SDT_SPCall, 127 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; 128 129def SDT_SPRetFlag : SDTypeProfile<0, 0, []>; 130def retflag : SDNode<"SPISD::RET_FLAG", SDT_SPRetFlag, 131 [SDNPHasChain, SDNPOptInFlag]>; 132 133//===----------------------------------------------------------------------===// 134// SPARC Flag Conditions 135//===----------------------------------------------------------------------===// 136 137// Note that these values must be kept in sync with the CCOp::CondCode enum 138// values. 139class ICC_VAL<int N> : PatLeaf<(i32 N)>; 140def ICC_NE : ICC_VAL< 9>; // Not Equal 141def ICC_E : ICC_VAL< 1>; // Equal 142def ICC_G : ICC_VAL<10>; // Greater 143def ICC_LE : ICC_VAL< 2>; // Less or Equal 144def ICC_GE : ICC_VAL<11>; // Greater or Equal 145def ICC_L : ICC_VAL< 3>; // Less 146def ICC_GU : ICC_VAL<12>; // Greater Unsigned 147def ICC_LEU : ICC_VAL< 4>; // Less or Equal Unsigned 148def ICC_CC : ICC_VAL<13>; // Carry Clear/Great or Equal Unsigned 149def ICC_CS : ICC_VAL< 5>; // Carry Set/Less Unsigned 150def ICC_POS : ICC_VAL<14>; // Positive 151def ICC_NEG : ICC_VAL< 6>; // Negative 152def ICC_VC : ICC_VAL<15>; // Overflow Clear 153def ICC_VS : ICC_VAL< 7>; // Overflow Set 154 155class FCC_VAL<int N> : PatLeaf<(i32 N)>; 156def FCC_U : FCC_VAL<23>; // Unordered 157def FCC_G : FCC_VAL<22>; // Greater 158def FCC_UG : FCC_VAL<21>; // Unordered or Greater 159def FCC_L : FCC_VAL<20>; // Less 160def FCC_UL : FCC_VAL<19>; // Unordered or Less 161def FCC_LG : FCC_VAL<18>; // Less or Greater 162def FCC_NE : FCC_VAL<17>; // Not Equal 163def FCC_E : FCC_VAL<25>; // Equal 164def FCC_UE : FCC_VAL<24>; // Unordered or Equal 165def FCC_GE : FCC_VAL<25>; // Greater or Equal 166def FCC_UGE : FCC_VAL<26>; // Unordered or Greater or Equal 167def FCC_LE : FCC_VAL<27>; // Less or Equal 168def FCC_ULE : FCC_VAL<28>; // Unordered or Less or Equal 169def FCC_O : FCC_VAL<29>; // Ordered 170 171//===----------------------------------------------------------------------===// 172// Instruction Class Templates 173//===----------------------------------------------------------------------===// 174 175/// F3_12 multiclass - Define a normal F3_1/F3_2 pattern in one shot. 176multiclass F3_12<string OpcStr, bits<6> Op3Val, SDNode OpNode> { 177 def rr : F3_1<2, Op3Val, 178 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 179 !strconcat(OpcStr, " $b, $c, $dst"), 180 [(set IntRegs:$dst, (OpNode IntRegs:$b, IntRegs:$c))]>; 181 def ri : F3_2<2, Op3Val, 182 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 183 !strconcat(OpcStr, " $b, $c, $dst"), 184 [(set IntRegs:$dst, (OpNode IntRegs:$b, simm13:$c))]>; 185} 186 187/// F3_12np multiclass - Define a normal F3_1/F3_2 pattern in one shot, with no 188/// pattern. 189multiclass F3_12np<string OpcStr, bits<6> Op3Val> { 190 def rr : F3_1<2, Op3Val, 191 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 192 !strconcat(OpcStr, " $b, $c, $dst"), []>; 193 def ri : F3_2<2, Op3Val, 194 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 195 !strconcat(OpcStr, " $b, $c, $dst"), []>; 196} 197 198//===----------------------------------------------------------------------===// 199// Instructions 200//===----------------------------------------------------------------------===// 201 202// Pseudo instructions. 203class Pseudo<dag ops, string asmstr, list<dag> pattern> 204 : InstSP<ops, asmstr, pattern>; 205 206def ADJCALLSTACKDOWN : Pseudo<(ops i32imm:$amt), 207 "!ADJCALLSTACKDOWN $amt", 208 [(callseq_start imm:$amt)]>; 209def ADJCALLSTACKUP : Pseudo<(ops i32imm:$amt), 210 "!ADJCALLSTACKUP $amt", 211 [(callseq_end imm:$amt)]>; 212def IMPLICIT_DEF_Int : Pseudo<(ops IntRegs:$dst), 213 "!IMPLICIT_DEF $dst", 214 [(set IntRegs:$dst, (undef))]>; 215def IMPLICIT_DEF_FP : Pseudo<(ops FPRegs:$dst), "!IMPLICIT_DEF $dst", 216 [(set FPRegs:$dst, (undef))]>; 217def IMPLICIT_DEF_DFP : Pseudo<(ops DFPRegs:$dst), "!IMPLICIT_DEF $dst", 218 [(set DFPRegs:$dst, (undef))]>; 219 220// FpMOVD/FpNEGD/FpABSD - These are lowered to single-precision ops by the 221// fpmover pass. 222let Predicates = [HasNoV9] in { // Only emit these in V8 mode. 223 def FpMOVD : Pseudo<(ops DFPRegs:$dst, DFPRegs:$src), 224 "!FpMOVD $src, $dst", []>; 225 def FpNEGD : Pseudo<(ops DFPRegs:$dst, DFPRegs:$src), 226 "!FpNEGD $src, $dst", 227 [(set DFPRegs:$dst, (fneg DFPRegs:$src))]>; 228 def FpABSD : Pseudo<(ops DFPRegs:$dst, DFPRegs:$src), 229 "!FpABSD $src, $dst", 230 [(set DFPRegs:$dst, (fabs DFPRegs:$src))]>; 231} 232 233// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded by the 234// scheduler into a branch sequence. This has to handle all permutations of 235// selection between i32/f32/f64 on ICC and FCC. 236let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler. 237 def SELECT_CC_Int_ICC 238 : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F, i32imm:$Cond), 239 "; SELECT_CC_Int_ICC PSEUDO!", 240 [(set IntRegs:$dst, (SPselecticc IntRegs:$T, IntRegs:$F, 241 imm:$Cond))]>; 242 def SELECT_CC_Int_FCC 243 : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F, i32imm:$Cond), 244 "; SELECT_CC_Int_FCC PSEUDO!", 245 [(set IntRegs:$dst, (SPselectfcc IntRegs:$T, IntRegs:$F, 246 imm:$Cond))]>; 247 def SELECT_CC_FP_ICC 248 : Pseudo<(ops FPRegs:$dst, FPRegs:$T, FPRegs:$F, i32imm:$Cond), 249 "; SELECT_CC_FP_ICC PSEUDO!", 250 [(set FPRegs:$dst, (SPselecticc FPRegs:$T, FPRegs:$F, 251 imm:$Cond))]>; 252 def SELECT_CC_FP_FCC 253 : Pseudo<(ops FPRegs:$dst, FPRegs:$T, FPRegs:$F, i32imm:$Cond), 254 "; SELECT_CC_FP_FCC PSEUDO!", 255 [(set FPRegs:$dst, (SPselectfcc FPRegs:$T, FPRegs:$F, 256 imm:$Cond))]>; 257 def SELECT_CC_DFP_ICC 258 : Pseudo<(ops DFPRegs:$dst, DFPRegs:$T, DFPRegs:$F, i32imm:$Cond), 259 "; SELECT_CC_DFP_ICC PSEUDO!", 260 [(set DFPRegs:$dst, (SPselecticc DFPRegs:$T, DFPRegs:$F, 261 imm:$Cond))]>; 262 def SELECT_CC_DFP_FCC 263 : Pseudo<(ops DFPRegs:$dst, DFPRegs:$T, DFPRegs:$F, i32imm:$Cond), 264 "; SELECT_CC_DFP_FCC PSEUDO!", 265 [(set DFPRegs:$dst, (SPselectfcc DFPRegs:$T, DFPRegs:$F, 266 imm:$Cond))]>; 267} 268 269 270// Section A.3 - Synthetic Instructions, p. 85 271// special cases of JMPL: 272let isReturn = 1, isTerminator = 1, hasDelaySlot = 1, noResults = 1 in { 273 let rd = O7.Num, rs1 = G0.Num, simm13 = 8 in 274 def RETL: F3_2<2, 0b111000, (ops), "retl", [(retflag)]>; 275} 276 277// Section B.1 - Load Integer Instructions, p. 90 278def LDSBrr : F3_1<3, 0b001001, 279 (ops IntRegs:$dst, MEMrr:$addr), 280 "ldsb [$addr], $dst", 281 [(set IntRegs:$dst, (sextloadi8 ADDRrr:$addr))]>; 282def LDSBri : F3_2<3, 0b001001, 283 (ops IntRegs:$dst, MEMri:$addr), 284 "ldsb [$addr], $dst", 285 [(set IntRegs:$dst, (sextloadi8 ADDRri:$addr))]>; 286def LDSHrr : F3_1<3, 0b001010, 287 (ops IntRegs:$dst, MEMrr:$addr), 288 "ldsh [$addr], $dst", 289 [(set IntRegs:$dst, (sextloadi16 ADDRrr:$addr))]>; 290def LDSHri : F3_2<3, 0b001010, 291 (ops IntRegs:$dst, MEMri:$addr), 292 "ldsh [$addr], $dst", 293 [(set IntRegs:$dst, (sextloadi16 ADDRri:$addr))]>; 294def LDUBrr : F3_1<3, 0b000001, 295 (ops IntRegs:$dst, MEMrr:$addr), 296 "ldub [$addr], $dst", 297 [(set IntRegs:$dst, (zextloadi8 ADDRrr:$addr))]>; 298def LDUBri : F3_2<3, 0b000001, 299 (ops IntRegs:$dst, MEMri:$addr), 300 "ldub [$addr], $dst", 301 [(set IntRegs:$dst, (zextloadi8 ADDRri:$addr))]>; 302def LDUHrr : F3_1<3, 0b000010, 303 (ops IntRegs:$dst, MEMrr:$addr), 304 "lduh [$addr], $dst", 305 [(set IntRegs:$dst, (zextloadi16 ADDRrr:$addr))]>; 306def LDUHri : F3_2<3, 0b000010, 307 (ops IntRegs:$dst, MEMri:$addr), 308 "lduh [$addr], $dst", 309 [(set IntRegs:$dst, (zextloadi16 ADDRri:$addr))]>; 310def LDrr : F3_1<3, 0b000000, 311 (ops IntRegs:$dst, MEMrr:$addr), 312 "ld [$addr], $dst", 313 [(set IntRegs:$dst, (load ADDRrr:$addr))]>; 314def LDri : F3_2<3, 0b000000, 315 (ops IntRegs:$dst, MEMri:$addr), 316 "ld [$addr], $dst", 317 [(set IntRegs:$dst, (load ADDRri:$addr))]>; 318 319// Section B.2 - Load Floating-point Instructions, p. 92 320def LDFrr : F3_1<3, 0b100000, 321 (ops FPRegs:$dst, MEMrr:$addr), 322 "ld [$addr], $dst", 323 [(set FPRegs:$dst, (load ADDRrr:$addr))]>; 324def LDFri : F3_2<3, 0b100000, 325 (ops FPRegs:$dst, MEMri:$addr), 326 "ld [$addr], $dst", 327 [(set FPRegs:$dst, (load ADDRri:$addr))]>; 328def LDDFrr : F3_1<3, 0b100011, 329 (ops DFPRegs:$dst, MEMrr:$addr), 330 "ldd [$addr], $dst", 331 [(set DFPRegs:$dst, (load ADDRrr:$addr))]>; 332def LDDFri : F3_2<3, 0b100011, 333 (ops DFPRegs:$dst, MEMri:$addr), 334 "ldd [$addr], $dst", 335 [(set DFPRegs:$dst, (load ADDRri:$addr))]>; 336 337// Section B.4 - Store Integer Instructions, p. 95 338def STBrr : F3_1<3, 0b000101, 339 (ops MEMrr:$addr, IntRegs:$src), 340 "stb $src, [$addr]", 341 [(truncstore IntRegs:$src, ADDRrr:$addr, i8)]>; 342def STBri : F3_2<3, 0b000101, 343 (ops MEMri:$addr, IntRegs:$src), 344 "stb $src, [$addr]", 345 [(truncstore IntRegs:$src, ADDRri:$addr, i8)]>; 346def STHrr : F3_1<3, 0b000110, 347 (ops MEMrr:$addr, IntRegs:$src), 348 "sth $src, [$addr]", 349 [(truncstore IntRegs:$src, ADDRrr:$addr, i16)]>; 350def STHri : F3_2<3, 0b000110, 351 (ops MEMri:$addr, IntRegs:$src), 352 "sth $src, [$addr]", 353 [(truncstore IntRegs:$src, ADDRri:$addr, i16)]>; 354def STrr : F3_1<3, 0b000100, 355 (ops MEMrr:$addr, IntRegs:$src), 356 "st $src, [$addr]", 357 [(store IntRegs:$src, ADDRrr:$addr)]>; 358def STri : F3_2<3, 0b000100, 359 (ops MEMri:$addr, IntRegs:$src), 360 "st $src, [$addr]", 361 [(store IntRegs:$src, ADDRri:$addr)]>; 362 363// Section B.5 - Store Floating-point Instructions, p. 97 364def STFrr : F3_1<3, 0b100100, 365 (ops MEMrr:$addr, FPRegs:$src), 366 "st $src, [$addr]", 367 [(store FPRegs:$src, ADDRrr:$addr)]>; 368def STFri : F3_2<3, 0b100100, 369 (ops MEMri:$addr, FPRegs:$src), 370 "st $src, [$addr]", 371 [(store FPRegs:$src, ADDRri:$addr)]>; 372def STDFrr : F3_1<3, 0b100111, 373 (ops MEMrr:$addr, DFPRegs:$src), 374 "std $src, [$addr]", 375 [(store DFPRegs:$src, ADDRrr:$addr)]>; 376def STDFri : F3_2<3, 0b100111, 377 (ops MEMri:$addr, DFPRegs:$src), 378 "std $src, [$addr]", 379 [(store DFPRegs:$src, ADDRri:$addr)]>; 380 381// Section B.9 - SETHI Instruction, p. 104 382def SETHIi: F2_1<0b100, 383 (ops IntRegs:$dst, i32imm:$src), 384 "sethi $src, $dst", 385 [(set IntRegs:$dst, SETHIimm:$src)]>; 386 387// Section B.10 - NOP Instruction, p. 105 388// (It's a special case of SETHI) 389let rd = 0, imm22 = 0 in 390 def NOP : F2_1<0b100, (ops), "nop", []>; 391 392// Section B.11 - Logical Instructions, p. 106 393defm AND : F3_12<"and", 0b000001, and>; 394 395def ANDNrr : F3_1<2, 0b000101, 396 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 397 "andn $b, $c, $dst", 398 [(set IntRegs:$dst, (and IntRegs:$b, (not IntRegs:$c)))]>; 399def ANDNri : F3_2<2, 0b000101, 400 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 401 "andn $b, $c, $dst", []>; 402 403defm OR : F3_12<"or", 0b000010, or>; 404 405def ORNrr : F3_1<2, 0b000110, 406 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 407 "orn $b, $c, $dst", 408 [(set IntRegs:$dst, (or IntRegs:$b, (not IntRegs:$c)))]>; 409def ORNri : F3_2<2, 0b000110, 410 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 411 "orn $b, $c, $dst", []>; 412defm XOR : F3_12<"xor", 0b000011, xor>; 413 414def XNORrr : F3_1<2, 0b000111, 415 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 416 "xnor $b, $c, $dst", 417 [(set IntRegs:$dst, (not (xor IntRegs:$b, IntRegs:$c)))]>; 418def XNORri : F3_2<2, 0b000111, 419 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 420 "xnor $b, $c, $dst", []>; 421 422// Section B.12 - Shift Instructions, p. 107 423defm SLL : F3_12<"sll", 0b100101, shl>; 424defm SRL : F3_12<"srl", 0b100110, srl>; 425defm SRA : F3_12<"sra", 0b100111, sra>; 426 427// Section B.13 - Add Instructions, p. 108 428defm ADD : F3_12<"add", 0b000000, add>; 429 430// "LEA" forms of add (patterns to make tblgen happy) 431def LEA_ADDri : F3_2<2, 0b000000, 432 (ops IntRegs:$dst, MEMri:$addr), 433 "add ${addr:arith}, $dst", 434 [(set IntRegs:$dst, ADDRri:$addr)]>; 435 436defm ADDCC : F3_12<"addcc", 0b010000, addc>; 437defm ADDX : F3_12<"addx", 0b001000, adde>; 438 439// Section B.15 - Subtract Instructions, p. 110 440defm SUB : F3_12 <"sub" , 0b000100, sub>; 441defm SUBX : F3_12 <"subx" , 0b001100, sube>; 442defm SUBCC : F3_12 <"subcc", 0b010100, SPcmpicc>; 443 444def SUBXCCrr: F3_1<2, 0b011100, 445 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 446 "subxcc $b, $c, $dst", []>; 447 448// Section B.18 - Multiply Instructions, p. 113 449defm UMUL : F3_12np<"umul", 0b001010>; 450defm SMUL : F3_12 <"smul", 0b001011, mul>; 451 452 453// Section B.19 - Divide Instructions, p. 115 454defm UDIV : F3_12np<"udiv", 0b001110>; 455defm SDIV : F3_12np<"sdiv", 0b001111>; 456 457// Section B.20 - SAVE and RESTORE, p. 117 458defm SAVE : F3_12np<"save" , 0b111100>; 459defm RESTORE : F3_12np<"restore", 0b111101>; 460 461// Section B.21 - Branch on Integer Condition Codes Instructions, p. 119 462 463// conditional branch class: 464class BranchSP<bits<4> cc, dag ops, string asmstr, list<dag> pattern> 465 : F2_2<cc, 0b010, ops, asmstr, pattern> { 466 let isBranch = 1; 467 let isTerminator = 1; 468 let hasDelaySlot = 1; 469 let noResults = 1; 470} 471 472let isBarrier = 1 in 473 def BA : BranchSP<0b1000, (ops brtarget:$dst), 474 "ba $dst", 475 [(br bb:$dst)]>; 476 477// FIXME: the encoding for the JIT should look at the condition field. 478def BCOND : BranchSP<0, (ops brtarget:$dst, CCOp:$cc), 479 "b$cc $dst", 480 [(SPbricc bb:$dst, imm:$cc)]>; 481 482 483// Section B.22 - Branch on Floating-point Condition Codes Instructions, p. 121 484 485// floating-point conditional branch class: 486class FPBranchSP<bits<4> cc, dag ops, string asmstr, list<dag> pattern> 487 : F2_2<cc, 0b110, ops, asmstr, pattern> { 488 let isBranch = 1; 489 let isTerminator = 1; 490 let hasDelaySlot = 1; 491 let noResults = 1; 492} 493 494// FIXME: the encoding for the JIT should look at the condition field. 495def FBCOND : FPBranchSP<0, (ops brtarget:$dst, CCOp:$cc), 496 "fb$cc $dst", 497 [(SPbrfcc bb:$dst, imm:$cc)]>; 498 499 500// Section B.24 - Call and Link Instruction, p. 125 501// This is the only Format 1 instruction 502let Uses = [O0, O1, O2, O3, O4, O5], 503 hasDelaySlot = 1, isCall = 1, noResults = 1, 504 Defs = [O0, O1, O2, O3, O4, O5, O7, G1, G2, G3, G4, G5, G6, G7, 505 D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15] in { 506 def CALL : InstSP<(ops calltarget:$dst), 507 "call $dst", []> { 508 bits<30> disp; 509 let op = 1; 510 let Inst{29-0} = disp; 511 } 512 513 // indirect calls 514 def JMPLrr : F3_1<2, 0b111000, 515 (ops MEMrr:$ptr), 516 "call $ptr", 517 [(call ADDRrr:$ptr)]>; 518 def JMPLri : F3_2<2, 0b111000, 519 (ops MEMri:$ptr), 520 "call $ptr", 521 [(call ADDRri:$ptr)]>; 522} 523 524// Section B.28 - Read State Register Instructions 525def RDY : F3_1<2, 0b101000, 526 (ops IntRegs:$dst), 527 "rd %y, $dst", []>; 528 529// Section B.29 - Write State Register Instructions 530def WRYrr : F3_1<2, 0b110000, 531 (ops IntRegs:$b, IntRegs:$c), 532 "wr $b, $c, %y", []>; 533def WRYri : F3_2<2, 0b110000, 534 (ops IntRegs:$b, i32imm:$c), 535 "wr $b, $c, %y", []>; 536 537// Convert Integer to Floating-point Instructions, p. 141 538def FITOS : F3_3<2, 0b110100, 0b011000100, 539 (ops FPRegs:$dst, FPRegs:$src), 540 "fitos $src, $dst", 541 [(set FPRegs:$dst, (SPitof FPRegs:$src))]>; 542def FITOD : F3_3<2, 0b110100, 0b011001000, 543 (ops DFPRegs:$dst, FPRegs:$src), 544 "fitod $src, $dst", 545 [(set DFPRegs:$dst, (SPitof FPRegs:$src))]>; 546 547// Convert Floating-point to Integer Instructions, p. 142 548def FSTOI : F3_3<2, 0b110100, 0b011010001, 549 (ops FPRegs:$dst, FPRegs:$src), 550 "fstoi $src, $dst", 551 [(set FPRegs:$dst, (SPftoi FPRegs:$src))]>; 552def FDTOI : F3_3<2, 0b110100, 0b011010010, 553 (ops FPRegs:$dst, DFPRegs:$src), 554 "fdtoi $src, $dst", 555 [(set FPRegs:$dst, (SPftoi DFPRegs:$src))]>; 556 557// Convert between Floating-point Formats Instructions, p. 143 558def FSTOD : F3_3<2, 0b110100, 0b011001001, 559 (ops DFPRegs:$dst, FPRegs:$src), 560 "fstod $src, $dst", 561 [(set DFPRegs:$dst, (fextend FPRegs:$src))]>; 562def FDTOS : F3_3<2, 0b110100, 0b011000110, 563 (ops FPRegs:$dst, DFPRegs:$src), 564 "fdtos $src, $dst", 565 [(set FPRegs:$dst, (fround DFPRegs:$src))]>; 566 567// Floating-point Move Instructions, p. 144 568def FMOVS : F3_3<2, 0b110100, 0b000000001, 569 (ops FPRegs:$dst, FPRegs:$src), 570 "fmovs $src, $dst", []>; 571def FNEGS : F3_3<2, 0b110100, 0b000000101, 572 (ops FPRegs:$dst, FPRegs:$src), 573 "fnegs $src, $dst", 574 [(set FPRegs:$dst, (fneg FPRegs:$src))]>; 575def FABSS : F3_3<2, 0b110100, 0b000001001, 576 (ops FPRegs:$dst, FPRegs:$src), 577 "fabss $src, $dst", 578 [(set FPRegs:$dst, (fabs FPRegs:$src))]>; 579 580 581// Floating-point Square Root Instructions, p.145 582def FSQRTS : F3_3<2, 0b110100, 0b000101001, 583 (ops FPRegs:$dst, FPRegs:$src), 584 "fsqrts $src, $dst", 585 [(set FPRegs:$dst, (fsqrt FPRegs:$src))]>; 586def FSQRTD : F3_3<2, 0b110100, 0b000101010, 587 (ops DFPRegs:$dst, DFPRegs:$src), 588 "fsqrtd $src, $dst", 589 [(set DFPRegs:$dst, (fsqrt DFPRegs:$src))]>; 590 591 592 593// Floating-point Add and Subtract Instructions, p. 146 594def FADDS : F3_3<2, 0b110100, 0b001000001, 595 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2), 596 "fadds $src1, $src2, $dst", 597 [(set FPRegs:$dst, (fadd FPRegs:$src1, FPRegs:$src2))]>; 598def FADDD : F3_3<2, 0b110100, 0b001000010, 599 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2), 600 "faddd $src1, $src2, $dst", 601 [(set DFPRegs:$dst, (fadd DFPRegs:$src1, DFPRegs:$src2))]>; 602def FSUBS : F3_3<2, 0b110100, 0b001000101, 603 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2), 604 "fsubs $src1, $src2, $dst", 605 [(set FPRegs:$dst, (fsub FPRegs:$src1, FPRegs:$src2))]>; 606def FSUBD : F3_3<2, 0b110100, 0b001000110, 607 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2), 608 "fsubd $src1, $src2, $dst", 609 [(set DFPRegs:$dst, (fsub DFPRegs:$src1, DFPRegs:$src2))]>; 610 611// Floating-point Multiply and Divide Instructions, p. 147 612def FMULS : F3_3<2, 0b110100, 0b001001001, 613 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2), 614 "fmuls $src1, $src2, $dst", 615 [(set FPRegs:$dst, (fmul FPRegs:$src1, FPRegs:$src2))]>; 616def FMULD : F3_3<2, 0b110100, 0b001001010, 617 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2), 618 "fmuld $src1, $src2, $dst", 619 [(set DFPRegs:$dst, (fmul DFPRegs:$src1, DFPRegs:$src2))]>; 620def FSMULD : F3_3<2, 0b110100, 0b001101001, 621 (ops DFPRegs:$dst, FPRegs:$src1, FPRegs:$src2), 622 "fsmuld $src1, $src2, $dst", 623 [(set DFPRegs:$dst, (fmul (fextend FPRegs:$src1), 624 (fextend FPRegs:$src2)))]>; 625def FDIVS : F3_3<2, 0b110100, 0b001001101, 626 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2), 627 "fdivs $src1, $src2, $dst", 628 [(set FPRegs:$dst, (fdiv FPRegs:$src1, FPRegs:$src2))]>; 629def FDIVD : F3_3<2, 0b110100, 0b001001110, 630 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2), 631 "fdivd $src1, $src2, $dst", 632 [(set DFPRegs:$dst, (fdiv DFPRegs:$src1, DFPRegs:$src2))]>; 633 634// Floating-point Compare Instructions, p. 148 635// Note: the 2nd template arg is different for these guys. 636// Note 2: the result of a FCMP is not available until the 2nd cycle 637// after the instr is retired, but there is no interlock. This behavior 638// is modelled with a forced noop after the instruction. 639def FCMPS : F3_3<2, 0b110101, 0b001010001, 640 (ops FPRegs:$src1, FPRegs:$src2), 641 "fcmps $src1, $src2\n\tnop", 642 [(SPcmpfcc FPRegs:$src1, FPRegs:$src2)]>; 643def FCMPD : F3_3<2, 0b110101, 0b001010010, 644 (ops DFPRegs:$src1, DFPRegs:$src2), 645 "fcmpd $src1, $src2\n\tnop", 646 [(SPcmpfcc DFPRegs:$src1, DFPRegs:$src2)]>; 647 648 649//===----------------------------------------------------------------------===// 650// V9 Instructions 651//===----------------------------------------------------------------------===// 652 653// V9 Conditional Moves. 654let Predicates = [HasV9], isTwoAddress = 1 in { 655 // Move Integer Register on Condition (MOVcc) p. 194 of the V9 manual. 656 // FIXME: Add instruction encodings for the JIT some day. 657 def MOVICCrr 658 : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F, CCOp:$cc), 659 "mov$cc %icc, $F, $dst", 660 [(set IntRegs:$dst, 661 (SPselecticc IntRegs:$F, IntRegs:$T, imm:$cc))]>; 662 def MOVICCri 663 : Pseudo<(ops IntRegs:$dst, IntRegs:$T, i32imm:$F, CCOp:$cc), 664 "mov$cc %icc, $F, $dst", 665 [(set IntRegs:$dst, 666 (SPselecticc simm11:$F, IntRegs:$T, imm:$cc))]>; 667 668 def MOVFCCrr 669 : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F, CCOp:$cc), 670 "mov$cc %fcc0, $F, $dst", 671 [(set IntRegs:$dst, 672 (SPselectfcc IntRegs:$F, IntRegs:$T, imm:$cc))]>; 673 def MOVFCCri 674 : Pseudo<(ops IntRegs:$dst, IntRegs:$T, i32imm:$F, CCOp:$cc), 675 "mov$cc %fcc0, $F, $dst", 676 [(set IntRegs:$dst, 677 (SPselectfcc simm11:$F, IntRegs:$T, imm:$cc))]>; 678 679 def FMOVS_ICC 680 : Pseudo<(ops FPRegs:$dst, FPRegs:$T, FPRegs:$F, CCOp:$cc), 681 "fmovs$cc %icc, $F, $dst", 682 [(set FPRegs:$dst, 683 (SPselecticc FPRegs:$F, FPRegs:$T, imm:$cc))]>; 684 def FMOVD_ICC 685 : Pseudo<(ops DFPRegs:$dst, DFPRegs:$T, DFPRegs:$F, CCOp:$cc), 686 "fmovd$cc %icc, $F, $dst", 687 [(set DFPRegs:$dst, 688 (SPselecticc DFPRegs:$F, DFPRegs:$T, imm:$cc))]>; 689 def FMOVS_FCC 690 : Pseudo<(ops FPRegs:$dst, FPRegs:$T, FPRegs:$F, CCOp:$cc), 691 "fmovs$cc %fcc0, $F, $dst", 692 [(set FPRegs:$dst, 693 (SPselectfcc FPRegs:$F, FPRegs:$T, imm:$cc))]>; 694 def FMOVD_FCC 695 : Pseudo<(ops DFPRegs:$dst, DFPRegs:$T, DFPRegs:$F, CCOp:$cc), 696 "fmovd$cc %fcc0, $F, $dst", 697 [(set DFPRegs:$dst, 698 (SPselectfcc DFPRegs:$F, DFPRegs:$T, imm:$cc))]>; 699 700} 701 702// Floating-Point Move Instructions, p. 164 of the V9 manual. 703let Predicates = [HasV9] in { 704 def FMOVD : F3_3<2, 0b110100, 0b000000010, 705 (ops DFPRegs:$dst, DFPRegs:$src), 706 "fmovd $src, $dst", []>; 707 def FNEGD : F3_3<2, 0b110100, 0b000000110, 708 (ops DFPRegs:$dst, DFPRegs:$src), 709 "fnegd $src, $dst", 710 [(set DFPRegs:$dst, (fneg DFPRegs:$src))]>; 711 def FABSD : F3_3<2, 0b110100, 0b000001010, 712 (ops DFPRegs:$dst, DFPRegs:$src), 713 "fabsd $src, $dst", 714 [(set DFPRegs:$dst, (fabs DFPRegs:$src))]>; 715} 716 717// POPCrr - This does a ctpop of a 64-bit register. As such, we have to clear 718// the top 32-bits before using it. To do this clearing, we use a SLLri X,0. 719def POPCrr : F3_1<2, 0b101110, 720 (ops IntRegs:$dst, IntRegs:$src), 721 "popc $src, $dst", []>, Requires<[HasV9]>; 722def : Pat<(ctpop IntRegs:$src), 723 (POPCrr (SLLri IntRegs:$src, 0))>; 724 725//===----------------------------------------------------------------------===// 726// Non-Instruction Patterns 727//===----------------------------------------------------------------------===// 728 729// Small immediates. 730def : Pat<(i32 simm13:$val), 731 (ORri G0, imm:$val)>; 732// Arbitrary immediates. 733def : Pat<(i32 imm:$val), 734 (ORri (SETHIi (HI22 imm:$val)), (LO10 imm:$val))>; 735 736// subc 737def : Pat<(subc IntRegs:$b, IntRegs:$c), 738 (SUBCCrr IntRegs:$b, IntRegs:$c)>; 739def : Pat<(subc IntRegs:$b, simm13:$val), 740 (SUBCCri IntRegs:$b, imm:$val)>; 741 742// Global addresses, constant pool entries 743def : Pat<(SPhi tglobaladdr:$in), (SETHIi tglobaladdr:$in)>; 744def : Pat<(SPlo tglobaladdr:$in), (ORri G0, tglobaladdr:$in)>; 745def : Pat<(SPhi tconstpool:$in), (SETHIi tconstpool:$in)>; 746def : Pat<(SPlo tconstpool:$in), (ORri G0, tconstpool:$in)>; 747 748// Add reg, lo. This is used when taking the addr of a global/constpool entry. 749def : Pat<(add IntRegs:$r, (SPlo tglobaladdr:$in)), 750 (ADDri IntRegs:$r, tglobaladdr:$in)>; 751def : Pat<(add IntRegs:$r, (SPlo tconstpool:$in)), 752 (ADDri IntRegs:$r, tconstpool:$in)>; 753 754// Calls: 755def : Pat<(call tglobaladdr:$dst), 756 (CALL tglobaladdr:$dst)>; 757def : Pat<(call texternalsym:$dst), 758 (CALL texternalsym:$dst)>; 759 760def : Pat<(ret), (RETL)>; 761 762// Map integer extload's to zextloads. 763def : Pat<(i32 (extloadi1 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>; 764def : Pat<(i32 (extloadi1 ADDRri:$src)), (LDUBri ADDRri:$src)>; 765def : Pat<(i32 (extloadi8 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>; 766def : Pat<(i32 (extloadi8 ADDRri:$src)), (LDUBri ADDRri:$src)>; 767def : Pat<(i32 (extloadi16 ADDRrr:$src)), (LDUHrr ADDRrr:$src)>; 768def : Pat<(i32 (extloadi16 ADDRri:$src)), (LDUHri ADDRri:$src)>; 769 770// zextload bool -> zextload byte 771def : Pat<(i32 (zextloadi1 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>; 772def : Pat<(i32 (zextloadi1 ADDRri:$src)), (LDUBri ADDRri:$src)>; 773 774// truncstore bool -> truncstore byte. 775def : Pat<(truncstore IntRegs:$src, ADDRrr:$addr, i1), 776 (STBrr ADDRrr:$addr, IntRegs:$src)>; 777def : Pat<(truncstore IntRegs:$src, ADDRri:$addr, i1), 778 (STBri ADDRri:$addr, IntRegs:$src)>; 779