SparcInstrInfo.td revision 57ff2e3ee711c8d6ab908c6f03d5806b34d910f0
1//===- SparcV8Instrs.td - Target Description for SparcV8 Target -----------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the SparcV8 instructions in TableGen format. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// Instruction format superclass 16//===----------------------------------------------------------------------===// 17 18class InstV8 : Instruction { // SparcV8 instruction baseline 19 field bits<32> Inst; 20 21 let Namespace = "V8"; 22 23 bits<2> op; 24 let Inst{31-30} = op; // Top two bits are the 'op' field 25 26 // Bit attributes specific to SparcV8 instructions 27 bit isPasi = 0; // Does this instruction affect an alternate addr space? 28 bit isPrivileged = 0; // Is this a privileged instruction? 29} 30 31include "SparcV8InstrInfo_F2.td" 32include "SparcV8InstrInfo_F3.td" 33 34//===----------------------------------------------------------------------===// 35// Instructions 36//===----------------------------------------------------------------------===// 37 38// Pseudo instructions. 39def PHI : InstV8 { 40 let Name = "PHI"; 41} 42def ADJCALLSTACKDOWN : InstV8 { 43 let Name = "ADJCALLSTACKDOWN"; 44} 45def ADJCALLSTACKUP : InstV8 { 46 let Name = "ADJCALLSTACKUP"; 47} 48 49// Section A.3 - Synthetic Instructions, p. 85 50// special cases of JMPL: 51let isReturn = 1, isTerminator = 1, simm13 = 8 in 52 def RET : F3_2<2, 0b111000, "ret">; 53let isReturn = 1, isTerminator = 1, simm13 = 8 in 54 def RETL: F3_2<2, 0b111000, "retl">; 55// CMP is a special case of SUBCC where destination is ignored, by setting it to 56// %g0 (hardwired zero). 57// FIXME: should keep track of the fact that it defs the integer condition codes 58let rd = 0 in 59 def CMPri: F3_2<2, 0b010100, "cmp">; 60 61// Section B.1 - Load Integer Instructions, p. 90 62def LDSB: F3_2<3, 0b001001, "ldsb">; 63def LDSH: F3_2<3, 0b001010, "ldsh">; 64def LDUB: F3_2<3, 0b000001, "ldub">; 65def LDUH: F3_2<3, 0b000010, "lduh">; 66def LD : F3_2<3, 0b000000, "ld">; 67def LDD : F3_2<3, 0b000011, "ldd">; 68 69// Section B.2 - Load Floating-point Instructions, p. 92 70def LDFrr : F3_1<3, 0b100000, "ld">; 71def LDFri : F3_2<3, 0b100000, "ld">; 72def LDDFrr : F3_1<3, 0b100011, "ldd">; 73def LDDFri : F3_2<3, 0b100011, "ldd">; 74def LDFSRrr: F3_1<3, 0b100001, "ld">; 75def LDFSRri: F3_2<3, 0b100001, "ld">; 76 77// Section B.4 - Store Integer Instructions, p. 95 78def STB : F3_2<3, 0b000101, "stb">; 79def STH : F3_2<3, 0b000110, "sth">; 80def ST : F3_2<3, 0b000100, "st">; 81def STD : F3_2<3, 0b000111, "std">; 82 83// Section B.5 - Store Floating-point Instructions, p. 97 84def STFrr : F3_1<3, 0b100100, "st">; 85def STFri : F3_2<3, 0b100100, "st">; 86def STDFrr : F3_1<3, 0b100111, "std">; 87def STDFri : F3_2<3, 0b100111, "std">; 88def STFSRrr : F3_1<3, 0b100101, "st">; 89def STFSRri : F3_2<3, 0b100101, "st">; 90def STDFQrr : F3_1<3, 0b100110, "std">; 91def STDFQri : F3_2<3, 0b100110, "std">; 92 93// Section B.9 - SETHI Instruction, p. 104 94def SETHIi: F2_1<0b100, "sethi">; 95 96// Section B.10 - NOP Instruction, p. 105 97// (It's a special case of SETHI) 98let rd = 0, imm = 0 in 99 def NOP : F2_1<0b100, "nop">; 100 101// Section B.11 - Logical Instructions, p. 106 102def ANDrr : F3_1<2, 0b000001, "and">; 103def ANDri : F3_2<2, 0b000001, "and">; 104def ORrr : F3_1<2, 0b000010, "or">; 105def ORri : F3_2<2, 0b000010, "or">; 106def XORrr : F3_1<2, 0b000011, "xor">; 107def XORri : F3_2<2, 0b000011, "xor">; 108 109// Section B.12 - Shift Instructions, p. 107 110def SLLrr : F3_1<2, 0b100101, "sll">; 111def SLLri : F3_2<2, 0b100101, "sll">; 112def SRLrr : F3_1<2, 0b100110, "srl">; 113def SRLri : F3_2<2, 0b100110, "srl">; 114def SRArr : F3_1<2, 0b100111, "sra">; 115def SRAri : F3_2<2, 0b100111, "sra">; 116 117// Section B.13 - Add Instructions, p. 108 118def ADDrr : F3_1<2, 0b000000, "add">; 119def ADDri : F3_2<2, 0b000000, "add">; 120 121// Section B.15 - Subtract Instructions, p. 110 122def SUBrr : F3_1<2, 0b000100, "sub">; 123def SUBCCrr : F3_1<2, 0b010100, "subcc">; 124def SUBCCri : F3_2<2, 0b010100, "subcc">; 125 126// Section B.18 - Multiply Instructions, p. 113 127def UMULrr : F3_1<2, 0b001010, "umul">; 128def SMULrr : F3_1<2, 0b001011, "smul">; 129 130// Section B.19 - Divide Instructions, p. 115 131def UDIVrr : F3_1<2, 0b001110, "udiv">; 132def UDIVri : F3_2<2, 0b001110, "udiv">; 133def SDIVrr : F3_1<2, 0b001111, "sdiv">; 134def SDIVri : F3_2<2, 0b001111, "sdiv">; 135def UDIVCCrr : F3_1<2, 0b011110, "udivcc">; 136def UDIVCCri : F3_2<2, 0b011110, "udivcc">; 137def SDIVCCrr : F3_1<2, 0b011111, "sdivcc">; 138def SDIVCCri : F3_2<2, 0b011111, "sdivcc">; 139 140// Section B.20 - SAVE and RESTORE, p. 117 141def SAVErr : F3_1<2, 0b111100, "save">; // save r, r, r 142def SAVEri : F3_2<2, 0b111100, "save">; // save r, i, r 143def RESTORErr : F3_1<2, 0b111101, "restore">; // restore r, r, r 144def RESTOREri : F3_2<2, 0b111101, "restore">; // restore r, i, r 145 146// Section B.21 - Branch on Integer Condition Codes Instructions, p. 119 147 148// conditional branch class: 149class BranchV8<bits<4> cc, string nm> : F2_2<cc, 0b010, nm> { 150 let isBranch = 1; 151 let isTerminator = 1; 152} 153def BA : BranchV8<0b1000, "ba">; 154def BN : BranchV8<0b0000, "bn">; 155def BNE : BranchV8<0b1001, "bne">; 156def BE : BranchV8<0b0001, "be">; 157def BG : BranchV8<0b1010, "bg">; 158def BLE : BranchV8<0b0010, "ble">; 159def BGE : BranchV8<0b1011, "bge">; 160def BL : BranchV8<0b0011, "bl">; 161def BGU : BranchV8<0b1100, "bgu">; 162def BLEU : BranchV8<0b0100, "bleu">; 163def BCC : BranchV8<0b1101, "bcc">; 164def BCS : BranchV8<0b0101, "bcs">; 165 166// Section B.24 - Call and Link Instruction, p. 125 167// This is the only Format 1 instruction 168def CALL : InstV8 { 169 bits<30> disp; 170 let op = 1; 171 let Inst{29-0} = disp; 172 let Name = "call"; 173 let isCall = 1; 174} 175 176// Section B.25 - Jump and Link, p. 126 177let isCall = 1 in 178 def JMPLrr : F3_1<2, 0b111000, "jmpl">; // jmpl [rs1+rs2], rd 179 180// Section B.29 - Write State Register Instructions 181def WRrr : F3_1<2, 0b110000, "wr">; // wr rs1, rs2, rd 182def WRri : F3_2<2, 0b110000, "wr">; // wr rs1, imm, rd 183 184// Convert between Floating-point Formats Instructions, p. 143 185def FSTOD : F3_3<2, 0b110100, 0b011001001, "fstod">; 186def FDTOS : F3_3<2, 0b110100, 0b011000110, "fdtos">; 187 188// Floating-point Move Instructions, p. 144 189def FMOVS : F3_3<2, 0b110100, 0b000000001, "fmovs">; 190def FNEGS : F3_3<2, 0b110100, 0b000000101, "fnegs">; 191def FABSS : F3_3<2, 0b110100, 0b000001001, "fabss">; 192 193 194