SparcInstrInfo.td revision 6ef781f3ce0d0311004adba9d1e7dbd7950918dd
1//===- SparcInstrInfo.td - Target Description for Sparc Target ------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the Sparc instructions in TableGen format. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// Instruction format superclass 16//===----------------------------------------------------------------------===// 17 18include "SparcInstrFormats.td" 19 20//===----------------------------------------------------------------------===// 21// Feature predicates. 22//===----------------------------------------------------------------------===// 23 24// HasV9 - This predicate is true when the target processor supports V9 25// instructions. Note that the machine may be running in 32-bit mode. 26def HasV9 : Predicate<"Subtarget.isV9()">; 27 28// HasNoV9 - This predicate is true when the target doesn't have V9 29// instructions. Use of this is just a hack for the isel not having proper 30// costs for V8 instructions that are more expensive than their V9 ones. 31def HasNoV9 : Predicate<"!Subtarget.isV9()">; 32 33// HasVIS - This is true when the target processor has VIS extensions. 34def HasVIS : Predicate<"Subtarget.isVIS()">; 35 36// UseDeprecatedInsts - This predicate is true when the target processor is a 37// V8, or when it is V9 but the V8 deprecated instructions are efficient enough 38// to use when appropriate. In either of these cases, the instruction selector 39// will pick deprecated instructions. 40def UseDeprecatedInsts : Predicate<"Subtarget.useDeprecatedV8Instructions()">; 41 42//===----------------------------------------------------------------------===// 43// Instruction Pattern Stuff 44//===----------------------------------------------------------------------===// 45 46def simm11 : PatLeaf<(imm), [{ 47 // simm11 predicate - True if the imm fits in a 11-bit sign extended field. 48 return (((int)N->getValue() << (32-11)) >> (32-11)) == (int)N->getValue(); 49}]>; 50 51def simm13 : PatLeaf<(imm), [{ 52 // simm13 predicate - True if the imm fits in a 13-bit sign extended field. 53 return (((int)N->getValue() << (32-13)) >> (32-13)) == (int)N->getValue(); 54}]>; 55 56def LO10 : SDNodeXForm<imm, [{ 57 return CurDAG->getTargetConstant((unsigned)N->getValue() & 1023, MVT::i32); 58}]>; 59 60def HI22 : SDNodeXForm<imm, [{ 61 // Transformation function: shift the immediate value down into the low bits. 62 return CurDAG->getTargetConstant((unsigned)N->getValue() >> 10, MVT::i32); 63}]>; 64 65def SETHIimm : PatLeaf<(imm), [{ 66 return (((unsigned)N->getValue() >> 10) << 10) == (unsigned)N->getValue(); 67}], HI22>; 68 69// Addressing modes. 70def ADDRrr : ComplexPattern<i32, 2, "SelectADDRrr", [], []>; 71def ADDRri : ComplexPattern<i32, 2, "SelectADDRri", [frameindex], []>; 72 73// Address operands 74def MEMrr : Operand<i32> { 75 let PrintMethod = "printMemOperand"; 76 let MIOperandInfo = (ops IntRegs, IntRegs); 77} 78def MEMri : Operand<i32> { 79 let PrintMethod = "printMemOperand"; 80 let MIOperandInfo = (ops IntRegs, i32imm); 81} 82 83// Branch targets have OtherVT type. 84def brtarget : Operand<OtherVT>; 85def calltarget : Operand<i32>; 86 87// Operand for printing out a condition code. 88let PrintMethod = "printCCOperand" in 89 def CCOp : Operand<i32>; 90 91def SDTSPcmpfcc : 92SDTypeProfile<0, 2, [SDTCisFP<0>, SDTCisSameAs<0, 1>]>; 93def SDTSPbrcc : 94SDTypeProfile<0, 2, [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>; 95def SDTSPselectcc : 96SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>]>; 97def SDTSPFTOI : 98SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisFP<1>]>; 99def SDTSPITOF : 100SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f32>]>; 101 102def SPcmpicc : SDNode<"SPISD::CMPICC", SDTIntBinOp, [SDNPOutFlag]>; 103def SPcmpfcc : SDNode<"SPISD::CMPFCC", SDTSPcmpfcc, [SDNPOutFlag]>; 104def SPbricc : SDNode<"SPISD::BRICC", SDTSPbrcc, [SDNPHasChain, SDNPInFlag]>; 105def SPbrfcc : SDNode<"SPISD::BRFCC", SDTSPbrcc, [SDNPHasChain, SDNPInFlag]>; 106 107def SPhi : SDNode<"SPISD::Hi", SDTIntUnaryOp>; 108def SPlo : SDNode<"SPISD::Lo", SDTIntUnaryOp>; 109 110def SPftoi : SDNode<"SPISD::FTOI", SDTSPFTOI>; 111def SPitof : SDNode<"SPISD::ITOF", SDTSPITOF>; 112 113def SPselecticc : SDNode<"SPISD::SELECT_ICC", SDTSPselectcc, [SDNPInFlag]>; 114def SPselectfcc : SDNode<"SPISD::SELECT_FCC", SDTSPselectcc, [SDNPInFlag]>; 115 116// These are target-independent nodes, but have target-specific formats. 117def SDT_SPCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>; 118def SDT_SPCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, 119 SDTCisVT<1, i32> ]>; 120 121def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_SPCallSeqStart, 122 [SDNPHasChain, SDNPOutFlag]>; 123def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_SPCallSeqEnd, 124 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; 125 126def SDT_SPCall : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>; 127def call : SDNode<"SPISD::CALL", SDT_SPCall, 128 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; 129 130def SDT_SPRetFlag : SDTypeProfile<0, 0, []>; 131def retflag : SDNode<"SPISD::RET_FLAG", SDT_SPRetFlag, 132 [SDNPHasChain, SDNPOptInFlag]>; 133 134//===----------------------------------------------------------------------===// 135// SPARC Flag Conditions 136//===----------------------------------------------------------------------===// 137 138// Note that these values must be kept in sync with the CCOp::CondCode enum 139// values. 140class ICC_VAL<int N> : PatLeaf<(i32 N)>; 141def ICC_NE : ICC_VAL< 9>; // Not Equal 142def ICC_E : ICC_VAL< 1>; // Equal 143def ICC_G : ICC_VAL<10>; // Greater 144def ICC_LE : ICC_VAL< 2>; // Less or Equal 145def ICC_GE : ICC_VAL<11>; // Greater or Equal 146def ICC_L : ICC_VAL< 3>; // Less 147def ICC_GU : ICC_VAL<12>; // Greater Unsigned 148def ICC_LEU : ICC_VAL< 4>; // Less or Equal Unsigned 149def ICC_CC : ICC_VAL<13>; // Carry Clear/Great or Equal Unsigned 150def ICC_CS : ICC_VAL< 5>; // Carry Set/Less Unsigned 151def ICC_POS : ICC_VAL<14>; // Positive 152def ICC_NEG : ICC_VAL< 6>; // Negative 153def ICC_VC : ICC_VAL<15>; // Overflow Clear 154def ICC_VS : ICC_VAL< 7>; // Overflow Set 155 156class FCC_VAL<int N> : PatLeaf<(i32 N)>; 157def FCC_U : FCC_VAL<23>; // Unordered 158def FCC_G : FCC_VAL<22>; // Greater 159def FCC_UG : FCC_VAL<21>; // Unordered or Greater 160def FCC_L : FCC_VAL<20>; // Less 161def FCC_UL : FCC_VAL<19>; // Unordered or Less 162def FCC_LG : FCC_VAL<18>; // Less or Greater 163def FCC_NE : FCC_VAL<17>; // Not Equal 164def FCC_E : FCC_VAL<25>; // Equal 165def FCC_UE : FCC_VAL<24>; // Unordered or Equal 166def FCC_GE : FCC_VAL<25>; // Greater or Equal 167def FCC_UGE : FCC_VAL<26>; // Unordered or Greater or Equal 168def FCC_LE : FCC_VAL<27>; // Less or Equal 169def FCC_ULE : FCC_VAL<28>; // Unordered or Less or Equal 170def FCC_O : FCC_VAL<29>; // Ordered 171 172//===----------------------------------------------------------------------===// 173// Instruction Class Templates 174//===----------------------------------------------------------------------===// 175 176/// F3_12 multiclass - Define a normal F3_1/F3_2 pattern in one shot. 177multiclass F3_12<string OpcStr, bits<6> Op3Val, SDNode OpNode> { 178 def rr : F3_1<2, Op3Val, 179 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c), 180 !strconcat(OpcStr, " $b, $c, $dst"), 181 [(set IntRegs:$dst, (OpNode IntRegs:$b, IntRegs:$c))]>; 182 def ri : F3_2<2, Op3Val, 183 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c), 184 !strconcat(OpcStr, " $b, $c, $dst"), 185 [(set IntRegs:$dst, (OpNode IntRegs:$b, simm13:$c))]>; 186} 187 188/// F3_12np multiclass - Define a normal F3_1/F3_2 pattern in one shot, with no 189/// pattern. 190multiclass F3_12np<string OpcStr, bits<6> Op3Val> { 191 def rr : F3_1<2, Op3Val, 192 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c), 193 !strconcat(OpcStr, " $b, $c, $dst"), []>; 194 def ri : F3_2<2, Op3Val, 195 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c), 196 !strconcat(OpcStr, " $b, $c, $dst"), []>; 197} 198 199//===----------------------------------------------------------------------===// 200// Instructions 201//===----------------------------------------------------------------------===// 202 203// Pseudo instructions. 204class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern> 205 : InstSP<outs, ins, asmstr, pattern>; 206 207let Defs = [O6], Uses = [O6] in { 208def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt), 209 "!ADJCALLSTACKDOWN $amt", 210 [(callseq_start imm:$amt)]>; 211def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2), 212 "!ADJCALLSTACKUP $amt1", 213 [(callseq_end imm:$amt1, imm:$amt2)]>; 214} 215 216let isImplicitDef = 1 in { 217def IMPLICIT_DEF_Int : Pseudo<(outs IntRegs:$dst), (ins), 218 "!IMPLICIT_DEF $dst", 219 [(set IntRegs:$dst, (undef))]>; 220def IMPLICIT_DEF_FP : Pseudo<(outs FPRegs:$dst), (ins), "!IMPLICIT_DEF $dst", 221 [(set FPRegs:$dst, (undef))]>; 222def IMPLICIT_DEF_DFP : Pseudo<(outs DFPRegs:$dst), (ins), "!IMPLICIT_DEF $dst", 223 [(set DFPRegs:$dst, (undef))]>; 224} 225 226// FpMOVD/FpNEGD/FpABSD - These are lowered to single-precision ops by the 227// fpmover pass. 228let Predicates = [HasNoV9] in { // Only emit these in V8 mode. 229 def FpMOVD : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$src), 230 "!FpMOVD $src, $dst", []>; 231 def FpNEGD : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$src), 232 "!FpNEGD $src, $dst", 233 [(set DFPRegs:$dst, (fneg DFPRegs:$src))]>; 234 def FpABSD : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$src), 235 "!FpABSD $src, $dst", 236 [(set DFPRegs:$dst, (fabs DFPRegs:$src))]>; 237} 238 239// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded by the 240// scheduler into a branch sequence. This has to handle all permutations of 241// selection between i32/f32/f64 on ICC and FCC. 242let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler. 243 def SELECT_CC_Int_ICC 244 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond), 245 "; SELECT_CC_Int_ICC PSEUDO!", 246 [(set IntRegs:$dst, (SPselecticc IntRegs:$T, IntRegs:$F, 247 imm:$Cond))]>; 248 def SELECT_CC_Int_FCC 249 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond), 250 "; SELECT_CC_Int_FCC PSEUDO!", 251 [(set IntRegs:$dst, (SPselectfcc IntRegs:$T, IntRegs:$F, 252 imm:$Cond))]>; 253 def SELECT_CC_FP_ICC 254 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, i32imm:$Cond), 255 "; SELECT_CC_FP_ICC PSEUDO!", 256 [(set FPRegs:$dst, (SPselecticc FPRegs:$T, FPRegs:$F, 257 imm:$Cond))]>; 258 def SELECT_CC_FP_FCC 259 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, i32imm:$Cond), 260 "; SELECT_CC_FP_FCC PSEUDO!", 261 [(set FPRegs:$dst, (SPselectfcc FPRegs:$T, FPRegs:$F, 262 imm:$Cond))]>; 263 def SELECT_CC_DFP_ICC 264 : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, i32imm:$Cond), 265 "; SELECT_CC_DFP_ICC PSEUDO!", 266 [(set DFPRegs:$dst, (SPselecticc DFPRegs:$T, DFPRegs:$F, 267 imm:$Cond))]>; 268 def SELECT_CC_DFP_FCC 269 : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, i32imm:$Cond), 270 "; SELECT_CC_DFP_FCC PSEUDO!", 271 [(set DFPRegs:$dst, (SPselectfcc DFPRegs:$T, DFPRegs:$F, 272 imm:$Cond))]>; 273} 274 275 276// Section A.3 - Synthetic Instructions, p. 85 277// special cases of JMPL: 278let isReturn = 1, isTerminator = 1, hasDelaySlot = 1 in { 279 let rd = O7.Num, rs1 = G0.Num, simm13 = 8 in 280 def RETL: F3_2<2, 0b111000, (outs), (ins), "retl", [(retflag)]>; 281} 282 283// Section B.1 - Load Integer Instructions, p. 90 284def LDSBrr : F3_1<3, 0b001001, 285 (outs IntRegs:$dst), (ins MEMrr:$addr), 286 "ldsb [$addr], $dst", 287 [(set IntRegs:$dst, (sextloadi8 ADDRrr:$addr))]>; 288def LDSBri : F3_2<3, 0b001001, 289 (outs IntRegs:$dst), (ins MEMri:$addr), 290 "ldsb [$addr], $dst", 291 [(set IntRegs:$dst, (sextloadi8 ADDRri:$addr))]>; 292def LDSHrr : F3_1<3, 0b001010, 293 (outs IntRegs:$dst), (ins MEMrr:$addr), 294 "ldsh [$addr], $dst", 295 [(set IntRegs:$dst, (sextloadi16 ADDRrr:$addr))]>; 296def LDSHri : F3_2<3, 0b001010, 297 (outs IntRegs:$dst), (ins MEMri:$addr), 298 "ldsh [$addr], $dst", 299 [(set IntRegs:$dst, (sextloadi16 ADDRri:$addr))]>; 300def LDUBrr : F3_1<3, 0b000001, 301 (outs IntRegs:$dst), (ins MEMrr:$addr), 302 "ldub [$addr], $dst", 303 [(set IntRegs:$dst, (zextloadi8 ADDRrr:$addr))]>; 304def LDUBri : F3_2<3, 0b000001, 305 (outs IntRegs:$dst), (ins MEMri:$addr), 306 "ldub [$addr], $dst", 307 [(set IntRegs:$dst, (zextloadi8 ADDRri:$addr))]>; 308def LDUHrr : F3_1<3, 0b000010, 309 (outs IntRegs:$dst), (ins MEMrr:$addr), 310 "lduh [$addr], $dst", 311 [(set IntRegs:$dst, (zextloadi16 ADDRrr:$addr))]>; 312def LDUHri : F3_2<3, 0b000010, 313 (outs IntRegs:$dst), (ins MEMri:$addr), 314 "lduh [$addr], $dst", 315 [(set IntRegs:$dst, (zextloadi16 ADDRri:$addr))]>; 316def LDrr : F3_1<3, 0b000000, 317 (outs IntRegs:$dst), (ins MEMrr:$addr), 318 "ld [$addr], $dst", 319 [(set IntRegs:$dst, (load ADDRrr:$addr))]>; 320def LDri : F3_2<3, 0b000000, 321 (outs IntRegs:$dst), (ins MEMri:$addr), 322 "ld [$addr], $dst", 323 [(set IntRegs:$dst, (load ADDRri:$addr))]>; 324 325// Section B.2 - Load Floating-point Instructions, p. 92 326def LDFrr : F3_1<3, 0b100000, 327 (outs FPRegs:$dst), (ins MEMrr:$addr), 328 "ld [$addr], $dst", 329 [(set FPRegs:$dst, (load ADDRrr:$addr))]>; 330def LDFri : F3_2<3, 0b100000, 331 (outs FPRegs:$dst), (ins MEMri:$addr), 332 "ld [$addr], $dst", 333 [(set FPRegs:$dst, (load ADDRri:$addr))]>; 334def LDDFrr : F3_1<3, 0b100011, 335 (outs DFPRegs:$dst), (ins MEMrr:$addr), 336 "ldd [$addr], $dst", 337 [(set DFPRegs:$dst, (load ADDRrr:$addr))]>; 338def LDDFri : F3_2<3, 0b100011, 339 (outs DFPRegs:$dst), (ins MEMri:$addr), 340 "ldd [$addr], $dst", 341 [(set DFPRegs:$dst, (load ADDRri:$addr))]>; 342 343// Section B.4 - Store Integer Instructions, p. 95 344def STBrr : F3_1<3, 0b000101, 345 (outs), (ins MEMrr:$addr, IntRegs:$src), 346 "stb $src, [$addr]", 347 [(truncstorei8 IntRegs:$src, ADDRrr:$addr)]>; 348def STBri : F3_2<3, 0b000101, 349 (outs), (ins MEMri:$addr, IntRegs:$src), 350 "stb $src, [$addr]", 351 [(truncstorei8 IntRegs:$src, ADDRri:$addr)]>; 352def STHrr : F3_1<3, 0b000110, 353 (outs), (ins MEMrr:$addr, IntRegs:$src), 354 "sth $src, [$addr]", 355 [(truncstorei16 IntRegs:$src, ADDRrr:$addr)]>; 356def STHri : F3_2<3, 0b000110, 357 (outs), (ins MEMri:$addr, IntRegs:$src), 358 "sth $src, [$addr]", 359 [(truncstorei16 IntRegs:$src, ADDRri:$addr)]>; 360def STrr : F3_1<3, 0b000100, 361 (outs), (ins MEMrr:$addr, IntRegs:$src), 362 "st $src, [$addr]", 363 [(store IntRegs:$src, ADDRrr:$addr)]>; 364def STri : F3_2<3, 0b000100, 365 (outs), (ins MEMri:$addr, IntRegs:$src), 366 "st $src, [$addr]", 367 [(store IntRegs:$src, ADDRri:$addr)]>; 368 369// Section B.5 - Store Floating-point Instructions, p. 97 370def STFrr : F3_1<3, 0b100100, 371 (outs), (ins MEMrr:$addr, FPRegs:$src), 372 "st $src, [$addr]", 373 [(store FPRegs:$src, ADDRrr:$addr)]>; 374def STFri : F3_2<3, 0b100100, 375 (outs), (ins MEMri:$addr, FPRegs:$src), 376 "st $src, [$addr]", 377 [(store FPRegs:$src, ADDRri:$addr)]>; 378def STDFrr : F3_1<3, 0b100111, 379 (outs), (ins MEMrr:$addr, DFPRegs:$src), 380 "std $src, [$addr]", 381 [(store DFPRegs:$src, ADDRrr:$addr)]>; 382def STDFri : F3_2<3, 0b100111, 383 (outs), (ins MEMri:$addr, DFPRegs:$src), 384 "std $src, [$addr]", 385 [(store DFPRegs:$src, ADDRri:$addr)]>; 386 387// Section B.9 - SETHI Instruction, p. 104 388def SETHIi: F2_1<0b100, 389 (outs IntRegs:$dst), (ins i32imm:$src), 390 "sethi $src, $dst", 391 [(set IntRegs:$dst, SETHIimm:$src)]>; 392 393// Section B.10 - NOP Instruction, p. 105 394// (It's a special case of SETHI) 395let rd = 0, imm22 = 0 in 396 def NOP : F2_1<0b100, (outs), (ins), "nop", []>; 397 398// Section B.11 - Logical Instructions, p. 106 399defm AND : F3_12<"and", 0b000001, and>; 400 401def ANDNrr : F3_1<2, 0b000101, 402 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c), 403 "andn $b, $c, $dst", 404 [(set IntRegs:$dst, (and IntRegs:$b, (not IntRegs:$c)))]>; 405def ANDNri : F3_2<2, 0b000101, 406 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c), 407 "andn $b, $c, $dst", []>; 408 409defm OR : F3_12<"or", 0b000010, or>; 410 411def ORNrr : F3_1<2, 0b000110, 412 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c), 413 "orn $b, $c, $dst", 414 [(set IntRegs:$dst, (or IntRegs:$b, (not IntRegs:$c)))]>; 415def ORNri : F3_2<2, 0b000110, 416 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c), 417 "orn $b, $c, $dst", []>; 418defm XOR : F3_12<"xor", 0b000011, xor>; 419 420def XNORrr : F3_1<2, 0b000111, 421 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c), 422 "xnor $b, $c, $dst", 423 [(set IntRegs:$dst, (not (xor IntRegs:$b, IntRegs:$c)))]>; 424def XNORri : F3_2<2, 0b000111, 425 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c), 426 "xnor $b, $c, $dst", []>; 427 428// Section B.12 - Shift Instructions, p. 107 429defm SLL : F3_12<"sll", 0b100101, shl>; 430defm SRL : F3_12<"srl", 0b100110, srl>; 431defm SRA : F3_12<"sra", 0b100111, sra>; 432 433// Section B.13 - Add Instructions, p. 108 434defm ADD : F3_12<"add", 0b000000, add>; 435 436// "LEA" forms of add (patterns to make tblgen happy) 437def LEA_ADDri : F3_2<2, 0b000000, 438 (outs IntRegs:$dst), (ins MEMri:$addr), 439 "add ${addr:arith}, $dst", 440 [(set IntRegs:$dst, ADDRri:$addr)]>; 441 442defm ADDCC : F3_12<"addcc", 0b010000, addc>; 443defm ADDX : F3_12<"addx", 0b001000, adde>; 444 445// Section B.15 - Subtract Instructions, p. 110 446defm SUB : F3_12 <"sub" , 0b000100, sub>; 447defm SUBX : F3_12 <"subx" , 0b001100, sube>; 448defm SUBCC : F3_12 <"subcc", 0b010100, SPcmpicc>; 449 450def SUBXCCrr: F3_1<2, 0b011100, 451 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c), 452 "subxcc $b, $c, $dst", []>; 453 454// Section B.18 - Multiply Instructions, p. 113 455defm UMUL : F3_12np<"umul", 0b001010>; 456defm SMUL : F3_12 <"smul", 0b001011, mul>; 457 458 459// Section B.19 - Divide Instructions, p. 115 460defm UDIV : F3_12np<"udiv", 0b001110>; 461defm SDIV : F3_12np<"sdiv", 0b001111>; 462 463// Section B.20 - SAVE and RESTORE, p. 117 464defm SAVE : F3_12np<"save" , 0b111100>; 465defm RESTORE : F3_12np<"restore", 0b111101>; 466 467// Section B.21 - Branch on Integer Condition Codes Instructions, p. 119 468 469// conditional branch class: 470class BranchSP<bits<4> cc, dag ins, string asmstr, list<dag> pattern> 471 : F2_2<cc, 0b010, (outs), ins, asmstr, pattern> { 472 let isBranch = 1; 473 let isTerminator = 1; 474 let hasDelaySlot = 1; 475} 476 477let isBarrier = 1 in 478 def BA : BranchSP<0b1000, (ins brtarget:$dst), 479 "ba $dst", 480 [(br bb:$dst)]>; 481 482// FIXME: the encoding for the JIT should look at the condition field. 483def BCOND : BranchSP<0, (ins brtarget:$dst, CCOp:$cc), 484 "b$cc $dst", 485 [(SPbricc bb:$dst, imm:$cc)]>; 486 487 488// Section B.22 - Branch on Floating-point Condition Codes Instructions, p. 121 489 490// floating-point conditional branch class: 491class FPBranchSP<bits<4> cc, dag ins, string asmstr, list<dag> pattern> 492 : F2_2<cc, 0b110, (outs), ins, asmstr, pattern> { 493 let isBranch = 1; 494 let isTerminator = 1; 495 let hasDelaySlot = 1; 496} 497 498// FIXME: the encoding for the JIT should look at the condition field. 499def FBCOND : FPBranchSP<0, (ins brtarget:$dst, CCOp:$cc), 500 "fb$cc $dst", 501 [(SPbrfcc bb:$dst, imm:$cc)]>; 502 503 504// Section B.24 - Call and Link Instruction, p. 125 505// This is the only Format 1 instruction 506let Uses = [O0, O1, O2, O3, O4, O5], 507 hasDelaySlot = 1, isCall = 1, 508 Defs = [O0, O1, O2, O3, O4, O5, O7, G1, G2, G3, G4, G5, G6, G7, 509 D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15] in { 510 def CALL : InstSP<(outs), (ins calltarget:$dst), 511 "call $dst", []> { 512 bits<30> disp; 513 let op = 1; 514 let Inst{29-0} = disp; 515 } 516 517 // indirect calls 518 def JMPLrr : F3_1<2, 0b111000, 519 (outs), (ins MEMrr:$ptr), 520 "call $ptr", 521 [(call ADDRrr:$ptr)]>; 522 def JMPLri : F3_2<2, 0b111000, 523 (outs), (ins MEMri:$ptr), 524 "call $ptr", 525 [(call ADDRri:$ptr)]>; 526} 527 528// Section B.28 - Read State Register Instructions 529def RDY : F3_1<2, 0b101000, 530 (outs IntRegs:$dst), (ins), 531 "rd %y, $dst", []>; 532 533// Section B.29 - Write State Register Instructions 534def WRYrr : F3_1<2, 0b110000, 535 (outs), (ins IntRegs:$b, IntRegs:$c), 536 "wr $b, $c, %y", []>; 537def WRYri : F3_2<2, 0b110000, 538 (outs), (ins IntRegs:$b, i32imm:$c), 539 "wr $b, $c, %y", []>; 540 541// Convert Integer to Floating-point Instructions, p. 141 542def FITOS : F3_3<2, 0b110100, 0b011000100, 543 (outs FPRegs:$dst), (ins FPRegs:$src), 544 "fitos $src, $dst", 545 [(set FPRegs:$dst, (SPitof FPRegs:$src))]>; 546def FITOD : F3_3<2, 0b110100, 0b011001000, 547 (outs DFPRegs:$dst), (ins FPRegs:$src), 548 "fitod $src, $dst", 549 [(set DFPRegs:$dst, (SPitof FPRegs:$src))]>; 550 551// Convert Floating-point to Integer Instructions, p. 142 552def FSTOI : F3_3<2, 0b110100, 0b011010001, 553 (outs FPRegs:$dst), (ins FPRegs:$src), 554 "fstoi $src, $dst", 555 [(set FPRegs:$dst, (SPftoi FPRegs:$src))]>; 556def FDTOI : F3_3<2, 0b110100, 0b011010010, 557 (outs FPRegs:$dst), (ins DFPRegs:$src), 558 "fdtoi $src, $dst", 559 [(set FPRegs:$dst, (SPftoi DFPRegs:$src))]>; 560 561// Convert between Floating-point Formats Instructions, p. 143 562def FSTOD : F3_3<2, 0b110100, 0b011001001, 563 (outs DFPRegs:$dst), (ins FPRegs:$src), 564 "fstod $src, $dst", 565 [(set DFPRegs:$dst, (fextend FPRegs:$src))]>; 566def FDTOS : F3_3<2, 0b110100, 0b011000110, 567 (outs FPRegs:$dst), (ins DFPRegs:$src), 568 "fdtos $src, $dst", 569 [(set FPRegs:$dst, (fround DFPRegs:$src))]>; 570 571// Floating-point Move Instructions, p. 144 572def FMOVS : F3_3<2, 0b110100, 0b000000001, 573 (outs FPRegs:$dst), (ins FPRegs:$src), 574 "fmovs $src, $dst", []>; 575def FNEGS : F3_3<2, 0b110100, 0b000000101, 576 (outs FPRegs:$dst), (ins FPRegs:$src), 577 "fnegs $src, $dst", 578 [(set FPRegs:$dst, (fneg FPRegs:$src))]>; 579def FABSS : F3_3<2, 0b110100, 0b000001001, 580 (outs FPRegs:$dst), (ins FPRegs:$src), 581 "fabss $src, $dst", 582 [(set FPRegs:$dst, (fabs FPRegs:$src))]>; 583 584 585// Floating-point Square Root Instructions, p.145 586def FSQRTS : F3_3<2, 0b110100, 0b000101001, 587 (outs FPRegs:$dst), (ins FPRegs:$src), 588 "fsqrts $src, $dst", 589 [(set FPRegs:$dst, (fsqrt FPRegs:$src))]>; 590def FSQRTD : F3_3<2, 0b110100, 0b000101010, 591 (outs DFPRegs:$dst), (ins DFPRegs:$src), 592 "fsqrtd $src, $dst", 593 [(set DFPRegs:$dst, (fsqrt DFPRegs:$src))]>; 594 595 596 597// Floating-point Add and Subtract Instructions, p. 146 598def FADDS : F3_3<2, 0b110100, 0b001000001, 599 (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2), 600 "fadds $src1, $src2, $dst", 601 [(set FPRegs:$dst, (fadd FPRegs:$src1, FPRegs:$src2))]>; 602def FADDD : F3_3<2, 0b110100, 0b001000010, 603 (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2), 604 "faddd $src1, $src2, $dst", 605 [(set DFPRegs:$dst, (fadd DFPRegs:$src1, DFPRegs:$src2))]>; 606def FSUBS : F3_3<2, 0b110100, 0b001000101, 607 (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2), 608 "fsubs $src1, $src2, $dst", 609 [(set FPRegs:$dst, (fsub FPRegs:$src1, FPRegs:$src2))]>; 610def FSUBD : F3_3<2, 0b110100, 0b001000110, 611 (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2), 612 "fsubd $src1, $src2, $dst", 613 [(set DFPRegs:$dst, (fsub DFPRegs:$src1, DFPRegs:$src2))]>; 614 615// Floating-point Multiply and Divide Instructions, p. 147 616def FMULS : F3_3<2, 0b110100, 0b001001001, 617 (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2), 618 "fmuls $src1, $src2, $dst", 619 [(set FPRegs:$dst, (fmul FPRegs:$src1, FPRegs:$src2))]>; 620def FMULD : F3_3<2, 0b110100, 0b001001010, 621 (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2), 622 "fmuld $src1, $src2, $dst", 623 [(set DFPRegs:$dst, (fmul DFPRegs:$src1, DFPRegs:$src2))]>; 624def FSMULD : F3_3<2, 0b110100, 0b001101001, 625 (outs DFPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2), 626 "fsmuld $src1, $src2, $dst", 627 [(set DFPRegs:$dst, (fmul (fextend FPRegs:$src1), 628 (fextend FPRegs:$src2)))]>; 629def FDIVS : F3_3<2, 0b110100, 0b001001101, 630 (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2), 631 "fdivs $src1, $src2, $dst", 632 [(set FPRegs:$dst, (fdiv FPRegs:$src1, FPRegs:$src2))]>; 633def FDIVD : F3_3<2, 0b110100, 0b001001110, 634 (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2), 635 "fdivd $src1, $src2, $dst", 636 [(set DFPRegs:$dst, (fdiv DFPRegs:$src1, DFPRegs:$src2))]>; 637 638// Floating-point Compare Instructions, p. 148 639// Note: the 2nd template arg is different for these guys. 640// Note 2: the result of a FCMP is not available until the 2nd cycle 641// after the instr is retired, but there is no interlock. This behavior 642// is modelled with a forced noop after the instruction. 643def FCMPS : F3_3<2, 0b110101, 0b001010001, 644 (outs), (ins FPRegs:$src1, FPRegs:$src2), 645 "fcmps $src1, $src2\n\tnop", 646 [(SPcmpfcc FPRegs:$src1, FPRegs:$src2)]>; 647def FCMPD : F3_3<2, 0b110101, 0b001010010, 648 (outs), (ins DFPRegs:$src1, DFPRegs:$src2), 649 "fcmpd $src1, $src2\n\tnop", 650 [(SPcmpfcc DFPRegs:$src1, DFPRegs:$src2)]>; 651 652 653//===----------------------------------------------------------------------===// 654// V9 Instructions 655//===----------------------------------------------------------------------===// 656 657// V9 Conditional Moves. 658let Predicates = [HasV9], isTwoAddress = 1 in { 659 // Move Integer Register on Condition (MOVcc) p. 194 of the V9 manual. 660 // FIXME: Add instruction encodings for the JIT some day. 661 def MOVICCrr 662 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, CCOp:$cc), 663 "mov$cc %icc, $F, $dst", 664 [(set IntRegs:$dst, 665 (SPselecticc IntRegs:$F, IntRegs:$T, imm:$cc))]>; 666 def MOVICCri 667 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, i32imm:$F, CCOp:$cc), 668 "mov$cc %icc, $F, $dst", 669 [(set IntRegs:$dst, 670 (SPselecticc simm11:$F, IntRegs:$T, imm:$cc))]>; 671 672 def MOVFCCrr 673 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, CCOp:$cc), 674 "mov$cc %fcc0, $F, $dst", 675 [(set IntRegs:$dst, 676 (SPselectfcc IntRegs:$F, IntRegs:$T, imm:$cc))]>; 677 def MOVFCCri 678 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, i32imm:$F, CCOp:$cc), 679 "mov$cc %fcc0, $F, $dst", 680 [(set IntRegs:$dst, 681 (SPselectfcc simm11:$F, IntRegs:$T, imm:$cc))]>; 682 683 def FMOVS_ICC 684 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, CCOp:$cc), 685 "fmovs$cc %icc, $F, $dst", 686 [(set FPRegs:$dst, 687 (SPselecticc FPRegs:$F, FPRegs:$T, imm:$cc))]>; 688 def FMOVD_ICC 689 : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, CCOp:$cc), 690 "fmovd$cc %icc, $F, $dst", 691 [(set DFPRegs:$dst, 692 (SPselecticc DFPRegs:$F, DFPRegs:$T, imm:$cc))]>; 693 def FMOVS_FCC 694 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, CCOp:$cc), 695 "fmovs$cc %fcc0, $F, $dst", 696 [(set FPRegs:$dst, 697 (SPselectfcc FPRegs:$F, FPRegs:$T, imm:$cc))]>; 698 def FMOVD_FCC 699 : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, CCOp:$cc), 700 "fmovd$cc %fcc0, $F, $dst", 701 [(set DFPRegs:$dst, 702 (SPselectfcc DFPRegs:$F, DFPRegs:$T, imm:$cc))]>; 703 704} 705 706// Floating-Point Move Instructions, p. 164 of the V9 manual. 707let Predicates = [HasV9] in { 708 def FMOVD : F3_3<2, 0b110100, 0b000000010, 709 (outs DFPRegs:$dst), (ins DFPRegs:$src), 710 "fmovd $src, $dst", []>; 711 def FNEGD : F3_3<2, 0b110100, 0b000000110, 712 (outs DFPRegs:$dst), (ins DFPRegs:$src), 713 "fnegd $src, $dst", 714 [(set DFPRegs:$dst, (fneg DFPRegs:$src))]>; 715 def FABSD : F3_3<2, 0b110100, 0b000001010, 716 (outs DFPRegs:$dst), (ins DFPRegs:$src), 717 "fabsd $src, $dst", 718 [(set DFPRegs:$dst, (fabs DFPRegs:$src))]>; 719} 720 721// POPCrr - This does a ctpop of a 64-bit register. As such, we have to clear 722// the top 32-bits before using it. To do this clearing, we use a SLLri X,0. 723def POPCrr : F3_1<2, 0b101110, 724 (outs IntRegs:$dst), (ins IntRegs:$src), 725 "popc $src, $dst", []>, Requires<[HasV9]>; 726def : Pat<(ctpop IntRegs:$src), 727 (POPCrr (SLLri IntRegs:$src, 0))>; 728 729//===----------------------------------------------------------------------===// 730// Non-Instruction Patterns 731//===----------------------------------------------------------------------===// 732 733// Small immediates. 734def : Pat<(i32 simm13:$val), 735 (ORri G0, imm:$val)>; 736// Arbitrary immediates. 737def : Pat<(i32 imm:$val), 738 (ORri (SETHIi (HI22 imm:$val)), (LO10 imm:$val))>; 739 740// subc 741def : Pat<(subc IntRegs:$b, IntRegs:$c), 742 (SUBCCrr IntRegs:$b, IntRegs:$c)>; 743def : Pat<(subc IntRegs:$b, simm13:$val), 744 (SUBCCri IntRegs:$b, imm:$val)>; 745 746// Global addresses, constant pool entries 747def : Pat<(SPhi tglobaladdr:$in), (SETHIi tglobaladdr:$in)>; 748def : Pat<(SPlo tglobaladdr:$in), (ORri G0, tglobaladdr:$in)>; 749def : Pat<(SPhi tconstpool:$in), (SETHIi tconstpool:$in)>; 750def : Pat<(SPlo tconstpool:$in), (ORri G0, tconstpool:$in)>; 751 752// Add reg, lo. This is used when taking the addr of a global/constpool entry. 753def : Pat<(add IntRegs:$r, (SPlo tglobaladdr:$in)), 754 (ADDri IntRegs:$r, tglobaladdr:$in)>; 755def : Pat<(add IntRegs:$r, (SPlo tconstpool:$in)), 756 (ADDri IntRegs:$r, tconstpool:$in)>; 757 758// Calls: 759def : Pat<(call tglobaladdr:$dst), 760 (CALL tglobaladdr:$dst)>; 761def : Pat<(call texternalsym:$dst), 762 (CALL texternalsym:$dst)>; 763 764def : Pat<(ret), (RETL)>; 765 766// Map integer extload's to zextloads. 767def : Pat<(i32 (extloadi1 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>; 768def : Pat<(i32 (extloadi1 ADDRri:$src)), (LDUBri ADDRri:$src)>; 769def : Pat<(i32 (extloadi8 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>; 770def : Pat<(i32 (extloadi8 ADDRri:$src)), (LDUBri ADDRri:$src)>; 771def : Pat<(i32 (extloadi16 ADDRrr:$src)), (LDUHrr ADDRrr:$src)>; 772def : Pat<(i32 (extloadi16 ADDRri:$src)), (LDUHri ADDRri:$src)>; 773 774// zextload bool -> zextload byte 775def : Pat<(i32 (zextloadi1 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>; 776def : Pat<(i32 (zextloadi1 ADDRri:$src)), (LDUBri ADDRri:$src)>; 777