SparcInstrInfo.td revision 704df9fcbddd8bd6f358bef688ef51f8540dce4d
1//===- SparcInstrInfo.td - Target Description for Sparc Target ------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the Sparc instructions in TableGen format. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// Instruction format superclass 16//===----------------------------------------------------------------------===// 17 18include "SparcInstrFormats.td" 19 20//===----------------------------------------------------------------------===// 21// Feature predicates. 22//===----------------------------------------------------------------------===// 23 24// HasV9 - This predicate is true when the target processor supports V9 25// instructions. Note that the machine may be running in 32-bit mode. 26def HasV9 : Predicate<"Subtarget.isV9()">; 27 28// HasNoV9 - This predicate is true when the target doesn't have V9 29// instructions. Use of this is just a hack for the isel not having proper 30// costs for V8 instructions that are more expensive than their V9 ones. 31def HasNoV9 : Predicate<"!Subtarget.isV9()">; 32 33// HasVIS - This is true when the target processor has VIS extensions. 34def HasVIS : Predicate<"Subtarget.isVIS()">; 35 36// UseDeprecatedInsts - This predicate is true when the target processor is a 37// V8, or when it is V9 but the V8 deprecated instructions are efficient enough 38// to use when appropriate. In either of these cases, the instruction selector 39// will pick deprecated instructions. 40def UseDeprecatedInsts : Predicate<"Subtarget.useDeprecatedV8Instructions()">; 41 42//===----------------------------------------------------------------------===// 43// Instruction Pattern Stuff 44//===----------------------------------------------------------------------===// 45 46def simm11 : PatLeaf<(imm), [{ 47 // simm11 predicate - True if the imm fits in a 11-bit sign extended field. 48 return (((int)N->getValue() << (32-11)) >> (32-11)) == (int)N->getValue(); 49}]>; 50 51def simm13 : PatLeaf<(imm), [{ 52 // simm13 predicate - True if the imm fits in a 13-bit sign extended field. 53 return (((int)N->getValue() << (32-13)) >> (32-13)) == (int)N->getValue(); 54}]>; 55 56def LO10 : SDNodeXForm<imm, [{ 57 return CurDAG->getTargetConstant((unsigned)N->getValue() & 1023, MVT::i32); 58}]>; 59 60def HI22 : SDNodeXForm<imm, [{ 61 // Transformation function: shift the immediate value down into the low bits. 62 return CurDAG->getTargetConstant((unsigned)N->getValue() >> 10, MVT::i32); 63}]>; 64 65def SETHIimm : PatLeaf<(imm), [{ 66 return (((unsigned)N->getValue() >> 10) << 10) == (unsigned)N->getValue(); 67}], HI22>; 68 69// Addressing modes. 70def ADDRrr : ComplexPattern<i32, 2, "SelectADDRrr", [], []>; 71def ADDRri : ComplexPattern<i32, 2, "SelectADDRri", [frameindex], []>; 72 73// Address operands 74def MEMrr : Operand<i32> { 75 let PrintMethod = "printMemOperand"; 76 let MIOperandInfo = (ops IntRegs, IntRegs); 77} 78def MEMri : Operand<i32> { 79 let PrintMethod = "printMemOperand"; 80 let MIOperandInfo = (ops IntRegs, i32imm); 81} 82 83// Branch targets have OtherVT type. 84def brtarget : Operand<OtherVT>; 85def calltarget : Operand<i32>; 86 87// Operand for printing out a condition code. 88let PrintMethod = "printCCOperand" in 89 def CCOp : Operand<i32>; 90 91def SDTSPcmpfcc : 92SDTypeProfile<0, 2, [SDTCisFP<0>, SDTCisSameAs<0, 1>]>; 93def SDTSPbrcc : 94SDTypeProfile<0, 2, [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>; 95def SDTSPselectcc : 96SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>]>; 97def SDTSPFTOI : 98SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisFP<1>]>; 99def SDTSPITOF : 100SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f32>]>; 101 102def SPcmpicc : SDNode<"SPISD::CMPICC", SDTIntBinOp, [SDNPOutFlag]>; 103def SPcmpfcc : SDNode<"SPISD::CMPFCC", SDTSPcmpfcc, [SDNPOutFlag]>; 104def SPbricc : SDNode<"SPISD::BRICC", SDTSPbrcc, [SDNPHasChain, SDNPInFlag]>; 105def SPbrfcc : SDNode<"SPISD::BRFCC", SDTSPbrcc, [SDNPHasChain, SDNPInFlag]>; 106 107def SPhi : SDNode<"SPISD::Hi", SDTIntUnaryOp>; 108def SPlo : SDNode<"SPISD::Lo", SDTIntUnaryOp>; 109 110def SPftoi : SDNode<"SPISD::FTOI", SDTSPFTOI>; 111def SPitof : SDNode<"SPISD::ITOF", SDTSPITOF>; 112 113def SPselecticc : SDNode<"SPISD::SELECT_ICC", SDTSPselectcc, [SDNPInFlag]>; 114def SPselectfcc : SDNode<"SPISD::SELECT_FCC", SDTSPselectcc, [SDNPInFlag]>; 115 116// These are target-independent nodes, but have target-specific formats. 117def SDT_SPCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>; 118def SDT_SPCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, 119 SDTCisVT<1, i32> ]>; 120 121def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_SPCallSeqStart, 122 [SDNPHasChain, SDNPOutFlag]>; 123def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_SPCallSeqEnd, 124 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; 125 126def SDT_SPCall : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>; 127def call : SDNode<"SPISD::CALL", SDT_SPCall, 128 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; 129 130def retflag : SDNode<"SPISD::RET_FLAG", SDTNone, 131 [SDNPHasChain, SDNPOptInFlag]>; 132 133//===----------------------------------------------------------------------===// 134// SPARC Flag Conditions 135//===----------------------------------------------------------------------===// 136 137// Note that these values must be kept in sync with the CCOp::CondCode enum 138// values. 139class ICC_VAL<int N> : PatLeaf<(i32 N)>; 140def ICC_NE : ICC_VAL< 9>; // Not Equal 141def ICC_E : ICC_VAL< 1>; // Equal 142def ICC_G : ICC_VAL<10>; // Greater 143def ICC_LE : ICC_VAL< 2>; // Less or Equal 144def ICC_GE : ICC_VAL<11>; // Greater or Equal 145def ICC_L : ICC_VAL< 3>; // Less 146def ICC_GU : ICC_VAL<12>; // Greater Unsigned 147def ICC_LEU : ICC_VAL< 4>; // Less or Equal Unsigned 148def ICC_CC : ICC_VAL<13>; // Carry Clear/Great or Equal Unsigned 149def ICC_CS : ICC_VAL< 5>; // Carry Set/Less Unsigned 150def ICC_POS : ICC_VAL<14>; // Positive 151def ICC_NEG : ICC_VAL< 6>; // Negative 152def ICC_VC : ICC_VAL<15>; // Overflow Clear 153def ICC_VS : ICC_VAL< 7>; // Overflow Set 154 155class FCC_VAL<int N> : PatLeaf<(i32 N)>; 156def FCC_U : FCC_VAL<23>; // Unordered 157def FCC_G : FCC_VAL<22>; // Greater 158def FCC_UG : FCC_VAL<21>; // Unordered or Greater 159def FCC_L : FCC_VAL<20>; // Less 160def FCC_UL : FCC_VAL<19>; // Unordered or Less 161def FCC_LG : FCC_VAL<18>; // Less or Greater 162def FCC_NE : FCC_VAL<17>; // Not Equal 163def FCC_E : FCC_VAL<25>; // Equal 164def FCC_UE : FCC_VAL<24>; // Unordered or Equal 165def FCC_GE : FCC_VAL<25>; // Greater or Equal 166def FCC_UGE : FCC_VAL<26>; // Unordered or Greater or Equal 167def FCC_LE : FCC_VAL<27>; // Less or Equal 168def FCC_ULE : FCC_VAL<28>; // Unordered or Less or Equal 169def FCC_O : FCC_VAL<29>; // Ordered 170 171//===----------------------------------------------------------------------===// 172// Instruction Class Templates 173//===----------------------------------------------------------------------===// 174 175/// F3_12 multiclass - Define a normal F3_1/F3_2 pattern in one shot. 176multiclass F3_12<string OpcStr, bits<6> Op3Val, SDNode OpNode> { 177 def rr : F3_1<2, Op3Val, 178 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c), 179 !strconcat(OpcStr, " $b, $c, $dst"), 180 [(set IntRegs:$dst, (OpNode IntRegs:$b, IntRegs:$c))]>; 181 def ri : F3_2<2, Op3Val, 182 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c), 183 !strconcat(OpcStr, " $b, $c, $dst"), 184 [(set IntRegs:$dst, (OpNode IntRegs:$b, simm13:$c))]>; 185} 186 187/// F3_12np multiclass - Define a normal F3_1/F3_2 pattern in one shot, with no 188/// pattern. 189multiclass F3_12np<string OpcStr, bits<6> Op3Val> { 190 def rr : F3_1<2, Op3Val, 191 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c), 192 !strconcat(OpcStr, " $b, $c, $dst"), []>; 193 def ri : F3_2<2, Op3Val, 194 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c), 195 !strconcat(OpcStr, " $b, $c, $dst"), []>; 196} 197 198//===----------------------------------------------------------------------===// 199// Instructions 200//===----------------------------------------------------------------------===// 201 202// Pseudo instructions. 203class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern> 204 : InstSP<outs, ins, asmstr, pattern>; 205 206let Defs = [O6], Uses = [O6] in { 207def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt), 208 "!ADJCALLSTACKDOWN $amt", 209 [(callseq_start imm:$amt)]>; 210def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2), 211 "!ADJCALLSTACKUP $amt1", 212 [(callseq_end imm:$amt1, imm:$amt2)]>; 213} 214 215let isImplicitDef = 1 in { 216def IMPLICIT_DEF_Int : Pseudo<(outs IntRegs:$dst), (ins), 217 "!IMPLICIT_DEF $dst", 218 [(set IntRegs:$dst, (undef))]>; 219def IMPLICIT_DEF_FP : Pseudo<(outs FPRegs:$dst), (ins), "!IMPLICIT_DEF $dst", 220 [(set FPRegs:$dst, (undef))]>; 221def IMPLICIT_DEF_DFP : Pseudo<(outs DFPRegs:$dst), (ins), "!IMPLICIT_DEF $dst", 222 [(set DFPRegs:$dst, (undef))]>; 223} 224 225// FpMOVD/FpNEGD/FpABSD - These are lowered to single-precision ops by the 226// fpmover pass. 227let Predicates = [HasNoV9] in { // Only emit these in V8 mode. 228 def FpMOVD : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$src), 229 "!FpMOVD $src, $dst", []>; 230 def FpNEGD : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$src), 231 "!FpNEGD $src, $dst", 232 [(set DFPRegs:$dst, (fneg DFPRegs:$src))]>; 233 def FpABSD : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$src), 234 "!FpABSD $src, $dst", 235 [(set DFPRegs:$dst, (fabs DFPRegs:$src))]>; 236} 237 238// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded by the 239// scheduler into a branch sequence. This has to handle all permutations of 240// selection between i32/f32/f64 on ICC and FCC. 241let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler. 242 def SELECT_CC_Int_ICC 243 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond), 244 "; SELECT_CC_Int_ICC PSEUDO!", 245 [(set IntRegs:$dst, (SPselecticc IntRegs:$T, IntRegs:$F, 246 imm:$Cond))]>; 247 def SELECT_CC_Int_FCC 248 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond), 249 "; SELECT_CC_Int_FCC PSEUDO!", 250 [(set IntRegs:$dst, (SPselectfcc IntRegs:$T, IntRegs:$F, 251 imm:$Cond))]>; 252 def SELECT_CC_FP_ICC 253 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, i32imm:$Cond), 254 "; SELECT_CC_FP_ICC PSEUDO!", 255 [(set FPRegs:$dst, (SPselecticc FPRegs:$T, FPRegs:$F, 256 imm:$Cond))]>; 257 def SELECT_CC_FP_FCC 258 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, i32imm:$Cond), 259 "; SELECT_CC_FP_FCC PSEUDO!", 260 [(set FPRegs:$dst, (SPselectfcc FPRegs:$T, FPRegs:$F, 261 imm:$Cond))]>; 262 def SELECT_CC_DFP_ICC 263 : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, i32imm:$Cond), 264 "; SELECT_CC_DFP_ICC PSEUDO!", 265 [(set DFPRegs:$dst, (SPselecticc DFPRegs:$T, DFPRegs:$F, 266 imm:$Cond))]>; 267 def SELECT_CC_DFP_FCC 268 : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, i32imm:$Cond), 269 "; SELECT_CC_DFP_FCC PSEUDO!", 270 [(set DFPRegs:$dst, (SPselectfcc DFPRegs:$T, DFPRegs:$F, 271 imm:$Cond))]>; 272} 273 274 275// Section A.3 - Synthetic Instructions, p. 85 276// special cases of JMPL: 277let isReturn = 1, isTerminator = 1, hasDelaySlot = 1 in { 278 let rd = O7.Num, rs1 = G0.Num, simm13 = 8 in 279 def RETL: F3_2<2, 0b111000, (outs), (ins), "retl", [(retflag)]>; 280} 281 282// Section B.1 - Load Integer Instructions, p. 90 283def LDSBrr : F3_1<3, 0b001001, 284 (outs IntRegs:$dst), (ins MEMrr:$addr), 285 "ldsb [$addr], $dst", 286 [(set IntRegs:$dst, (sextloadi8 ADDRrr:$addr))]>; 287def LDSBri : F3_2<3, 0b001001, 288 (outs IntRegs:$dst), (ins MEMri:$addr), 289 "ldsb [$addr], $dst", 290 [(set IntRegs:$dst, (sextloadi8 ADDRri:$addr))]>; 291def LDSHrr : F3_1<3, 0b001010, 292 (outs IntRegs:$dst), (ins MEMrr:$addr), 293 "ldsh [$addr], $dst", 294 [(set IntRegs:$dst, (sextloadi16 ADDRrr:$addr))]>; 295def LDSHri : F3_2<3, 0b001010, 296 (outs IntRegs:$dst), (ins MEMri:$addr), 297 "ldsh [$addr], $dst", 298 [(set IntRegs:$dst, (sextloadi16 ADDRri:$addr))]>; 299def LDUBrr : F3_1<3, 0b000001, 300 (outs IntRegs:$dst), (ins MEMrr:$addr), 301 "ldub [$addr], $dst", 302 [(set IntRegs:$dst, (zextloadi8 ADDRrr:$addr))]>; 303def LDUBri : F3_2<3, 0b000001, 304 (outs IntRegs:$dst), (ins MEMri:$addr), 305 "ldub [$addr], $dst", 306 [(set IntRegs:$dst, (zextloadi8 ADDRri:$addr))]>; 307def LDUHrr : F3_1<3, 0b000010, 308 (outs IntRegs:$dst), (ins MEMrr:$addr), 309 "lduh [$addr], $dst", 310 [(set IntRegs:$dst, (zextloadi16 ADDRrr:$addr))]>; 311def LDUHri : F3_2<3, 0b000010, 312 (outs IntRegs:$dst), (ins MEMri:$addr), 313 "lduh [$addr], $dst", 314 [(set IntRegs:$dst, (zextloadi16 ADDRri:$addr))]>; 315def LDrr : F3_1<3, 0b000000, 316 (outs IntRegs:$dst), (ins MEMrr:$addr), 317 "ld [$addr], $dst", 318 [(set IntRegs:$dst, (load ADDRrr:$addr))]>; 319def LDri : F3_2<3, 0b000000, 320 (outs IntRegs:$dst), (ins MEMri:$addr), 321 "ld [$addr], $dst", 322 [(set IntRegs:$dst, (load ADDRri:$addr))]>; 323 324// Section B.2 - Load Floating-point Instructions, p. 92 325def LDFrr : F3_1<3, 0b100000, 326 (outs FPRegs:$dst), (ins MEMrr:$addr), 327 "ld [$addr], $dst", 328 [(set FPRegs:$dst, (load ADDRrr:$addr))]>; 329def LDFri : F3_2<3, 0b100000, 330 (outs FPRegs:$dst), (ins MEMri:$addr), 331 "ld [$addr], $dst", 332 [(set FPRegs:$dst, (load ADDRri:$addr))]>; 333def LDDFrr : F3_1<3, 0b100011, 334 (outs DFPRegs:$dst), (ins MEMrr:$addr), 335 "ldd [$addr], $dst", 336 [(set DFPRegs:$dst, (load ADDRrr:$addr))]>; 337def LDDFri : F3_2<3, 0b100011, 338 (outs DFPRegs:$dst), (ins MEMri:$addr), 339 "ldd [$addr], $dst", 340 [(set DFPRegs:$dst, (load ADDRri:$addr))]>; 341 342// Section B.4 - Store Integer Instructions, p. 95 343def STBrr : F3_1<3, 0b000101, 344 (outs), (ins MEMrr:$addr, IntRegs:$src), 345 "stb $src, [$addr]", 346 [(truncstorei8 IntRegs:$src, ADDRrr:$addr)]>; 347def STBri : F3_2<3, 0b000101, 348 (outs), (ins MEMri:$addr, IntRegs:$src), 349 "stb $src, [$addr]", 350 [(truncstorei8 IntRegs:$src, ADDRri:$addr)]>; 351def STHrr : F3_1<3, 0b000110, 352 (outs), (ins MEMrr:$addr, IntRegs:$src), 353 "sth $src, [$addr]", 354 [(truncstorei16 IntRegs:$src, ADDRrr:$addr)]>; 355def STHri : F3_2<3, 0b000110, 356 (outs), (ins MEMri:$addr, IntRegs:$src), 357 "sth $src, [$addr]", 358 [(truncstorei16 IntRegs:$src, ADDRri:$addr)]>; 359def STrr : F3_1<3, 0b000100, 360 (outs), (ins MEMrr:$addr, IntRegs:$src), 361 "st $src, [$addr]", 362 [(store IntRegs:$src, ADDRrr:$addr)]>; 363def STri : F3_2<3, 0b000100, 364 (outs), (ins MEMri:$addr, IntRegs:$src), 365 "st $src, [$addr]", 366 [(store IntRegs:$src, ADDRri:$addr)]>; 367 368// Section B.5 - Store Floating-point Instructions, p. 97 369def STFrr : F3_1<3, 0b100100, 370 (outs), (ins MEMrr:$addr, FPRegs:$src), 371 "st $src, [$addr]", 372 [(store FPRegs:$src, ADDRrr:$addr)]>; 373def STFri : F3_2<3, 0b100100, 374 (outs), (ins MEMri:$addr, FPRegs:$src), 375 "st $src, [$addr]", 376 [(store FPRegs:$src, ADDRri:$addr)]>; 377def STDFrr : F3_1<3, 0b100111, 378 (outs), (ins MEMrr:$addr, DFPRegs:$src), 379 "std $src, [$addr]", 380 [(store DFPRegs:$src, ADDRrr:$addr)]>; 381def STDFri : F3_2<3, 0b100111, 382 (outs), (ins MEMri:$addr, DFPRegs:$src), 383 "std $src, [$addr]", 384 [(store DFPRegs:$src, ADDRri:$addr)]>; 385 386// Section B.9 - SETHI Instruction, p. 104 387def SETHIi: F2_1<0b100, 388 (outs IntRegs:$dst), (ins i32imm:$src), 389 "sethi $src, $dst", 390 [(set IntRegs:$dst, SETHIimm:$src)]>; 391 392// Section B.10 - NOP Instruction, p. 105 393// (It's a special case of SETHI) 394let rd = 0, imm22 = 0 in 395 def NOP : F2_1<0b100, (outs), (ins), "nop", []>; 396 397// Section B.11 - Logical Instructions, p. 106 398defm AND : F3_12<"and", 0b000001, and>; 399 400def ANDNrr : F3_1<2, 0b000101, 401 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c), 402 "andn $b, $c, $dst", 403 [(set IntRegs:$dst, (and IntRegs:$b, (not IntRegs:$c)))]>; 404def ANDNri : F3_2<2, 0b000101, 405 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c), 406 "andn $b, $c, $dst", []>; 407 408defm OR : F3_12<"or", 0b000010, or>; 409 410def ORNrr : F3_1<2, 0b000110, 411 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c), 412 "orn $b, $c, $dst", 413 [(set IntRegs:$dst, (or IntRegs:$b, (not IntRegs:$c)))]>; 414def ORNri : F3_2<2, 0b000110, 415 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c), 416 "orn $b, $c, $dst", []>; 417defm XOR : F3_12<"xor", 0b000011, xor>; 418 419def XNORrr : F3_1<2, 0b000111, 420 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c), 421 "xnor $b, $c, $dst", 422 [(set IntRegs:$dst, (not (xor IntRegs:$b, IntRegs:$c)))]>; 423def XNORri : F3_2<2, 0b000111, 424 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c), 425 "xnor $b, $c, $dst", []>; 426 427// Section B.12 - Shift Instructions, p. 107 428defm SLL : F3_12<"sll", 0b100101, shl>; 429defm SRL : F3_12<"srl", 0b100110, srl>; 430defm SRA : F3_12<"sra", 0b100111, sra>; 431 432// Section B.13 - Add Instructions, p. 108 433defm ADD : F3_12<"add", 0b000000, add>; 434 435// "LEA" forms of add (patterns to make tblgen happy) 436def LEA_ADDri : F3_2<2, 0b000000, 437 (outs IntRegs:$dst), (ins MEMri:$addr), 438 "add ${addr:arith}, $dst", 439 [(set IntRegs:$dst, ADDRri:$addr)]>; 440 441defm ADDCC : F3_12<"addcc", 0b010000, addc>; 442defm ADDX : F3_12<"addx", 0b001000, adde>; 443 444// Section B.15 - Subtract Instructions, p. 110 445defm SUB : F3_12 <"sub" , 0b000100, sub>; 446defm SUBX : F3_12 <"subx" , 0b001100, sube>; 447defm SUBCC : F3_12 <"subcc", 0b010100, SPcmpicc>; 448 449def SUBXCCrr: F3_1<2, 0b011100, 450 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c), 451 "subxcc $b, $c, $dst", []>; 452 453// Section B.18 - Multiply Instructions, p. 113 454defm UMUL : F3_12np<"umul", 0b001010>; 455defm SMUL : F3_12 <"smul", 0b001011, mul>; 456 457 458// Section B.19 - Divide Instructions, p. 115 459defm UDIV : F3_12np<"udiv", 0b001110>; 460defm SDIV : F3_12np<"sdiv", 0b001111>; 461 462// Section B.20 - SAVE and RESTORE, p. 117 463defm SAVE : F3_12np<"save" , 0b111100>; 464defm RESTORE : F3_12np<"restore", 0b111101>; 465 466// Section B.21 - Branch on Integer Condition Codes Instructions, p. 119 467 468// conditional branch class: 469class BranchSP<bits<4> cc, dag ins, string asmstr, list<dag> pattern> 470 : F2_2<cc, 0b010, (outs), ins, asmstr, pattern> { 471 let isBranch = 1; 472 let isTerminator = 1; 473 let hasDelaySlot = 1; 474} 475 476let isBarrier = 1 in 477 def BA : BranchSP<0b1000, (ins brtarget:$dst), 478 "ba $dst", 479 [(br bb:$dst)]>; 480 481// FIXME: the encoding for the JIT should look at the condition field. 482def BCOND : BranchSP<0, (ins brtarget:$dst, CCOp:$cc), 483 "b$cc $dst", 484 [(SPbricc bb:$dst, imm:$cc)]>; 485 486 487// Section B.22 - Branch on Floating-point Condition Codes Instructions, p. 121 488 489// floating-point conditional branch class: 490class FPBranchSP<bits<4> cc, dag ins, string asmstr, list<dag> pattern> 491 : F2_2<cc, 0b110, (outs), ins, asmstr, pattern> { 492 let isBranch = 1; 493 let isTerminator = 1; 494 let hasDelaySlot = 1; 495} 496 497// FIXME: the encoding for the JIT should look at the condition field. 498def FBCOND : FPBranchSP<0, (ins brtarget:$dst, CCOp:$cc), 499 "fb$cc $dst", 500 [(SPbrfcc bb:$dst, imm:$cc)]>; 501 502 503// Section B.24 - Call and Link Instruction, p. 125 504// This is the only Format 1 instruction 505let Uses = [O0, O1, O2, O3, O4, O5], 506 hasDelaySlot = 1, isCall = 1, 507 Defs = [O0, O1, O2, O3, O4, O5, O7, G1, G2, G3, G4, G5, G6, G7, 508 D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15] in { 509 def CALL : InstSP<(outs), (ins calltarget:$dst), 510 "call $dst", []> { 511 bits<30> disp; 512 let op = 1; 513 let Inst{29-0} = disp; 514 } 515 516 // indirect calls 517 def JMPLrr : F3_1<2, 0b111000, 518 (outs), (ins MEMrr:$ptr), 519 "call $ptr", 520 [(call ADDRrr:$ptr)]>; 521 def JMPLri : F3_2<2, 0b111000, 522 (outs), (ins MEMri:$ptr), 523 "call $ptr", 524 [(call ADDRri:$ptr)]>; 525} 526 527// Section B.28 - Read State Register Instructions 528def RDY : F3_1<2, 0b101000, 529 (outs IntRegs:$dst), (ins), 530 "rd %y, $dst", []>; 531 532// Section B.29 - Write State Register Instructions 533def WRYrr : F3_1<2, 0b110000, 534 (outs), (ins IntRegs:$b, IntRegs:$c), 535 "wr $b, $c, %y", []>; 536def WRYri : F3_2<2, 0b110000, 537 (outs), (ins IntRegs:$b, i32imm:$c), 538 "wr $b, $c, %y", []>; 539 540// Convert Integer to Floating-point Instructions, p. 141 541def FITOS : F3_3<2, 0b110100, 0b011000100, 542 (outs FPRegs:$dst), (ins FPRegs:$src), 543 "fitos $src, $dst", 544 [(set FPRegs:$dst, (SPitof FPRegs:$src))]>; 545def FITOD : F3_3<2, 0b110100, 0b011001000, 546 (outs DFPRegs:$dst), (ins FPRegs:$src), 547 "fitod $src, $dst", 548 [(set DFPRegs:$dst, (SPitof FPRegs:$src))]>; 549 550// Convert Floating-point to Integer Instructions, p. 142 551def FSTOI : F3_3<2, 0b110100, 0b011010001, 552 (outs FPRegs:$dst), (ins FPRegs:$src), 553 "fstoi $src, $dst", 554 [(set FPRegs:$dst, (SPftoi FPRegs:$src))]>; 555def FDTOI : F3_3<2, 0b110100, 0b011010010, 556 (outs FPRegs:$dst), (ins DFPRegs:$src), 557 "fdtoi $src, $dst", 558 [(set FPRegs:$dst, (SPftoi DFPRegs:$src))]>; 559 560// Convert between Floating-point Formats Instructions, p. 143 561def FSTOD : F3_3<2, 0b110100, 0b011001001, 562 (outs DFPRegs:$dst), (ins FPRegs:$src), 563 "fstod $src, $dst", 564 [(set DFPRegs:$dst, (fextend FPRegs:$src))]>; 565def FDTOS : F3_3<2, 0b110100, 0b011000110, 566 (outs FPRegs:$dst), (ins DFPRegs:$src), 567 "fdtos $src, $dst", 568 [(set FPRegs:$dst, (fround DFPRegs:$src))]>; 569 570// Floating-point Move Instructions, p. 144 571def FMOVS : F3_3<2, 0b110100, 0b000000001, 572 (outs FPRegs:$dst), (ins FPRegs:$src), 573 "fmovs $src, $dst", []>; 574def FNEGS : F3_3<2, 0b110100, 0b000000101, 575 (outs FPRegs:$dst), (ins FPRegs:$src), 576 "fnegs $src, $dst", 577 [(set FPRegs:$dst, (fneg FPRegs:$src))]>; 578def FABSS : F3_3<2, 0b110100, 0b000001001, 579 (outs FPRegs:$dst), (ins FPRegs:$src), 580 "fabss $src, $dst", 581 [(set FPRegs:$dst, (fabs FPRegs:$src))]>; 582 583 584// Floating-point Square Root Instructions, p.145 585def FSQRTS : F3_3<2, 0b110100, 0b000101001, 586 (outs FPRegs:$dst), (ins FPRegs:$src), 587 "fsqrts $src, $dst", 588 [(set FPRegs:$dst, (fsqrt FPRegs:$src))]>; 589def FSQRTD : F3_3<2, 0b110100, 0b000101010, 590 (outs DFPRegs:$dst), (ins DFPRegs:$src), 591 "fsqrtd $src, $dst", 592 [(set DFPRegs:$dst, (fsqrt DFPRegs:$src))]>; 593 594 595 596// Floating-point Add and Subtract Instructions, p. 146 597def FADDS : F3_3<2, 0b110100, 0b001000001, 598 (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2), 599 "fadds $src1, $src2, $dst", 600 [(set FPRegs:$dst, (fadd FPRegs:$src1, FPRegs:$src2))]>; 601def FADDD : F3_3<2, 0b110100, 0b001000010, 602 (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2), 603 "faddd $src1, $src2, $dst", 604 [(set DFPRegs:$dst, (fadd DFPRegs:$src1, DFPRegs:$src2))]>; 605def FSUBS : F3_3<2, 0b110100, 0b001000101, 606 (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2), 607 "fsubs $src1, $src2, $dst", 608 [(set FPRegs:$dst, (fsub FPRegs:$src1, FPRegs:$src2))]>; 609def FSUBD : F3_3<2, 0b110100, 0b001000110, 610 (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2), 611 "fsubd $src1, $src2, $dst", 612 [(set DFPRegs:$dst, (fsub DFPRegs:$src1, DFPRegs:$src2))]>; 613 614// Floating-point Multiply and Divide Instructions, p. 147 615def FMULS : F3_3<2, 0b110100, 0b001001001, 616 (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2), 617 "fmuls $src1, $src2, $dst", 618 [(set FPRegs:$dst, (fmul FPRegs:$src1, FPRegs:$src2))]>; 619def FMULD : F3_3<2, 0b110100, 0b001001010, 620 (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2), 621 "fmuld $src1, $src2, $dst", 622 [(set DFPRegs:$dst, (fmul DFPRegs:$src1, DFPRegs:$src2))]>; 623def FSMULD : F3_3<2, 0b110100, 0b001101001, 624 (outs DFPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2), 625 "fsmuld $src1, $src2, $dst", 626 [(set DFPRegs:$dst, (fmul (fextend FPRegs:$src1), 627 (fextend FPRegs:$src2)))]>; 628def FDIVS : F3_3<2, 0b110100, 0b001001101, 629 (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2), 630 "fdivs $src1, $src2, $dst", 631 [(set FPRegs:$dst, (fdiv FPRegs:$src1, FPRegs:$src2))]>; 632def FDIVD : F3_3<2, 0b110100, 0b001001110, 633 (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2), 634 "fdivd $src1, $src2, $dst", 635 [(set DFPRegs:$dst, (fdiv DFPRegs:$src1, DFPRegs:$src2))]>; 636 637// Floating-point Compare Instructions, p. 148 638// Note: the 2nd template arg is different for these guys. 639// Note 2: the result of a FCMP is not available until the 2nd cycle 640// after the instr is retired, but there is no interlock. This behavior 641// is modelled with a forced noop after the instruction. 642def FCMPS : F3_3<2, 0b110101, 0b001010001, 643 (outs), (ins FPRegs:$src1, FPRegs:$src2), 644 "fcmps $src1, $src2\n\tnop", 645 [(SPcmpfcc FPRegs:$src1, FPRegs:$src2)]>; 646def FCMPD : F3_3<2, 0b110101, 0b001010010, 647 (outs), (ins DFPRegs:$src1, DFPRegs:$src2), 648 "fcmpd $src1, $src2\n\tnop", 649 [(SPcmpfcc DFPRegs:$src1, DFPRegs:$src2)]>; 650 651 652//===----------------------------------------------------------------------===// 653// V9 Instructions 654//===----------------------------------------------------------------------===// 655 656// V9 Conditional Moves. 657let Predicates = [HasV9], isTwoAddress = 1 in { 658 // Move Integer Register on Condition (MOVcc) p. 194 of the V9 manual. 659 // FIXME: Add instruction encodings for the JIT some day. 660 def MOVICCrr 661 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, CCOp:$cc), 662 "mov$cc %icc, $F, $dst", 663 [(set IntRegs:$dst, 664 (SPselecticc IntRegs:$F, IntRegs:$T, imm:$cc))]>; 665 def MOVICCri 666 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, i32imm:$F, CCOp:$cc), 667 "mov$cc %icc, $F, $dst", 668 [(set IntRegs:$dst, 669 (SPselecticc simm11:$F, IntRegs:$T, imm:$cc))]>; 670 671 def MOVFCCrr 672 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, CCOp:$cc), 673 "mov$cc %fcc0, $F, $dst", 674 [(set IntRegs:$dst, 675 (SPselectfcc IntRegs:$F, IntRegs:$T, imm:$cc))]>; 676 def MOVFCCri 677 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, i32imm:$F, CCOp:$cc), 678 "mov$cc %fcc0, $F, $dst", 679 [(set IntRegs:$dst, 680 (SPselectfcc simm11:$F, IntRegs:$T, imm:$cc))]>; 681 682 def FMOVS_ICC 683 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, CCOp:$cc), 684 "fmovs$cc %icc, $F, $dst", 685 [(set FPRegs:$dst, 686 (SPselecticc FPRegs:$F, FPRegs:$T, imm:$cc))]>; 687 def FMOVD_ICC 688 : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, CCOp:$cc), 689 "fmovd$cc %icc, $F, $dst", 690 [(set DFPRegs:$dst, 691 (SPselecticc DFPRegs:$F, DFPRegs:$T, imm:$cc))]>; 692 def FMOVS_FCC 693 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, CCOp:$cc), 694 "fmovs$cc %fcc0, $F, $dst", 695 [(set FPRegs:$dst, 696 (SPselectfcc FPRegs:$F, FPRegs:$T, imm:$cc))]>; 697 def FMOVD_FCC 698 : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, CCOp:$cc), 699 "fmovd$cc %fcc0, $F, $dst", 700 [(set DFPRegs:$dst, 701 (SPselectfcc DFPRegs:$F, DFPRegs:$T, imm:$cc))]>; 702 703} 704 705// Floating-Point Move Instructions, p. 164 of the V9 manual. 706let Predicates = [HasV9] in { 707 def FMOVD : F3_3<2, 0b110100, 0b000000010, 708 (outs DFPRegs:$dst), (ins DFPRegs:$src), 709 "fmovd $src, $dst", []>; 710 def FNEGD : F3_3<2, 0b110100, 0b000000110, 711 (outs DFPRegs:$dst), (ins DFPRegs:$src), 712 "fnegd $src, $dst", 713 [(set DFPRegs:$dst, (fneg DFPRegs:$src))]>; 714 def FABSD : F3_3<2, 0b110100, 0b000001010, 715 (outs DFPRegs:$dst), (ins DFPRegs:$src), 716 "fabsd $src, $dst", 717 [(set DFPRegs:$dst, (fabs DFPRegs:$src))]>; 718} 719 720// POPCrr - This does a ctpop of a 64-bit register. As such, we have to clear 721// the top 32-bits before using it. To do this clearing, we use a SLLri X,0. 722def POPCrr : F3_1<2, 0b101110, 723 (outs IntRegs:$dst), (ins IntRegs:$src), 724 "popc $src, $dst", []>, Requires<[HasV9]>; 725def : Pat<(ctpop IntRegs:$src), 726 (POPCrr (SLLri IntRegs:$src, 0))>; 727 728//===----------------------------------------------------------------------===// 729// Non-Instruction Patterns 730//===----------------------------------------------------------------------===// 731 732// Small immediates. 733def : Pat<(i32 simm13:$val), 734 (ORri G0, imm:$val)>; 735// Arbitrary immediates. 736def : Pat<(i32 imm:$val), 737 (ORri (SETHIi (HI22 imm:$val)), (LO10 imm:$val))>; 738 739// subc 740def : Pat<(subc IntRegs:$b, IntRegs:$c), 741 (SUBCCrr IntRegs:$b, IntRegs:$c)>; 742def : Pat<(subc IntRegs:$b, simm13:$val), 743 (SUBCCri IntRegs:$b, imm:$val)>; 744 745// Global addresses, constant pool entries 746def : Pat<(SPhi tglobaladdr:$in), (SETHIi tglobaladdr:$in)>; 747def : Pat<(SPlo tglobaladdr:$in), (ORri G0, tglobaladdr:$in)>; 748def : Pat<(SPhi tconstpool:$in), (SETHIi tconstpool:$in)>; 749def : Pat<(SPlo tconstpool:$in), (ORri G0, tconstpool:$in)>; 750 751// Add reg, lo. This is used when taking the addr of a global/constpool entry. 752def : Pat<(add IntRegs:$r, (SPlo tglobaladdr:$in)), 753 (ADDri IntRegs:$r, tglobaladdr:$in)>; 754def : Pat<(add IntRegs:$r, (SPlo tconstpool:$in)), 755 (ADDri IntRegs:$r, tconstpool:$in)>; 756 757// Calls: 758def : Pat<(call tglobaladdr:$dst), 759 (CALL tglobaladdr:$dst)>; 760def : Pat<(call texternalsym:$dst), 761 (CALL texternalsym:$dst)>; 762 763def : Pat<(ret), (RETL)>; 764 765// Map integer extload's to zextloads. 766def : Pat<(i32 (extloadi1 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>; 767def : Pat<(i32 (extloadi1 ADDRri:$src)), (LDUBri ADDRri:$src)>; 768def : Pat<(i32 (extloadi8 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>; 769def : Pat<(i32 (extloadi8 ADDRri:$src)), (LDUBri ADDRri:$src)>; 770def : Pat<(i32 (extloadi16 ADDRrr:$src)), (LDUHrr ADDRrr:$src)>; 771def : Pat<(i32 (extloadi16 ADDRri:$src)), (LDUHri ADDRri:$src)>; 772 773// zextload bool -> zextload byte 774def : Pat<(i32 (zextloadi1 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>; 775def : Pat<(i32 (zextloadi1 ADDRri:$src)), (LDUBri ADDRri:$src)>; 776