SparcInstrInfo.td revision 749d6fadf8ac410bb4083a3467ea9f0429c30455
1//===- SparcV8Instrs.td - Target Description for SparcV8 Target -----------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the SparcV8 instructions in TableGen format. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// Instruction format superclass 16//===----------------------------------------------------------------------===// 17 18include "SparcV8InstrFormats.td" 19 20//===----------------------------------------------------------------------===// 21// Feature predicates. 22//===----------------------------------------------------------------------===// 23 24// HasV9 - This predicate is true when the target processor supports V9 25// instructions. Note that the machine may be running in 32-bit mode. 26def HasV9 : Predicate<"Subtarget.isV9()">; 27 28// HasNoV9 - This predicate is true when the target doesn't have V9 29// instructions. Use of this is just a hack for the isel not having proper 30// costs for V8 instructions that are more expensive than their V9 ones. 31def HasNoV9 : Predicate<"!Subtarget.isV9()">; 32 33// HasVIS - This is true when the target processor has VIS extensions. 34def HasVIS : Predicate<"Subtarget.isVIS()">; 35 36// UseDeprecatedInsts - This predicate is true when the target processor is a 37// V8, or when it is V9 but the V8 deprecated instructions are efficient enough 38// to use when appropriate. In either of these cases, the instruction selector 39// will pick deprecated instructions. 40def UseDeprecatedInsts : Predicate<"Subtarget.useDeprecatedV8Instructions()">; 41 42//===----------------------------------------------------------------------===// 43// Instruction Pattern Stuff 44//===----------------------------------------------------------------------===// 45 46def simm11 : PatLeaf<(imm), [{ 47 // simm11 predicate - True if the imm fits in a 11-bit sign extended field. 48 return (((int)N->getValue() << (32-11)) >> (32-11)) == (int)N->getValue(); 49}]>; 50 51def simm13 : PatLeaf<(imm), [{ 52 // simm13 predicate - True if the imm fits in a 13-bit sign extended field. 53 return (((int)N->getValue() << (32-13)) >> (32-13)) == (int)N->getValue(); 54}]>; 55 56def LO10 : SDNodeXForm<imm, [{ 57 return CurDAG->getTargetConstant((unsigned)N->getValue() & 1023, MVT::i32); 58}]>; 59 60def HI22 : SDNodeXForm<imm, [{ 61 // Transformation function: shift the immediate value down into the low bits. 62 return CurDAG->getTargetConstant((unsigned)N->getValue() >> 10, MVT::i32); 63}]>; 64 65def SETHIimm : PatLeaf<(imm), [{ 66 return (((unsigned)N->getValue() >> 10) << 10) == (unsigned)N->getValue(); 67}], HI22>; 68 69// Addressing modes. 70def ADDRrr : ComplexPattern<i32, 2, "SelectADDRrr", []>; 71def ADDRri : ComplexPattern<i32, 2, "SelectADDRri", []>; 72 73// Address operands 74def MEMrr : Operand<i32> { 75 let PrintMethod = "printMemOperand"; 76 let NumMIOperands = 2; 77 let MIOperandInfo = (ops IntRegs, IntRegs); 78} 79def MEMri : Operand<i32> { 80 let PrintMethod = "printMemOperand"; 81 let NumMIOperands = 2; 82 let MIOperandInfo = (ops IntRegs, i32imm); 83} 84 85// Branch targets have OtherVT type. 86def brtarget : Operand<OtherVT>; 87def calltarget : Operand<i32>; 88 89def SDTV8cmpfcc : 90SDTypeProfile<1, 2, [SDTCisVT<0, FlagVT>, SDTCisFP<1>, SDTCisSameAs<1, 2>]>; 91def SDTV8brcc : 92SDTypeProfile<0, 3, [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>, 93 SDTCisVT<2, FlagVT>]>; 94def SDTV8selectcc : 95SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, 96 SDTCisVT<3, i32>, SDTCisVT<4, FlagVT>]>; 97def SDTV8FTOI : 98SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisFP<1>]>; 99def SDTV8ITOF : 100SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f32>]>; 101 102def V8cmpicc : SDNode<"V8ISD::CMPICC", SDTIntBinOp, [SDNPOutFlag]>; 103def V8cmpfcc : SDNode<"V8ISD::CMPFCC", SDTV8cmpfcc, [SDNPOutFlag]>; 104def V8bricc : SDNode<"V8ISD::BRICC", SDTV8brcc, [SDNPHasChain]>; 105def V8brfcc : SDNode<"V8ISD::BRFCC", SDTV8brcc, [SDNPHasChain]>; 106 107def V8hi : SDNode<"V8ISD::Hi", SDTIntUnaryOp>; 108def V8lo : SDNode<"V8ISD::Lo", SDTIntUnaryOp>; 109 110def V8ftoi : SDNode<"V8ISD::FTOI", SDTV8FTOI>; 111def V8itof : SDNode<"V8ISD::ITOF", SDTV8ITOF>; 112 113def V8selecticc : SDNode<"V8ISD::SELECT_ICC", SDTV8selectcc>; 114def V8selectfcc : SDNode<"V8ISD::SELECT_FCC", SDTV8selectcc>; 115 116// These are target-independent nodes, but have target-specific formats. 117def SDT_V8CallSeq : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>; 118def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_V8CallSeq, [SDNPHasChain]>; 119def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_V8CallSeq, [SDNPHasChain]>; 120 121def SDT_V8Call : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>; 122def call : SDNode<"V8ISD::CALL", SDT_V8Call, 123 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; 124 125def SDT_V8RetFlag : SDTypeProfile<0, 0, []>; 126def retflag : SDNode<"V8ISD::RET_FLAG", SDT_V8RetFlag, 127 [SDNPHasChain, SDNPOptInFlag]>; 128 129//===----------------------------------------------------------------------===// 130// SPARC Flag Conditions 131//===----------------------------------------------------------------------===// 132 133// Note that these values must be kept in sync with the V8CC::CondCode enum 134// values. 135class ICC_VAL<int N> : PatLeaf<(i32 N)> { 136 int ICCVal = N; 137} 138def ICC_NE : ICC_VAL< 9>; // Not Equal 139def ICC_E : ICC_VAL< 1>; // Equal 140def ICC_G : ICC_VAL<10>; // Greater 141def ICC_LE : ICC_VAL< 2>; // Less or Equal 142def ICC_GE : ICC_VAL<11>; // Greater or Equal 143def ICC_L : ICC_VAL< 3>; // Less 144def ICC_GU : ICC_VAL<12>; // Greater Unsigned 145def ICC_LEU : ICC_VAL< 4>; // Less or Equal Unsigned 146def ICC_CC : ICC_VAL<13>; // Carry Clear/Great or Equal Unsigned 147def ICC_CS : ICC_VAL< 5>; // Carry Set/Less Unsigned 148def ICC_POS : ICC_VAL<14>; // Positive 149def ICC_NEG : ICC_VAL< 6>; // Negative 150def ICC_VC : ICC_VAL<15>; // Overflow Clear 151def ICC_VS : ICC_VAL< 7>; // Overflow Set 152 153class FCC_VAL<int N> : PatLeaf<(i32 N)> { 154 int FCCVal = N; 155} 156def FCC_U : FCC_VAL<23>; // Unordered 157def FCC_G : FCC_VAL<22>; // Greater 158def FCC_UG : FCC_VAL<21>; // Unordered or Greater 159def FCC_L : FCC_VAL<20>; // Less 160def FCC_UL : FCC_VAL<19>; // Unordered or Less 161def FCC_LG : FCC_VAL<18>; // Less or Greater 162def FCC_NE : FCC_VAL<17>; // Not Equal 163def FCC_E : FCC_VAL<25>; // Equal 164def FCC_UE : FCC_VAL<24>; // Unordered or Equal 165def FCC_GE : FCC_VAL<25>; // Greater or Equal 166def FCC_UGE : FCC_VAL<26>; // Unordered or Greater or Equal 167def FCC_LE : FCC_VAL<27>; // Less or Equal 168def FCC_ULE : FCC_VAL<28>; // Unordered or Less or Equal 169def FCC_O : FCC_VAL<29>; // Ordered 170 171 172//===----------------------------------------------------------------------===// 173// Instructions 174//===----------------------------------------------------------------------===// 175 176// Pseudo instructions. 177class Pseudo<dag ops, string asmstr, list<dag> pattern> 178 : InstV8<ops, asmstr, pattern>; 179 180def ADJCALLSTACKDOWN : Pseudo<(ops i32imm:$amt), 181 "!ADJCALLSTACKDOWN $amt", 182 [(callseq_start imm:$amt)]>; 183def ADJCALLSTACKUP : Pseudo<(ops i32imm:$amt), 184 "!ADJCALLSTACKUP $amt", 185 [(callseq_end imm:$amt)]>; 186def IMPLICIT_DEF_Int : Pseudo<(ops IntRegs:$dst), 187 "!IMPLICIT_DEF $dst", 188 [(set IntRegs:$dst, (undef))]>; 189def IMPLICIT_DEF_FP : Pseudo<(ops FPRegs:$dst), "!IMPLICIT_DEF $dst", 190 [(set FPRegs:$dst, (undef))]>; 191def IMPLICIT_DEF_DFP : Pseudo<(ops DFPRegs:$dst), "!IMPLICIT_DEF $dst", 192 [(set DFPRegs:$dst, (undef))]>; 193 194// FpMOVD/FpNEGD/FpABSD - These are lowered to single-precision ops by the 195// fpmover pass. 196let Predicates = [HasNoV9] in { // Only emit these in V8 mode. 197 def FpMOVD : Pseudo<(ops DFPRegs:$dst, DFPRegs:$src), 198 "!FpMOVD $src, $dst", []>; 199 def FpNEGD : Pseudo<(ops DFPRegs:$dst, DFPRegs:$src), 200 "!FpNEGD $src, $dst", 201 [(set DFPRegs:$dst, (fneg DFPRegs:$src))]>; 202 def FpABSD : Pseudo<(ops DFPRegs:$dst, DFPRegs:$src), 203 "!FpABSD $src, $dst", 204 [(set DFPRegs:$dst, (fabs DFPRegs:$src))]>; 205} 206 207// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded by the 208// scheduler into a branch sequence. This has to handle all permutations of 209// selection between i32/f32/f64 on ICC and FCC. 210let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler. 211 def SELECT_CC_Int_ICC 212 : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F, i32imm:$Cond), 213 "; SELECT_CC_Int_ICC PSEUDO!", 214 [(set IntRegs:$dst, (V8selecticc IntRegs:$T, IntRegs:$F, 215 imm:$Cond, ICC))]>; 216 def SELECT_CC_Int_FCC 217 : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F, i32imm:$Cond), 218 "; SELECT_CC_Int_FCC PSEUDO!", 219 [(set IntRegs:$dst, (V8selectfcc IntRegs:$T, IntRegs:$F, 220 imm:$Cond, FCC))]>; 221 def SELECT_CC_FP_ICC 222 : Pseudo<(ops FPRegs:$dst, FPRegs:$T, FPRegs:$F, i32imm:$Cond), 223 "; SELECT_CC_FP_ICC PSEUDO!", 224 [(set FPRegs:$dst, (V8selecticc FPRegs:$T, FPRegs:$F, 225 imm:$Cond, ICC))]>; 226 def SELECT_CC_FP_FCC 227 : Pseudo<(ops FPRegs:$dst, FPRegs:$T, FPRegs:$F, i32imm:$Cond), 228 "; SELECT_CC_FP_FCC PSEUDO!", 229 [(set FPRegs:$dst, (V8selectfcc FPRegs:$T, FPRegs:$F, 230 imm:$Cond, FCC))]>; 231 def SELECT_CC_DFP_ICC 232 : Pseudo<(ops DFPRegs:$dst, DFPRegs:$T, DFPRegs:$F, i32imm:$Cond), 233 "; SELECT_CC_DFP_ICC PSEUDO!", 234 [(set DFPRegs:$dst, (V8selecticc DFPRegs:$T, DFPRegs:$F, 235 imm:$Cond, ICC))]>; 236 def SELECT_CC_DFP_FCC 237 : Pseudo<(ops DFPRegs:$dst, DFPRegs:$T, DFPRegs:$F, i32imm:$Cond), 238 "; SELECT_CC_DFP_FCC PSEUDO!", 239 [(set DFPRegs:$dst, (V8selectfcc DFPRegs:$T, DFPRegs:$F, 240 imm:$Cond, FCC))]>; 241} 242 243 244// Section A.3 - Synthetic Instructions, p. 85 245// special cases of JMPL: 246let isReturn = 1, isTerminator = 1, hasDelaySlot = 1, noResults = 1 in { 247 let rd = O7.Num, rs1 = G0.Num, simm13 = 8 in 248 def RETL: F3_2<2, 0b111000, (ops), "retl", [(retflag)]>; 249} 250 251// Section B.1 - Load Integer Instructions, p. 90 252def LDSBrr : F3_1<3, 0b001001, 253 (ops IntRegs:$dst, MEMrr:$addr), 254 "ldsb [$addr], $dst", 255 [(set IntRegs:$dst, (sextload ADDRrr:$addr, i8))]>; 256def LDSBri : F3_2<3, 0b001001, 257 (ops IntRegs:$dst, MEMri:$addr), 258 "ldsb [$addr], $dst", 259 [(set IntRegs:$dst, (sextload ADDRri:$addr, i8))]>; 260def LDSHrr : F3_1<3, 0b001010, 261 (ops IntRegs:$dst, MEMrr:$addr), 262 "ldsh [$addr], $dst", 263 [(set IntRegs:$dst, (sextload ADDRrr:$addr, i16))]>; 264def LDSHri : F3_2<3, 0b001010, 265 (ops IntRegs:$dst, MEMri:$addr), 266 "ldsh [$addr], $dst", 267 [(set IntRegs:$dst, (sextload ADDRri:$addr, i16))]>; 268def LDUBrr : F3_1<3, 0b000001, 269 (ops IntRegs:$dst, MEMrr:$addr), 270 "ldub [$addr], $dst", 271 [(set IntRegs:$dst, (zextload ADDRrr:$addr, i8))]>; 272def LDUBri : F3_2<3, 0b000001, 273 (ops IntRegs:$dst, MEMri:$addr), 274 "ldub [$addr], $dst", 275 [(set IntRegs:$dst, (zextload ADDRri:$addr, i8))]>; 276def LDUHrr : F3_1<3, 0b000010, 277 (ops IntRegs:$dst, MEMrr:$addr), 278 "lduh [$addr], $dst", 279 [(set IntRegs:$dst, (zextload ADDRrr:$addr, i16))]>; 280def LDUHri : F3_2<3, 0b000010, 281 (ops IntRegs:$dst, MEMri:$addr), 282 "lduh [$addr], $dst", 283 [(set IntRegs:$dst, (zextload ADDRri:$addr, i16))]>; 284def LDrr : F3_1<3, 0b000000, 285 (ops IntRegs:$dst, MEMrr:$addr), 286 "ld [$addr], $dst", 287 [(set IntRegs:$dst, (load ADDRrr:$addr))]>; 288def LDri : F3_2<3, 0b000000, 289 (ops IntRegs:$dst, MEMri:$addr), 290 "ld [$addr], $dst", 291 [(set IntRegs:$dst, (load ADDRri:$addr))]>; 292 293// Section B.2 - Load Floating-point Instructions, p. 92 294def LDFrr : F3_1<3, 0b100000, 295 (ops FPRegs:$dst, MEMrr:$addr), 296 "ld [$addr], $dst", 297 [(set FPRegs:$dst, (load ADDRrr:$addr))]>; 298def LDFri : F3_2<3, 0b100000, 299 (ops FPRegs:$dst, MEMri:$addr), 300 "ld [$addr], $dst", 301 [(set FPRegs:$dst, (load ADDRri:$addr))]>; 302def LDDFrr : F3_1<3, 0b100011, 303 (ops DFPRegs:$dst, MEMrr:$addr), 304 "ldd [$addr], $dst", 305 [(set DFPRegs:$dst, (load ADDRrr:$addr))]>; 306def LDDFri : F3_2<3, 0b100011, 307 (ops DFPRegs:$dst, MEMri:$addr), 308 "ldd [$addr], $dst", 309 [(set DFPRegs:$dst, (load ADDRri:$addr))]>; 310 311// Section B.4 - Store Integer Instructions, p. 95 312def STBrr : F3_1<3, 0b000101, 313 (ops MEMrr:$addr, IntRegs:$src), 314 "stb $src, [$addr]", 315 [(truncstore IntRegs:$src, ADDRrr:$addr, i8)]>; 316def STBri : F3_2<3, 0b000101, 317 (ops MEMri:$addr, IntRegs:$src), 318 "stb $src, [$addr]", 319 [(truncstore IntRegs:$src, ADDRri:$addr, i8)]>; 320def STHrr : F3_1<3, 0b000110, 321 (ops MEMrr:$addr, IntRegs:$src), 322 "sth $src, [$addr]", 323 [(truncstore IntRegs:$src, ADDRrr:$addr, i16)]>; 324def STHri : F3_2<3, 0b000110, 325 (ops MEMri:$addr, IntRegs:$src), 326 "sth $src, [$addr]", 327 [(truncstore IntRegs:$src, ADDRri:$addr, i16)]>; 328def STrr : F3_1<3, 0b000100, 329 (ops MEMrr:$addr, IntRegs:$src), 330 "st $src, [$addr]", 331 [(store IntRegs:$src, ADDRrr:$addr)]>; 332def STri : F3_2<3, 0b000100, 333 (ops MEMri:$addr, IntRegs:$src), 334 "st $src, [$addr]", 335 [(store IntRegs:$src, ADDRri:$addr)]>; 336 337// Section B.5 - Store Floating-point Instructions, p. 97 338def STFrr : F3_1<3, 0b100100, 339 (ops MEMrr:$addr, FPRegs:$src), 340 "st $src, [$addr]", 341 [(store FPRegs:$src, ADDRrr:$addr)]>; 342def STFri : F3_2<3, 0b100100, 343 (ops MEMri:$addr, FPRegs:$src), 344 "st $src, [$addr]", 345 [(store FPRegs:$src, ADDRri:$addr)]>; 346def STDFrr : F3_1<3, 0b100111, 347 (ops MEMrr:$addr, DFPRegs:$src), 348 "std $src, [$addr]", 349 [(store DFPRegs:$src, ADDRrr:$addr)]>; 350def STDFri : F3_2<3, 0b100111, 351 (ops MEMri:$addr, DFPRegs:$src), 352 "std $src, [$addr]", 353 [(store DFPRegs:$src, ADDRri:$addr)]>; 354 355// Section B.9 - SETHI Instruction, p. 104 356def SETHIi: F2_1<0b100, 357 (ops IntRegs:$dst, i32imm:$src), 358 "sethi $src, $dst", 359 [(set IntRegs:$dst, SETHIimm:$src)]>; 360 361// Section B.10 - NOP Instruction, p. 105 362// (It's a special case of SETHI) 363let rd = 0, imm22 = 0 in 364 def NOP : F2_1<0b100, (ops), "nop", []>; 365 366// Section B.11 - Logical Instructions, p. 106 367def ANDrr : F3_1<2, 0b000001, 368 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 369 "and $b, $c, $dst", 370 [(set IntRegs:$dst, (and IntRegs:$b, IntRegs:$c))]>; 371def ANDri : F3_2<2, 0b000001, 372 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 373 "and $b, $c, $dst", 374 [(set IntRegs:$dst, (and IntRegs:$b, simm13:$c))]>; 375def ANDNrr : F3_1<2, 0b000101, 376 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 377 "andn $b, $c, $dst", 378 [(set IntRegs:$dst, (and IntRegs:$b, (not IntRegs:$c)))]>; 379def ANDNri : F3_2<2, 0b000101, 380 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 381 "andn $b, $c, $dst", []>; 382def ORrr : F3_1<2, 0b000010, 383 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 384 "or $b, $c, $dst", 385 [(set IntRegs:$dst, (or IntRegs:$b, IntRegs:$c))]>; 386def ORri : F3_2<2, 0b000010, 387 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 388 "or $b, $c, $dst", 389 [(set IntRegs:$dst, (or IntRegs:$b, simm13:$c))]>; 390def ORNrr : F3_1<2, 0b000110, 391 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 392 "orn $b, $c, $dst", 393 [(set IntRegs:$dst, (or IntRegs:$b, (not IntRegs:$c)))]>; 394def ORNri : F3_2<2, 0b000110, 395 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 396 "orn $b, $c, $dst", []>; 397def XORrr : F3_1<2, 0b000011, 398 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 399 "xor $b, $c, $dst", 400 [(set IntRegs:$dst, (xor IntRegs:$b, IntRegs:$c))]>; 401def XORri : F3_2<2, 0b000011, 402 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 403 "xor $b, $c, $dst", 404 [(set IntRegs:$dst, (xor IntRegs:$b, simm13:$c))]>; 405def XNORrr : F3_1<2, 0b000111, 406 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 407 "xnor $b, $c, $dst", 408 [(set IntRegs:$dst, (not (xor IntRegs:$b, IntRegs:$c)))]>; 409def XNORri : F3_2<2, 0b000111, 410 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 411 "xnor $b, $c, $dst", []>; 412 413// Section B.12 - Shift Instructions, p. 107 414def SLLrr : F3_1<2, 0b100101, 415 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 416 "sll $b, $c, $dst", 417 [(set IntRegs:$dst, (shl IntRegs:$b, IntRegs:$c))]>; 418def SLLri : F3_2<2, 0b100101, 419 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 420 "sll $b, $c, $dst", 421 [(set IntRegs:$dst, (shl IntRegs:$b, simm13:$c))]>; 422def SRLrr : F3_1<2, 0b100110, 423 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 424 "srl $b, $c, $dst", 425 [(set IntRegs:$dst, (srl IntRegs:$b, IntRegs:$c))]>; 426def SRLri : F3_2<2, 0b100110, 427 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 428 "srl $b, $c, $dst", 429 [(set IntRegs:$dst, (srl IntRegs:$b, simm13:$c))]>; 430def SRArr : F3_1<2, 0b100111, 431 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 432 "sra $b, $c, $dst", 433 [(set IntRegs:$dst, (sra IntRegs:$b, IntRegs:$c))]>; 434def SRAri : F3_2<2, 0b100111, 435 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 436 "sra $b, $c, $dst", 437 [(set IntRegs:$dst, (sra IntRegs:$b, simm13:$c))]>; 438 439// Section B.13 - Add Instructions, p. 108 440def ADDrr : F3_1<2, 0b000000, 441 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 442 "add $b, $c, $dst", 443 [(set IntRegs:$dst, (add IntRegs:$b, IntRegs:$c))]>; 444def ADDri : F3_2<2, 0b000000, 445 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 446 "add $b, $c, $dst", 447 [(set IntRegs:$dst, (add IntRegs:$b, simm13:$c))]>; 448def ADDCCrr : F3_1<2, 0b010000, 449 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 450 "addcc $b, $c, $dst", []>; 451def ADDCCri : F3_2<2, 0b010000, 452 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 453 "addcc $b, $c, $dst", []>; 454def ADDXrr : F3_1<2, 0b001000, 455 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 456 "addx $b, $c, $dst", []>; 457def ADDXri : F3_2<2, 0b001000, 458 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 459 "addx $b, $c, $dst", []>; 460 461// Section B.15 - Subtract Instructions, p. 110 462def SUBrr : F3_1<2, 0b000100, 463 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 464 "sub $b, $c, $dst", 465 [(set IntRegs:$dst, (sub IntRegs:$b, IntRegs:$c))]>; 466def SUBri : F3_2<2, 0b000100, 467 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 468 "sub $b, $c, $dst", 469 [(set IntRegs:$dst, (sub IntRegs:$b, simm13:$c))]>; 470def SUBXrr : F3_1<2, 0b001100, 471 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 472 "subx $b, $c, $dst", []>; 473def SUBXri : F3_2<2, 0b001100, 474 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 475 "subx $b, $c, $dst", []>; 476def SUBCCrr : F3_1<2, 0b010100, 477 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 478 "subcc $b, $c, $dst", 479 [(set IntRegs:$dst, (V8cmpicc IntRegs:$b, IntRegs:$c))]>; 480def SUBCCri : F3_2<2, 0b010100, 481 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 482 "subcc $b, $c, $dst", 483 [(set IntRegs:$dst, (V8cmpicc IntRegs:$b, simm13:$c))]>; 484def SUBXCCrr: F3_1<2, 0b011100, 485 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 486 "subxcc $b, $c, $dst", []>; 487 488// Section B.18 - Multiply Instructions, p. 113 489def UMULrr : F3_1<2, 0b001010, 490 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 491 "umul $b, $c, $dst", []>; 492def UMULri : F3_2<2, 0b001010, 493 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 494 "umul $b, $c, $dst", []>; 495def SMULrr : F3_1<2, 0b001011, 496 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 497 "smul $b, $c, $dst", 498 [(set IntRegs:$dst, (mul IntRegs:$b, IntRegs:$c))]>; 499def SMULri : F3_2<2, 0b001011, 500 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 501 "smul $b, $c, $dst", 502 [(set IntRegs:$dst, (mul IntRegs:$b, simm13:$c))]>; 503 504// Section B.19 - Divide Instructions, p. 115 505def UDIVrr : F3_1<2, 0b001110, 506 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 507 "udiv $b, $c, $dst", []>; 508def UDIVri : F3_2<2, 0b001110, 509 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 510 "udiv $b, $c, $dst", []>; 511def SDIVrr : F3_1<2, 0b001111, 512 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 513 "sdiv $b, $c, $dst", []>; 514def SDIVri : F3_2<2, 0b001111, 515 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 516 "sdiv $b, $c, $dst", []>; 517 518// Section B.20 - SAVE and RESTORE, p. 117 519def SAVErr : F3_1<2, 0b111100, 520 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 521 "save $b, $c, $dst", []>; 522def SAVEri : F3_2<2, 0b111100, 523 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 524 "save $b, $c, $dst", []>; 525def RESTORErr : F3_1<2, 0b111101, 526 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 527 "restore $b, $c, $dst", []>; 528def RESTOREri : F3_2<2, 0b111101, 529 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 530 "restore $b, $c, $dst", []>; 531 532// Section B.21 - Branch on Integer Condition Codes Instructions, p. 119 533 534// conditional branch class: 535class BranchV8<bits<4> cc, dag ops, string asmstr, list<dag> pattern> 536 : F2_2<cc, 0b010, ops, asmstr, pattern> { 537 let isBranch = 1; 538 let isTerminator = 1; 539 let hasDelaySlot = 1; 540 let noResults = 1; 541} 542 543let isBarrier = 1 in 544 def BA : BranchV8<0b1000, (ops brtarget:$dst), 545 "ba $dst", 546 [(br bb:$dst)]>; 547def BNE : BranchV8<0b1001, (ops brtarget:$dst), 548 "bne $dst", 549 [(V8bricc bb:$dst, ICC_NE, ICC)]>; 550def BE : BranchV8<0b0001, (ops brtarget:$dst), 551 "be $dst", 552 [(V8bricc bb:$dst, ICC_E, ICC)]>; 553def BG : BranchV8<0b1010, (ops brtarget:$dst), 554 "bg $dst", 555 [(V8bricc bb:$dst, ICC_G, ICC)]>; 556def BLE : BranchV8<0b0010, (ops brtarget:$dst), 557 "ble $dst", 558 [(V8bricc bb:$dst, ICC_LE, ICC)]>; 559def BGE : BranchV8<0b1011, (ops brtarget:$dst), 560 "bge $dst", 561 [(V8bricc bb:$dst, ICC_GE, ICC)]>; 562def BL : BranchV8<0b0011, (ops brtarget:$dst), 563 "bl $dst", 564 [(V8bricc bb:$dst, ICC_L, ICC)]>; 565def BGU : BranchV8<0b1100, (ops brtarget:$dst), 566 "bgu $dst", 567 [(V8bricc bb:$dst, ICC_GU, ICC)]>; 568def BLEU : BranchV8<0b0100, (ops brtarget:$dst), 569 "bleu $dst", 570 [(V8bricc bb:$dst, ICC_LEU, ICC)]>; 571def BCC : BranchV8<0b1101, (ops brtarget:$dst), 572 "bcc $dst", 573 [(V8bricc bb:$dst, ICC_CC, ICC)]>; 574def BCS : BranchV8<0b0101, (ops brtarget:$dst), 575 "bcs $dst", 576 [(V8bricc bb:$dst, ICC_CS, ICC)]>; 577def BPOS : BranchV8<0b1110, (ops brtarget:$dst), 578 "bpos $dst", 579 [(V8bricc bb:$dst, ICC_POS, ICC)]>; 580def BNEG : BranchV8<0b0110, (ops brtarget:$dst), 581 "bneg $dst", 582 [(V8bricc bb:$dst, ICC_NEG, ICC)]>; 583def BVC : BranchV8<0b1111, (ops brtarget:$dst), 584 "bvc $dst", 585 [(V8bricc bb:$dst, ICC_VC, ICC)]>; 586def BVS : BranchV8<0b0111, (ops brtarget:$dst), 587 "bvs $dst", 588 [(V8bricc bb:$dst, ICC_VS, ICC)]>; 589 590 591 592// Section B.22 - Branch on Floating-point Condition Codes Instructions, p. 121 593 594// floating-point conditional branch class: 595class FPBranchV8<bits<4> cc, dag ops, string asmstr, list<dag> pattern> 596 : F2_2<cc, 0b110, ops, asmstr, pattern> { 597 let isBranch = 1; 598 let isTerminator = 1; 599 let hasDelaySlot = 1; 600 let noResults = 1; 601} 602 603def FBU : FPBranchV8<0b0111, (ops brtarget:$dst), 604 "fbu $dst", 605 [(V8brfcc bb:$dst, FCC_U, FCC)]>; 606def FBG : FPBranchV8<0b0110, (ops brtarget:$dst), 607 "fbg $dst", 608 [(V8brfcc bb:$dst, FCC_G, FCC)]>; 609def FBUG : FPBranchV8<0b0101, (ops brtarget:$dst), 610 "fbug $dst", 611 [(V8brfcc bb:$dst, FCC_UG, FCC)]>; 612def FBL : FPBranchV8<0b0100, (ops brtarget:$dst), 613 "fbl $dst", 614 [(V8brfcc bb:$dst, FCC_L, FCC)]>; 615def FBUL : FPBranchV8<0b0011, (ops brtarget:$dst), 616 "fbul $dst", 617 [(V8brfcc bb:$dst, FCC_UL, FCC)]>; 618def FBLG : FPBranchV8<0b0010, (ops brtarget:$dst), 619 "fblg $dst", 620 [(V8brfcc bb:$dst, FCC_LG, FCC)]>; 621def FBNE : FPBranchV8<0b0001, (ops brtarget:$dst), 622 "fbne $dst", 623 [(V8brfcc bb:$dst, FCC_NE, FCC)]>; 624def FBE : FPBranchV8<0b1001, (ops brtarget:$dst), 625 "fbe $dst", 626 [(V8brfcc bb:$dst, FCC_E, FCC)]>; 627def FBUE : FPBranchV8<0b1010, (ops brtarget:$dst), 628 "fbue $dst", 629 [(V8brfcc bb:$dst, FCC_UE, FCC)]>; 630def FBGE : FPBranchV8<0b1011, (ops brtarget:$dst), 631 "fbge $dst", 632 [(V8brfcc bb:$dst, FCC_GE, FCC)]>; 633def FBUGE: FPBranchV8<0b1100, (ops brtarget:$dst), 634 "fbuge $dst", 635 [(V8brfcc bb:$dst, FCC_UGE, FCC)]>; 636def FBLE : FPBranchV8<0b1101, (ops brtarget:$dst), 637 "fble $dst", 638 [(V8brfcc bb:$dst, FCC_LE, FCC)]>; 639def FBULE: FPBranchV8<0b1110, (ops brtarget:$dst), 640 "fbule $dst", 641 [(V8brfcc bb:$dst, FCC_ULE, FCC)]>; 642def FBO : FPBranchV8<0b1111, (ops brtarget:$dst), 643 "fbo $dst", 644 [(V8brfcc bb:$dst, FCC_O, FCC)]>; 645 646 647 648// Section B.24 - Call and Link Instruction, p. 125 649// This is the only Format 1 instruction 650let Uses = [O0, O1, O2, O3, O4, O5], 651 hasDelaySlot = 1, isCall = 1, noResults = 1, 652 Defs = [O0, O1, O2, O3, O4, O5, O7, G1, G2, G3, G4, G5, G6, G7, 653 D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15] in { 654 def CALL : InstV8<(ops calltarget:$dst), 655 "call $dst", []> { 656 bits<30> disp; 657 let op = 1; 658 let Inst{29-0} = disp; 659 } 660 661 // indirect calls 662 def JMPLrr : F3_1<2, 0b111000, 663 (ops MEMrr:$ptr), 664 "call $ptr", 665 [(call ADDRrr:$ptr)]>; 666 def JMPLri : F3_2<2, 0b111000, 667 (ops MEMri:$ptr), 668 "call $ptr", 669 [(call ADDRri:$ptr)]>; 670} 671 672// Section B.28 - Read State Register Instructions 673def RDY : F3_1<2, 0b101000, 674 (ops IntRegs:$dst), 675 "rd %y, $dst", []>; 676 677// Section B.29 - Write State Register Instructions 678def WRYrr : F3_1<2, 0b110000, 679 (ops IntRegs:$b, IntRegs:$c), 680 "wr $b, $c, %y", []>; 681def WRYri : F3_2<2, 0b110000, 682 (ops IntRegs:$b, i32imm:$c), 683 "wr $b, $c, %y", []>; 684 685// Convert Integer to Floating-point Instructions, p. 141 686def FITOS : F3_3<2, 0b110100, 0b011000100, 687 (ops FPRegs:$dst, FPRegs:$src), 688 "fitos $src, $dst", 689 [(set FPRegs:$dst, (V8itof FPRegs:$src))]>; 690def FITOD : F3_3<2, 0b110100, 0b011001000, 691 (ops DFPRegs:$dst, FPRegs:$src), 692 "fitod $src, $dst", 693 [(set DFPRegs:$dst, (V8itof FPRegs:$src))]>; 694 695// Convert Floating-point to Integer Instructions, p. 142 696def FSTOI : F3_3<2, 0b110100, 0b011010001, 697 (ops FPRegs:$dst, FPRegs:$src), 698 "fstoi $src, $dst", 699 [(set FPRegs:$dst, (V8ftoi FPRegs:$src))]>; 700def FDTOI : F3_3<2, 0b110100, 0b011010010, 701 (ops FPRegs:$dst, DFPRegs:$src), 702 "fdtoi $src, $dst", 703 [(set FPRegs:$dst, (V8ftoi DFPRegs:$src))]>; 704 705// Convert between Floating-point Formats Instructions, p. 143 706def FSTOD : F3_3<2, 0b110100, 0b011001001, 707 (ops DFPRegs:$dst, FPRegs:$src), 708 "fstod $src, $dst", 709 [(set DFPRegs:$dst, (fextend FPRegs:$src))]>; 710def FDTOS : F3_3<2, 0b110100, 0b011000110, 711 (ops FPRegs:$dst, DFPRegs:$src), 712 "fdtos $src, $dst", 713 [(set FPRegs:$dst, (fround DFPRegs:$src))]>; 714 715// Floating-point Move Instructions, p. 144 716def FMOVS : F3_3<2, 0b110100, 0b000000001, 717 (ops FPRegs:$dst, FPRegs:$src), 718 "fmovs $src, $dst", []>; 719def FNEGS : F3_3<2, 0b110100, 0b000000101, 720 (ops FPRegs:$dst, FPRegs:$src), 721 "fnegs $src, $dst", 722 [(set FPRegs:$dst, (fneg FPRegs:$src))]>; 723def FABSS : F3_3<2, 0b110100, 0b000001001, 724 (ops FPRegs:$dst, FPRegs:$src), 725 "fabss $src, $dst", 726 [(set FPRegs:$dst, (fabs FPRegs:$src))]>; 727 728 729// Floating-point Square Root Instructions, p.145 730def FSQRTS : F3_3<2, 0b110100, 0b000101001, 731 (ops FPRegs:$dst, FPRegs:$src), 732 "fsqrts $src, $dst", 733 [(set FPRegs:$dst, (fsqrt FPRegs:$src))]>; 734def FSQRTD : F3_3<2, 0b110100, 0b000101010, 735 (ops DFPRegs:$dst, DFPRegs:$src), 736 "fsqrtd $src, $dst", 737 [(set DFPRegs:$dst, (fsqrt DFPRegs:$src))]>; 738 739 740 741// Floating-point Add and Subtract Instructions, p. 146 742def FADDS : F3_3<2, 0b110100, 0b001000001, 743 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2), 744 "fadds $src1, $src2, $dst", 745 [(set FPRegs:$dst, (fadd FPRegs:$src1, FPRegs:$src2))]>; 746def FADDD : F3_3<2, 0b110100, 0b001000010, 747 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2), 748 "faddd $src1, $src2, $dst", 749 [(set DFPRegs:$dst, (fadd DFPRegs:$src1, DFPRegs:$src2))]>; 750def FSUBS : F3_3<2, 0b110100, 0b001000101, 751 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2), 752 "fsubs $src1, $src2, $dst", 753 [(set FPRegs:$dst, (fsub FPRegs:$src1, FPRegs:$src2))]>; 754def FSUBD : F3_3<2, 0b110100, 0b001000110, 755 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2), 756 "fsubd $src1, $src2, $dst", 757 [(set DFPRegs:$dst, (fsub DFPRegs:$src1, DFPRegs:$src2))]>; 758 759// Floating-point Multiply and Divide Instructions, p. 147 760def FMULS : F3_3<2, 0b110100, 0b001001001, 761 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2), 762 "fmuls $src1, $src2, $dst", 763 [(set FPRegs:$dst, (fmul FPRegs:$src1, FPRegs:$src2))]>; 764def FMULD : F3_3<2, 0b110100, 0b001001010, 765 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2), 766 "fmuld $src1, $src2, $dst", 767 [(set DFPRegs:$dst, (fmul DFPRegs:$src1, DFPRegs:$src2))]>; 768def FSMULD : F3_3<2, 0b110100, 0b001101001, 769 (ops DFPRegs:$dst, FPRegs:$src1, FPRegs:$src2), 770 "fsmuld $src1, $src2, $dst", 771 [(set DFPRegs:$dst, (fmul (fextend FPRegs:$src1), 772 (fextend FPRegs:$src2)))]>; 773def FDIVS : F3_3<2, 0b110100, 0b001001101, 774 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2), 775 "fdivs $src1, $src2, $dst", 776 [(set FPRegs:$dst, (fdiv FPRegs:$src1, FPRegs:$src2))]>; 777def FDIVD : F3_3<2, 0b110100, 0b001001110, 778 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2), 779 "fdivd $src1, $src2, $dst", 780 [(set DFPRegs:$dst, (fdiv DFPRegs:$src1, DFPRegs:$src2))]>; 781 782// Floating-point Compare Instructions, p. 148 783// Note: the 2nd template arg is different for these guys. 784// Note 2: the result of a FCMP is not available until the 2nd cycle 785// after the instr is retired, but there is no interlock. This behavior 786// is modelled with a forced noop after the instruction. 787def FCMPS : F3_3<2, 0b110101, 0b001010001, 788 (ops FPRegs:$src1, FPRegs:$src2), 789 "fcmps $src1, $src2\n\tnop", 790 [(set FCC, (V8cmpfcc FPRegs:$src1, FPRegs:$src2))]>; 791def FCMPD : F3_3<2, 0b110101, 0b001010010, 792 (ops DFPRegs:$src1, DFPRegs:$src2), 793 "fcmpd $src1, $src2\n\tnop", 794 [(set FCC, (V8cmpfcc DFPRegs:$src1, DFPRegs:$src2))]>; 795 796 797//===----------------------------------------------------------------------===// 798// V9 Instructions 799//===----------------------------------------------------------------------===// 800 801// V9 Conditional Moves. 802let Predicates = [HasV9], isTwoAddress = 1 in { 803 // FIXME: Add instruction encodings for the JIT some day. 804 class IntCMOVICCrr<string asmstr, ICC_VAL CC> 805 : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F), 806 asmstr, 807 [(set IntRegs:$dst, 808 (V8selecticc IntRegs:$F, IntRegs:$T, CC, ICC))]> { 809 int CondBits = CC.ICCVal; 810 } 811 812 813 // Move Integer Register on Condition (MOVcc) p. 194 of the V9 manual. 814 def MOVNErr : IntCMOVICCrr< "movne %icc, $F, $dst", ICC_NE>; 815 def MOVErr : IntCMOVICCrr< "move %icc, $F, $dst", ICC_E>; 816 def MOVGrr : IntCMOVICCrr< "movg %icc, $F, $dst", ICC_G>; 817 def MOVLErr : IntCMOVICCrr< "movle %icc, $F, $dst", ICC_LE>; 818 def MOVGErr : IntCMOVICCrr< "movge %icc, $F, $dst", ICC_GE>; 819 def MOVLrr : IntCMOVICCrr< "movl %icc, $F, $dst", ICC_L>; 820 def MOVGUrr : IntCMOVICCrr< "movgu %icc, $F, $dst", ICC_GU>; 821 def MOVLEUrr : IntCMOVICCrr<"movleu %icc, $F, $dst", ICC_LEU>; 822 def MOVCCrr : IntCMOVICCrr< "movcc %icc, $F, $dst", ICC_CC>; 823 def MOVCSrr : IntCMOVICCrr< "movcs %icc, $F, $dst", ICC_CS>; 824 def MOVPOSrr : IntCMOVICCrr<"movpos %icc, $F, $dst", ICC_POS>; 825 def MOVNEGrr : IntCMOVICCrr<"movneg %icc, $F, $dst", ICC_NEG>; 826 def MOVVCrr : IntCMOVICCrr< "movvc %icc, $F, $dst", ICC_VC>; 827 def MOVVSrr : IntCMOVICCrr< "movvs %icc, $F, $dst", ICC_VS>; 828 829 // FIXME: Allow regalloc of the fcc condition code some day. 830 class IntCMOVFCCrr<string asmstr, FCC_VAL CC> 831 : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F), 832 asmstr, 833 [(set IntRegs:$dst, 834 (V8selectfcc IntRegs:$F, IntRegs:$T, CC, FCC))]> { 835 int CondBits = CC.FCCVal; 836 } 837 838 def MOVFUrr : IntCMOVFCCrr< "movfu %fcc, $F, $dst", FCC_U>; 839 def MOVFGrr : IntCMOVFCCrr< "movfg %fcc, $F, $dst", FCC_G>; 840 def MOVFUGrr : IntCMOVFCCrr< "movfug %fcc, $F, $dst", FCC_UG>; 841 def MOVFLrr : IntCMOVFCCrr< "movfl %fcc, $F, $dst", FCC_L>; 842 def MOVFULrr : IntCMOVFCCrr< "movful %fcc, $F, $dst", FCC_UL>; 843 def MOVFLGrr : IntCMOVFCCrr< "movflg %fcc, $F, $dst", FCC_LG>; 844 def MOVFNErr : IntCMOVFCCrr< "movfne %fcc, $F, $dst", FCC_NE>; 845 def MOVFErr : IntCMOVFCCrr< "movfe %fcc, $F, $dst", FCC_E>; 846 def MOVFUErr : IntCMOVFCCrr< "movfue %fcc, $F, $dst", FCC_UE>; 847 def MOVFGErr : IntCMOVFCCrr< "movfge %fcc, $F, $dst", FCC_GE>; 848 def MOVFUGErr : IntCMOVFCCrr<"movfuge %fcc, $F, $dst", FCC_UGE>; 849 def MOVFLErr : IntCMOVFCCrr< "movfle %fcc, $F, $dst", FCC_LE>; 850 def MOVFULErr : IntCMOVFCCrr<"movfule %fcc, $F, $dst", FCC_ULE>; 851 def MOVFOrr : IntCMOVFCCrr< "movfo %fcc, $F, $dst", FCC_O>; 852} 853 854// Floating-Point Move Instructions, p. 164 of the V9 manual. 855let Predicates = [HasV9] in { 856 def FMOVD : F3_3<2, 0b110100, 0b000000010, 857 (ops DFPRegs:$dst, DFPRegs:$src), 858 "fmovd $src, $dst", []>; 859 def FNEGD : F3_3<2, 0b110100, 0b000000110, 860 (ops DFPRegs:$dst, DFPRegs:$src), 861 "fnegd $src, $dst", 862 [(set DFPRegs:$dst, (fneg DFPRegs:$src))]>; 863 def FABSD : F3_3<2, 0b110100, 0b000001010, 864 (ops DFPRegs:$dst, DFPRegs:$src), 865 "fabsd $src, $dst", 866 [(set DFPRegs:$dst, (fabs DFPRegs:$src))]>; 867} 868 869// POPCrr - This does a ctpop of a 64-bit register. As such, we have to clear 870// the top 32-bits before using it. To do this clearing, we use a SLLri X,0. 871def POPCrr : F3_1<2, 0b101110, 872 (ops IntRegs:$dst, IntRegs:$src), 873 "popc $src, $dst", []>, Requires<[HasV9]>; 874def : Pat<(ctpop IntRegs:$src), 875 (POPCrr (SLLri IntRegs:$src, 0))>; 876 877//===----------------------------------------------------------------------===// 878// Non-Instruction Patterns 879//===----------------------------------------------------------------------===// 880 881// Small immediates. 882def : Pat<(i32 simm13:$val), 883 (ORri G0, imm:$val)>; 884// Arbitrary immediates. 885def : Pat<(i32 imm:$val), 886 (ORri (SETHIi (HI22 imm:$val)), (LO10 imm:$val))>; 887 888// Global addresses, constant pool entries 889def : Pat<(V8hi tglobaladdr:$in), (SETHIi tglobaladdr:$in)>; 890def : Pat<(V8lo tglobaladdr:$in), (ORri G0, tglobaladdr:$in)>; 891def : Pat<(V8hi tconstpool:$in), (SETHIi tconstpool:$in)>; 892def : Pat<(V8lo tconstpool:$in), (ORri G0, tconstpool:$in)>; 893 894// Add reg, lo. This is used when taking the addr of a global/constpool entry. 895def : Pat<(add IntRegs:$r, (V8lo tglobaladdr:$in)), 896 (ADDri IntRegs:$r, tglobaladdr:$in)>; 897def : Pat<(add IntRegs:$r, (V8lo tconstpool:$in)), 898 (ADDri IntRegs:$r, tconstpool:$in)>; 899 900 901// Calls: 902def : Pat<(call tglobaladdr:$dst), 903 (CALL tglobaladdr:$dst)>; 904def : Pat<(call externalsym:$dst), 905 (CALL externalsym:$dst)>; 906 907def : Pat<(ret), (RETL)>; 908 909// Map integer extload's to zextloads. 910def : Pat<(i32 (extload ADDRrr:$src, i1)), (LDUBrr ADDRrr:$src)>; 911def : Pat<(i32 (extload ADDRri:$src, i1)), (LDUBri ADDRri:$src)>; 912def : Pat<(i32 (extload ADDRrr:$src, i8)), (LDUBrr ADDRrr:$src)>; 913def : Pat<(i32 (extload ADDRri:$src, i8)), (LDUBri ADDRri:$src)>; 914def : Pat<(i32 (extload ADDRrr:$src, i16)), (LDUHrr ADDRrr:$src)>; 915def : Pat<(i32 (extload ADDRri:$src, i16)), (LDUHri ADDRri:$src)>; 916 917// zextload bool -> zextload byte 918def : Pat<(i32 (zextload ADDRrr:$src, i1)), (LDUBrr ADDRrr:$src)>; 919def : Pat<(i32 (zextload ADDRri:$src, i1)), (LDUBri ADDRri:$src)>; 920 921// truncstore bool -> truncstore byte. 922def : Pat<(truncstore IntRegs:$src, ADDRrr:$addr, i1), 923 (STBrr ADDRrr:$addr, IntRegs:$src)>; 924def : Pat<(truncstore IntRegs:$src, ADDRri:$addr, i1), 925 (STBri ADDRri:$addr, IntRegs:$src)>; 926