SparcInstrInfo.td revision 8fa54dc70239dc08cc3c93cb7513e0625be50eb4
1//===- SparcV8Instrs.td - Target Description for SparcV8 Target -----------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the SparcV8 instructions in TableGen format. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// Instruction format superclass 16//===----------------------------------------------------------------------===// 17 18class InstV8 : Instruction { // SparcV8 instruction baseline 19 field bits<32> Inst; 20 21 let Namespace = "V8"; 22 23 bits<2> op; 24 let Inst{31-30} = op; // Top two bits are the 'op' field 25 26 // Bit attributes specific to SparcV8 instructions 27 bit isPasi = 0; // Does this instruction affect an alternate addr space? 28 bit isPrivileged = 0; // Is this a privileged instruction? 29} 30 31include "SparcV8InstrFormats.td" 32 33//===----------------------------------------------------------------------===// 34// Instruction Pattern Stuff 35//===----------------------------------------------------------------------===// 36 37def simm13 : PatLeaf<(imm), [{ 38 // simm13 predicate - True if the imm fits in a 13-bit sign extended field. 39 return (((int)N->getValue() << (32-13)) >> (32-13)) == (int)N->getValue(); 40}]>; 41 42def LO10 : SDNodeXForm<imm, [{ 43 return CurDAG->getTargetConstant((unsigned)N->getValue() & 1023, MVT::i32); 44}]>; 45 46def HI22 : SDNodeXForm<imm, [{ 47 // Transformation function: shift the immediate value down into the low bits. 48 return CurDAG->getTargetConstant((unsigned)N->getValue() >> 10, MVT::i32); 49}]>; 50 51def SETHIimm : PatLeaf<(imm), [{ 52 return (((unsigned)N->getValue() >> 10) << 10) == (unsigned)N->getValue(); 53}], HI22>; 54 55// Addressing modes. 56def ADDRrr : ComplexPattern<i32, 2, "SelectADDRrr", []>; 57def ADDRri : ComplexPattern<i32, 2, "SelectADDRri", []>; 58 59// Address operands 60def MEMrr : Operand<i32> { 61 let PrintMethod = "printMemOperand"; 62 let NumMIOperands = 2; 63 let MIOperandInfo = (ops IntRegs, IntRegs); 64} 65def MEMri : Operand<i32> { 66 let PrintMethod = "printMemOperand"; 67 let NumMIOperands = 2; 68 let MIOperandInfo = (ops IntRegs, i32imm); 69} 70 71// Branch targets have OtherVT type. 72def brtarget : Operand<OtherVT>; 73 74def SDTV8cmpicc : 75SDTypeProfile<1, 2, [SDTCisVT<0, FlagVT>, SDTCisInt<1>, SDTCisSameAs<1, 2>]>; 76def SDTV8cmpfcc : 77SDTypeProfile<1, 2, [SDTCisVT<0, FlagVT>, SDTCisFP<1>, SDTCisSameAs<1, 2>]>; 78def SDTV8brcc : 79SDTypeProfile<0, 3, [SDTCisVT<0, OtherVT>, SDTCisVT<1, OtherVT>, 80 SDTCisVT<2, FlagVT>]>; 81 82def V8cmpicc : SDNode<"V8ISD::CMPICC", SDTV8cmpicc>; 83def V8cmpfcc : SDNode<"V8ISD::CMPFCC", SDTV8cmpfcc>; 84def V8bricc : SDNode<"V8ISD::BRICC", SDTV8brcc, [SDNPHasChain]>; 85def V8brfcc : SDNode<"V8ISD::BRFCC", SDTV8brcc, [SDNPHasChain]>; 86 87def V8hi : SDNode<"V8ISD::Hi", SDTIntUnaryOp>; 88def V8lo : SDNode<"V8ISD::Lo", SDTIntUnaryOp>; 89 90def V8ftoi : SDNode<"V8ISD::FTOI", SDTFPUnaryOp>; 91def V8itof : SDNode<"V8ISD::ITOF", SDTFPUnaryOp>; 92 93//===----------------------------------------------------------------------===// 94// Instructions 95//===----------------------------------------------------------------------===// 96 97// Pseudo instructions. 98class PseudoInstV8<string asmstr, dag ops> : InstV8 { 99 let AsmString = asmstr; 100 dag OperandList = ops; 101} 102def PHI : PseudoInstV8<"PHI", (ops variable_ops)>; 103def ADJCALLSTACKDOWN : PseudoInstV8<"!ADJCALLSTACKDOWN $amt", 104 (ops i32imm:$amt)>; 105def ADJCALLSTACKUP : PseudoInstV8<"!ADJCALLSTACKUP $amt", 106 (ops i32imm:$amt)>; 107//def IMPLICIT_USE : PseudoInstV8<"!IMPLICIT_USE",(ops variable_ops)>; 108def IMPLICIT_DEF : PseudoInstV8<"!IMPLICIT_DEF $dst", 109 (ops IntRegs:$dst)>; 110def FpMOVD : PseudoInstV8<"!FpMOVD", // pseudo 64-bit double move 111 (ops DFPRegs:$dst, DFPRegs:$src)>; 112 113// Section A.3 - Synthetic Instructions, p. 85 114// special cases of JMPL: 115let isReturn = 1, isTerminator = 1, hasDelaySlot = 1 in { 116 let rd = O7.Num, rs1 = G0.Num, simm13 = 8 in 117 def RETL: F3_2<2, 0b111000, (ops), 118 "retl", [(ret)]>; 119} 120 121// Section B.1 - Load Integer Instructions, p. 90 122def LDSBrr : F3_1<3, 0b001001, 123 (ops IntRegs:$dst, MEMrr:$addr), 124 "ldsb [$addr], $dst", 125 [(set IntRegs:$dst, (sextload ADDRrr:$addr, i8))]>; 126def LDSBri : F3_2<3, 0b001001, 127 (ops IntRegs:$dst, MEMri:$addr), 128 "ldsb [$addr], $dst", 129 [(set IntRegs:$dst, (sextload ADDRri:$addr, i8))]>; 130def LDSHrr : F3_1<3, 0b001010, 131 (ops IntRegs:$dst, MEMrr:$addr), 132 "ldsh [$addr], $dst", 133 [(set IntRegs:$dst, (sextload ADDRrr:$addr, i16))]>; 134def LDSHri : F3_2<3, 0b001010, 135 (ops IntRegs:$dst, MEMri:$addr), 136 "ldsh [$addr], $dst", 137 [(set IntRegs:$dst, (sextload ADDRri:$addr, i16))]>; 138def LDUBrr : F3_1<3, 0b000001, 139 (ops IntRegs:$dst, MEMrr:$addr), 140 "ldub [$addr], $dst", 141 [(set IntRegs:$dst, (zextload ADDRrr:$addr, i8))]>; 142def LDUBri : F3_2<3, 0b000001, 143 (ops IntRegs:$dst, MEMri:$addr), 144 "ldub [$addr], $dst", 145 [(set IntRegs:$dst, (zextload ADDRri:$addr, i8))]>; 146def LDUHrr : F3_1<3, 0b000010, 147 (ops IntRegs:$dst, MEMrr:$addr), 148 "lduh [$addr], $dst", 149 [(set IntRegs:$dst, (zextload ADDRrr:$addr, i16))]>; 150def LDUHri : F3_2<3, 0b000010, 151 (ops IntRegs:$dst, MEMri:$addr), 152 "lduh [$addr], $dst", 153 [(set IntRegs:$dst, (zextload ADDRri:$addr, i16))]>; 154def LDrr : F3_1<3, 0b000000, 155 (ops IntRegs:$dst, MEMrr:$addr), 156 "ld [$addr], $dst", 157 [(set IntRegs:$dst, (load ADDRrr:$addr))]>; 158def LDri : F3_2<3, 0b000000, 159 (ops IntRegs:$dst, MEMri:$addr), 160 "ld [$addr], $dst", 161 [(set IntRegs:$dst, (load ADDRri:$addr))]>; 162def LDDrr : F3_1<3, 0b000011, 163 (ops IntRegs:$dst, MEMrr:$addr), 164 "ldd [$addr], $dst", []>; 165def LDDri : F3_2<3, 0b000011, 166 (ops IntRegs:$dst, MEMri:$addr), 167 "ldd [$addr], $dst", []>; 168 169// Section B.2 - Load Floating-point Instructions, p. 92 170def LDFrr : F3_1<3, 0b100000, 171 (ops FPRegs:$dst, MEMrr:$addr), 172 "ld [$addr], $dst", 173 [(set FPRegs:$dst, (load ADDRrr:$addr))]>; 174def LDFri : F3_2<3, 0b100000, 175 (ops FPRegs:$dst, MEMri:$addr), 176 "ld [$addr], $dst", 177 [(set FPRegs:$dst, (load ADDRri:$addr))]>; 178def LDDFrr : F3_1<3, 0b100011, 179 (ops DFPRegs:$dst, MEMrr:$addr), 180 "ldd [$addr], $dst", 181 [(set DFPRegs:$dst, (load ADDRrr:$addr))]>; 182def LDDFri : F3_2<3, 0b100011, 183 (ops DFPRegs:$dst, MEMri:$addr), 184 "ldd [$addr], $dst", 185 [(set DFPRegs:$dst, (load ADDRri:$addr))]>; 186 187// Section B.4 - Store Integer Instructions, p. 95 188def STBrr : F3_1<3, 0b000101, 189 (ops MEMrr:$addr, IntRegs:$src), 190 "stb $src, [$addr]", 191 [(truncstore IntRegs:$src, ADDRrr:$addr, i8)]>; 192def STBri : F3_2<3, 0b000101, 193 (ops MEMri:$addr, IntRegs:$src), 194 "stb $src, [$addr]", 195 [(truncstore IntRegs:$src, ADDRri:$addr, i8)]>; 196def STHrr : F3_1<3, 0b000110, 197 (ops MEMrr:$addr, IntRegs:$src), 198 "sth $src, [$addr]", 199 [(truncstore IntRegs:$src, ADDRrr:$addr, i16)]>; 200def STHri : F3_2<3, 0b000110, 201 (ops MEMri:$addr, IntRegs:$src), 202 "sth $src, [$addr]", 203 [(truncstore IntRegs:$src, ADDRri:$addr, i16)]>; 204def STrr : F3_1<3, 0b000100, 205 (ops MEMrr:$addr, IntRegs:$src), 206 "st $src, [$addr]", 207 [(store IntRegs:$src, ADDRrr:$addr)]>; 208def STri : F3_2<3, 0b000100, 209 (ops MEMri:$addr, IntRegs:$src), 210 "st $src, [$addr]", 211 [(store IntRegs:$src, ADDRri:$addr)]>; 212def STDrr : F3_1<3, 0b000111, 213 (ops MEMrr:$addr, IntRegs:$src), 214 "std $src, [$addr]", []>; 215def STDri : F3_2<3, 0b000111, 216 (ops MEMri:$addr, IntRegs:$src), 217 "std $src, [$addr]", []>; 218 219// Section B.5 - Store Floating-point Instructions, p. 97 220def STFrr : F3_1<3, 0b100100, 221 (ops MEMrr:$addr, FPRegs:$src), 222 "st $src, [$addr]", 223 [(store FPRegs:$src, ADDRrr:$addr)]>; 224def STFri : F3_2<3, 0b100100, 225 (ops MEMri:$addr, FPRegs:$src), 226 "st $src, [$addr]", 227 [(store FPRegs:$src, ADDRri:$addr)]>; 228def STDFrr : F3_1<3, 0b100111, 229 (ops MEMrr:$addr, DFPRegs:$src), 230 "std $src, [$addr]", 231 [(store DFPRegs:$src, ADDRrr:$addr)]>; 232def STDFri : F3_2<3, 0b100111, 233 (ops MEMri:$addr, DFPRegs:$src), 234 "std $src, [$addr]", 235 [(store DFPRegs:$src, ADDRri:$addr)]>; 236 237// Section B.9 - SETHI Instruction, p. 104 238def SETHIi: F2_1<0b100, 239 (ops IntRegs:$dst, i32imm:$src), 240 "sethi $src, $dst", 241 [(set IntRegs:$dst, SETHIimm:$src)]>; 242 243// Section B.10 - NOP Instruction, p. 105 244// (It's a special case of SETHI) 245let rd = 0, imm22 = 0 in 246 def NOP : F2_1<0b100, (ops), "nop", []>; 247 248// Section B.11 - Logical Instructions, p. 106 249def ANDrr : F3_1<2, 0b000001, 250 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 251 "and $b, $c, $dst", 252 [(set IntRegs:$dst, (and IntRegs:$b, IntRegs:$c))]>; 253def ANDri : F3_2<2, 0b000001, 254 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 255 "and $b, $c, $dst", 256 [(set IntRegs:$dst, (and IntRegs:$b, simm13:$c))]>; 257def ANDNrr : F3_1<2, 0b000101, 258 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 259 "andn $b, $c, $dst", 260 [(set IntRegs:$dst, (and IntRegs:$b, (not IntRegs:$c)))]>; 261def ANDNri : F3_2<2, 0b000101, 262 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 263 "andn $b, $c, $dst", []>; 264def ORrr : F3_1<2, 0b000010, 265 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 266 "or $b, $c, $dst", 267 [(set IntRegs:$dst, (or IntRegs:$b, IntRegs:$c))]>; 268def ORri : F3_2<2, 0b000010, 269 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 270 "or $b, $c, $dst", 271 [(set IntRegs:$dst, (or IntRegs:$b, simm13:$c))]>; 272def ORNrr : F3_1<2, 0b000110, 273 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 274 "orn $b, $c, $dst", 275 [(set IntRegs:$dst, (or IntRegs:$b, (not IntRegs:$c)))]>; 276def ORNri : F3_2<2, 0b000110, 277 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 278 "orn $b, $c, $dst", []>; 279def XORrr : F3_1<2, 0b000011, 280 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 281 "xor $b, $c, $dst", 282 [(set IntRegs:$dst, (xor IntRegs:$b, IntRegs:$c))]>; 283def XORri : F3_2<2, 0b000011, 284 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 285 "xor $b, $c, $dst", 286 [(set IntRegs:$dst, (xor IntRegs:$b, simm13:$c))]>; 287def XNORrr : F3_1<2, 0b000111, 288 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 289 "xnor $b, $c, $dst", 290 [(set IntRegs:$dst, (xor IntRegs:$b, (not IntRegs:$c)))]>; 291def XNORri : F3_2<2, 0b000111, 292 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 293 "xnor $b, $c, $dst", []>; 294 295// Section B.12 - Shift Instructions, p. 107 296def SLLrr : F3_1<2, 0b100101, 297 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 298 "sll $b, $c, $dst", 299 [(set IntRegs:$dst, (shl IntRegs:$b, IntRegs:$c))]>; 300def SLLri : F3_2<2, 0b100101, 301 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 302 "sll $b, $c, $dst", 303 [(set IntRegs:$dst, (shl IntRegs:$b, simm13:$c))]>; 304def SRLrr : F3_1<2, 0b100110, 305 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 306 "srl $b, $c, $dst", 307 [(set IntRegs:$dst, (srl IntRegs:$b, IntRegs:$c))]>; 308def SRLri : F3_2<2, 0b100110, 309 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 310 "srl $b, $c, $dst", 311 [(set IntRegs:$dst, (srl IntRegs:$b, simm13:$c))]>; 312def SRArr : F3_1<2, 0b100111, 313 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 314 "sra $b, $c, $dst", 315 [(set IntRegs:$dst, (sra IntRegs:$b, IntRegs:$c))]>; 316def SRAri : F3_2<2, 0b100111, 317 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 318 "sra $b, $c, $dst", 319 [(set IntRegs:$dst, (sra IntRegs:$b, simm13:$c))]>; 320 321// Section B.13 - Add Instructions, p. 108 322def ADDrr : F3_1<2, 0b000000, 323 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 324 "add $b, $c, $dst", 325 [(set IntRegs:$dst, (add IntRegs:$b, IntRegs:$c))]>; 326def ADDri : F3_2<2, 0b000000, 327 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 328 "add $b, $c, $dst", 329 [(set IntRegs:$dst, (add IntRegs:$b, simm13:$c))]>; 330def ADDCCrr : F3_1<2, 0b010000, 331 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 332 "addcc $b, $c, $dst", []>; 333def ADDCCri : F3_2<2, 0b010000, 334 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 335 "addcc $b, $c, $dst", []>; 336def ADDXrr : F3_1<2, 0b001000, 337 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 338 "addx $b, $c, $dst", []>; 339def ADDXri : F3_2<2, 0b001000, 340 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 341 "addx $b, $c, $dst", []>; 342 343// Section B.15 - Subtract Instructions, p. 110 344def SUBrr : F3_1<2, 0b000100, 345 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 346 "sub $b, $c, $dst", 347 [(set IntRegs:$dst, (sub IntRegs:$b, IntRegs:$c))]>; 348def SUBri : F3_2<2, 0b000100, 349 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 350 "sub $b, $c, $dst", 351 [(set IntRegs:$dst, (sub IntRegs:$b, simm13:$c))]>; 352def SUBXrr : F3_1<2, 0b001100, 353 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 354 "subx $b, $c, $dst", []>; 355def SUBXri : F3_2<2, 0b001100, 356 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 357 "subx $b, $c, $dst", []>; 358def SUBCCrr : F3_1<2, 0b010100, 359 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 360 "subcc $b, $c, $dst", []>; 361def SUBCCri : F3_2<2, 0b010100, 362 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 363 "subcc $b, $c, $dst", []>; 364def SUBXCCrr: F3_1<2, 0b011100, 365 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 366 "subxcc $b, $c, $dst", []>; 367 368// Section B.18 - Multiply Instructions, p. 113 369def UMULrr : F3_1<2, 0b001010, 370 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 371 "umul $b, $c, $dst", []>; 372def UMULri : F3_2<2, 0b001010, 373 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 374 "umul $b, $c, $dst", []>; 375def SMULrr : F3_1<2, 0b001011, 376 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 377 "smul $b, $c, $dst", 378 [(set IntRegs:$dst, (mul IntRegs:$b, IntRegs:$c))]>; 379def SMULri : F3_2<2, 0b001011, 380 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 381 "smul $b, $c, $dst", 382 [(set IntRegs:$dst, (mul IntRegs:$b, simm13:$c))]>; 383 384// Section B.19 - Divide Instructions, p. 115 385def UDIVrr : F3_1<2, 0b001110, 386 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 387 "udiv $b, $c, $dst", []>; 388def UDIVri : F3_2<2, 0b001110, 389 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 390 "udiv $b, $c, $dst", []>; 391def SDIVrr : F3_1<2, 0b001111, 392 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 393 "sdiv $b, $c, $dst", []>; 394def SDIVri : F3_2<2, 0b001111, 395 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 396 "sdiv $b, $c, $dst", []>; 397 398// Section B.20 - SAVE and RESTORE, p. 117 399def SAVErr : F3_1<2, 0b111100, 400 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 401 "save $b, $c, $dst", []>; 402def SAVEri : F3_2<2, 0b111100, 403 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 404 "save $b, $c, $dst", []>; 405def RESTORErr : F3_1<2, 0b111101, 406 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 407 "restore $b, $c, $dst", []>; 408def RESTOREri : F3_2<2, 0b111101, 409 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 410 "restore $b, $c, $dst", []>; 411 412// Section B.21 - Branch on Integer Condition Codes Instructions, p. 119 413 414// conditional branch class: 415class BranchV8<bits<4> cc, dag ops, string asmstr, list<dag> pattern> 416 : F2_2<cc, 0b010, ops, asmstr, pattern> { 417 let isBranch = 1; 418 let isTerminator = 1; 419 let hasDelaySlot = 1; 420} 421 422let isBarrier = 1 in 423 def BA : BranchV8<0b1000, (ops brtarget:$dst), 424 "ba $dst", 425 [(br bb:$dst)]>; 426def BNE : BranchV8<0b1001, (ops brtarget:$dst), 427 "bne $dst", 428 [(V8bricc bb:$dst, SETNE, ICC)]>; 429def BE : BranchV8<0b0001, (ops brtarget:$dst), 430 "be $dst", 431 [(V8bricc bb:$dst, SETEQ, ICC)]>; 432def BG : BranchV8<0b1010, (ops brtarget:$dst), 433 "bg $dst", 434 [(V8bricc bb:$dst, SETGT, ICC)]>; 435def BLE : BranchV8<0b0010, (ops brtarget:$dst), 436 "ble $dst", 437 [(V8bricc bb:$dst, SETLE, ICC)]>; 438def BGE : BranchV8<0b1011, (ops brtarget:$dst), 439 "bge $dst", 440 [(V8bricc bb:$dst, SETGE, ICC)]>; 441def BL : BranchV8<0b0011, (ops brtarget:$dst), 442 "bl $dst", 443 [(V8bricc bb:$dst, SETLT, ICC)]>; 444def BGU : BranchV8<0b1100, (ops brtarget:$dst), 445 "bgu $dst", 446 [(V8bricc bb:$dst, SETUGT, ICC)]>; 447def BLEU : BranchV8<0b0100, (ops brtarget:$dst), 448 "bleu $dst", 449 [(V8bricc bb:$dst, SETULE, ICC)]>; 450def BCC : BranchV8<0b1101, (ops brtarget:$dst), 451 "bcc $dst", 452 [(V8bricc bb:$dst, SETUGE, ICC)]>; 453def BCS : BranchV8<0b0101, (ops brtarget:$dst), 454 "bcs $dst", 455 [(V8bricc bb:$dst, SETULT, ICC)]>; 456 457// Section B.22 - Branch on Floating-point Condition Codes Instructions, p. 121 458 459// floating-point conditional branch class: 460class FPBranchV8<bits<4> cc, dag ops, string asmstr, list<dag> pattern> 461 : F2_2<cc, 0b110, ops, asmstr, pattern> { 462 let isBranch = 1; 463 let isTerminator = 1; 464 let hasDelaySlot = 1; 465} 466 467def FBU : FPBranchV8<0b0111, (ops brtarget:$dst), 468 "fbu $dst", 469 [(V8brfcc bb:$dst, SETUO, FCC)]>; 470def FBG : FPBranchV8<0b0110, (ops brtarget:$dst), 471 "fbg $dst", 472 [(V8brfcc bb:$dst, SETGT, FCC)]>; 473def FBUG : FPBranchV8<0b0101, (ops brtarget:$dst), 474 "fbug $dst", 475 [(V8brfcc bb:$dst, SETUGT, FCC)]>; 476def FBL : FPBranchV8<0b0100, (ops brtarget:$dst), 477 "fbl $dst", 478 [(V8brfcc bb:$dst, SETLT, FCC)]>; 479def FBUL : FPBranchV8<0b0011, (ops brtarget:$dst), 480 "fbul $dst", 481 [(V8brfcc bb:$dst, SETULT, FCC)]>; 482def FBLG : FPBranchV8<0b0010, (ops brtarget:$dst), 483 "fblg $dst", 484 [(V8brfcc bb:$dst, SETONE, FCC)]>; 485def FBNE : FPBranchV8<0b0001, (ops brtarget:$dst), 486 "fbne $dst", 487 [(V8brfcc bb:$dst, SETNE, FCC)]>; 488def FBE : FPBranchV8<0b1001, (ops brtarget:$dst), 489 "fbe $dst", 490 [(V8brfcc bb:$dst, SETEQ, FCC)]>; 491def FBUE : FPBranchV8<0b1010, (ops brtarget:$dst), 492 "fbue $dst", 493 [(V8brfcc bb:$dst, SETUEQ, FCC)]>; 494def FBGE : FPBranchV8<0b1011, (ops brtarget:$dst), 495 "fbge $dst", 496 [(V8brfcc bb:$dst, SETGE, FCC)]>; 497def FBUGE: FPBranchV8<0b1100, (ops brtarget:$dst), 498 "fbuge $dst", 499 [(V8brfcc bb:$dst, SETUGE, FCC)]>; 500def FBLE : FPBranchV8<0b1101, (ops brtarget:$dst), 501 "fble $dst", 502 [(V8brfcc bb:$dst, SETLE, FCC)]>; 503def FBULE: FPBranchV8<0b1110, (ops brtarget:$dst), 504 "fbule $dst", 505 [(V8brfcc bb:$dst, SETULE, FCC)]>; 506def FBO : FPBranchV8<0b1111, (ops brtarget:$dst), 507 "fbo $dst", 508 [(V8brfcc bb:$dst, SETO, FCC)]>; 509 510 511 512// Section B.24 - Call and Link Instruction, p. 125 513// This is the only Format 1 instruction 514let Uses = [O0, O1, O2, O3, O4, O5], hasDelaySlot = 1, isCall = 1 in { 515 // pc-relative call: 516 let Defs = [O0, O1, O2, O3, O4, O5, O7, G1, G2, G3, G4, G5, G6, G7, 517 D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15] in 518 def CALL : InstV8 { 519 let OperandList = (ops IntRegs:$dst); 520 bits<30> disp; 521 let op = 1; 522 let Inst{29-0} = disp; 523 let AsmString = "call $dst"; 524 } 525 526 // indirect call (O7 is an EXPLICIT def in indirect calls, so it cannot also 527 // be an implicit def): 528 let Defs = [O0, O1, O2, O3, O4, O5, G1, G2, G3, G4, G5, G6, G7, 529 D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15] in 530 def JMPLrr : F3_1<2, 0b111000, 531 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 532 "jmpl $b+$c, $dst", []>; 533} 534 535// Section B.28 - Read State Register Instructions 536def RDY : F3_1<2, 0b101000, 537 (ops IntRegs:$dst), 538 "rdy $dst", []>; 539 540// Section B.29 - Write State Register Instructions 541def WRYrr : F3_1<2, 0b110000, 542 (ops IntRegs:$b, IntRegs:$c), 543 "wr $b, $c, %y", []>; 544def WRYri : F3_2<2, 0b110000, 545 (ops IntRegs:$b, i32imm:$c), 546 "wr $b, $c, %y", []>; 547 548// Convert Integer to Floating-point Instructions, p. 141 549def FITOS : F3_3<2, 0b110100, 0b011000100, 550 (ops FPRegs:$dst, FPRegs:$src), 551 "fitos $src, $dst", 552 [(set FPRegs:$dst, (V8itof FPRegs:$src))]>; 553def FITOD : F3_3<2, 0b110100, 0b011001000, 554 (ops DFPRegs:$dst, DFPRegs:$src), 555 "fitod $src, $dst", 556 [(set DFPRegs:$dst, (V8itof DFPRegs:$src))]>; 557 558// Convert Floating-point to Integer Instructions, p. 142 559def FSTOI : F3_3<2, 0b110100, 0b011010001, 560 (ops FPRegs:$dst, FPRegs:$src), 561 "fstoi $src, $dst", 562 [(set FPRegs:$dst, (V8ftoi FPRegs:$src))]>; 563def FDTOI : F3_3<2, 0b110100, 0b011010010, 564 (ops DFPRegs:$dst, DFPRegs:$src), 565 "fdtoi $src, $dst", 566 [(set DFPRegs:$dst, (V8ftoi DFPRegs:$src))]>; 567 568// Convert between Floating-point Formats Instructions, p. 143 569def FSTOD : F3_3<2, 0b110100, 0b011001001, 570 (ops DFPRegs:$dst, FPRegs:$src), 571 "fstod $src, $dst", 572 [(set DFPRegs:$dst, (fextend FPRegs:$src))]>; 573def FDTOS : F3_3<2, 0b110100, 0b011000110, 574 (ops FPRegs:$dst, DFPRegs:$src), 575 "fdtos $src, $dst", 576 [(set FPRegs:$dst, (fround DFPRegs:$src))]>; 577 578// Floating-point Move Instructions, p. 144 579def FMOVS : F3_3<2, 0b110100, 0b000000001, 580 (ops FPRegs:$dst, FPRegs:$src), 581 "fmovs $src, $dst", []>; 582def FNEGS : F3_3<2, 0b110100, 0b000000101, 583 (ops FPRegs:$dst, FPRegs:$src), 584 "fnegs $src, $dst", 585 [(set FPRegs:$dst, (fneg FPRegs:$src))]>; 586def FABSS : F3_3<2, 0b110100, 0b000001001, 587 (ops FPRegs:$dst, FPRegs:$src), 588 "fabss $src, $dst", 589 [(set FPRegs:$dst, (fabs FPRegs:$src))]>; 590// FIXME: ADD FNEGD/FABSD pseudo instructions. 591 592 593// Floating-point Square Root Instructions, p.145 594def FSQRTS : F3_3<2, 0b110100, 0b000101001, 595 (ops FPRegs:$dst, FPRegs:$src), 596 "fsqrts $src, $dst", 597 [(set FPRegs:$dst, (fsqrt FPRegs:$src))]>; 598def FSQRTD : F3_3<2, 0b110100, 0b000101010, 599 (ops DFPRegs:$dst, DFPRegs:$src), 600 "fsqrtd $src, $dst", 601 [(set DFPRegs:$dst, (fsqrt DFPRegs:$src))]>; 602 603 604 605// Floating-point Add and Subtract Instructions, p. 146 606def FADDS : F3_3<2, 0b110100, 0b001000001, 607 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2), 608 "fadds $src1, $src2, $dst", 609 [(set FPRegs:$dst, (fadd FPRegs:$src1, FPRegs:$src2))]>; 610def FADDD : F3_3<2, 0b110100, 0b001000010, 611 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2), 612 "faddd $src1, $src2, $dst", 613 [(set DFPRegs:$dst, (fadd DFPRegs:$src1, DFPRegs:$src2))]>; 614def FSUBS : F3_3<2, 0b110100, 0b001000101, 615 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2), 616 "fsubs $src1, $src2, $dst", 617 [(set FPRegs:$dst, (fsub FPRegs:$src1, FPRegs:$src2))]>; 618def FSUBD : F3_3<2, 0b110100, 0b001000110, 619 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2), 620 "fsubd $src1, $src2, $dst", 621 [(set DFPRegs:$dst, (fsub DFPRegs:$src1, DFPRegs:$src2))]>; 622 623// Floating-point Multiply and Divide Instructions, p. 147 624def FMULS : F3_3<2, 0b110100, 0b001001001, 625 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2), 626 "fmuls $src1, $src2, $dst", 627 [(set FPRegs:$dst, (fmul FPRegs:$src1, FPRegs:$src2))]>; 628def FMULD : F3_3<2, 0b110100, 0b001001010, 629 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2), 630 "fmuld $src1, $src2, $dst", 631 [(set DFPRegs:$dst, (fmul DFPRegs:$src1, DFPRegs:$src2))]>; 632def FSMULD : F3_3<2, 0b110100, 0b001101001, 633 (ops DFPRegs:$dst, FPRegs:$src1, FPRegs:$src2), 634 "fsmuld $src1, $src2, $dst", 635 [(set DFPRegs:$dst, (fmul (fextend FPRegs:$src1), 636 (fextend FPRegs:$src2)))]>; 637def FDIVS : F3_3<2, 0b110100, 0b001001101, 638 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2), 639 "fdivs $src1, $src2, $dst", 640 [(set FPRegs:$dst, (fdiv FPRegs:$src1, FPRegs:$src2))]>; 641def FDIVD : F3_3<2, 0b110100, 0b001001110, 642 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2), 643 "fdivd $src1, $src2, $dst", 644 [(set DFPRegs:$dst, (fdiv DFPRegs:$src1, DFPRegs:$src2))]>; 645 646// Floating-point Compare Instructions, p. 148 647// Note: the 2nd template arg is different for these guys. 648// Note 2: the result of a FCMP is not available until the 2nd cycle 649// after the instr is retired, but there is no interlock. This behavior 650// is modelled with a forced noop after the instruction. 651def FCMPS : F3_3<2, 0b110101, 0b001010001, 652 (ops FPRegs:$src1, FPRegs:$src2), 653 "fcmps $src1, $src2\n\tnop", 654 [(set FCC, (V8cmpfcc FPRegs:$src1, FPRegs:$src2))]>; 655def FCMPD : F3_3<2, 0b110101, 0b001010010, 656 (ops DFPRegs:$src1, DFPRegs:$src2), 657 "fcmpd $src1, $src2\n\tnop", 658 [(set FCC, (V8cmpfcc DFPRegs:$src1, DFPRegs:$src2))]>; 659 660//===----------------------------------------------------------------------===// 661// Non-Instruction Patterns 662//===----------------------------------------------------------------------===// 663 664// Small immediates. 665def : Pat<(i32 simm13:$val), 666 (ORri G0, imm:$val)>; 667// Arbitrary immediates. 668def : Pat<(i32 imm:$val), 669 (ORri (SETHIi (HI22 imm:$val)), (LO10 imm:$val))>; 670 671// Global addresses, constant pool entries 672def : Pat<(V8hi tglobaladdr:$in), (SETHIi tglobaladdr:$in)>; 673def : Pat<(V8lo tglobaladdr:$in), (ORri G0, tglobaladdr:$in)>; 674def : Pat<(V8hi tconstpool:$in), (SETHIi tconstpool:$in)>; 675def : Pat<(V8lo tconstpool:$in), (ORri G0, tconstpool:$in)>; 676