SparcInstrInfo.td revision a432a97b62617b8b74219ae60c6c6db5cc5ec7ab
1//===-- SparcInstrInfo.td - Target Description for Sparc Target -----------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the Sparc instructions in TableGen format. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// Instruction format superclass 16//===----------------------------------------------------------------------===// 17 18include "SparcInstrFormats.td" 19 20//===----------------------------------------------------------------------===// 21// Feature predicates. 22//===----------------------------------------------------------------------===// 23 24// True when generating 32-bit code. 25def Is32Bit : Predicate<"!Subtarget.is64Bit()">; 26 27// True when generating 64-bit code. This also implies HasV9. 28def Is64Bit : Predicate<"Subtarget.is64Bit()">; 29 30// HasV9 - This predicate is true when the target processor supports V9 31// instructions. Note that the machine may be running in 32-bit mode. 32def HasV9 : Predicate<"Subtarget.isV9()">; 33 34// HasNoV9 - This predicate is true when the target doesn't have V9 35// instructions. Use of this is just a hack for the isel not having proper 36// costs for V8 instructions that are more expensive than their V9 ones. 37def HasNoV9 : Predicate<"!Subtarget.isV9()">; 38 39// HasVIS - This is true when the target processor has VIS extensions. 40def HasVIS : Predicate<"Subtarget.isVIS()">; 41 42// HasHardQuad - This is true when the target processor supports quad floating 43// point instructions. 44def HasHardQuad : Predicate<"Subtarget.hasHardQuad()">; 45 46// UseDeprecatedInsts - This predicate is true when the target processor is a 47// V8, or when it is V9 but the V8 deprecated instructions are efficient enough 48// to use when appropriate. In either of these cases, the instruction selector 49// will pick deprecated instructions. 50def UseDeprecatedInsts : Predicate<"Subtarget.useDeprecatedV8Instructions()">; 51 52//===----------------------------------------------------------------------===// 53// Instruction Pattern Stuff 54//===----------------------------------------------------------------------===// 55 56def simm11 : PatLeaf<(imm), [{ return isInt<11>(N->getSExtValue()); }]>; 57 58def simm13 : PatLeaf<(imm), [{ return isInt<13>(N->getSExtValue()); }]>; 59 60def LO10 : SDNodeXForm<imm, [{ 61 return CurDAG->getTargetConstant((unsigned)N->getZExtValue() & 1023, 62 MVT::i32); 63}]>; 64 65def HI22 : SDNodeXForm<imm, [{ 66 // Transformation function: shift the immediate value down into the low bits. 67 return CurDAG->getTargetConstant((unsigned)N->getZExtValue() >> 10, MVT::i32); 68}]>; 69 70def SETHIimm : PatLeaf<(imm), [{ 71 return isShiftedUInt<22, 10>(N->getZExtValue()); 72}], HI22>; 73 74// Addressing modes. 75def ADDRrr : ComplexPattern<iPTR, 2, "SelectADDRrr", [], []>; 76def ADDRri : ComplexPattern<iPTR, 2, "SelectADDRri", [frameindex], []>; 77 78// Address operands 79def MEMrr : Operand<iPTR> { 80 let PrintMethod = "printMemOperand"; 81 let MIOperandInfo = (ops ptr_rc, ptr_rc); 82} 83def MEMri : Operand<iPTR> { 84 let PrintMethod = "printMemOperand"; 85 let MIOperandInfo = (ops ptr_rc, i32imm); 86} 87 88def TLSSym : Operand<iPTR>; 89 90// Branch targets have OtherVT type. 91def brtarget : Operand<OtherVT>; 92def calltarget : Operand<i32>; 93 94// Operand for printing out a condition code. 95let PrintMethod = "printCCOperand" in 96 def CCOp : Operand<i32>; 97 98def SDTSPcmpicc : 99SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>]>; 100def SDTSPcmpfcc : 101SDTypeProfile<0, 2, [SDTCisFP<0>, SDTCisSameAs<0, 1>]>; 102def SDTSPbrcc : 103SDTypeProfile<0, 2, [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>; 104def SDTSPselectcc : 105SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>]>; 106def SDTSPFTOI : 107SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisFP<1>]>; 108def SDTSPITOF : 109SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f32>]>; 110 111def SDTSPtlsadd : 112SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>, SDTCisPtrTy<2>]>; 113def SDTSPtlsld : 114SDTypeProfile<1, 2, [SDTCisPtrTy<0>, SDTCisPtrTy<1>]>; 115 116def SPcmpicc : SDNode<"SPISD::CMPICC", SDTSPcmpicc, [SDNPOutGlue]>; 117def SPcmpfcc : SDNode<"SPISD::CMPFCC", SDTSPcmpfcc, [SDNPOutGlue]>; 118def SPbricc : SDNode<"SPISD::BRICC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>; 119def SPbrxcc : SDNode<"SPISD::BRXCC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>; 120def SPbrfcc : SDNode<"SPISD::BRFCC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>; 121 122def SPhi : SDNode<"SPISD::Hi", SDTIntUnaryOp>; 123def SPlo : SDNode<"SPISD::Lo", SDTIntUnaryOp>; 124 125def SPftoi : SDNode<"SPISD::FTOI", SDTSPFTOI>; 126def SPitof : SDNode<"SPISD::ITOF", SDTSPITOF>; 127 128def SPselecticc : SDNode<"SPISD::SELECT_ICC", SDTSPselectcc, [SDNPInGlue]>; 129def SPselectxcc : SDNode<"SPISD::SELECT_XCC", SDTSPselectcc, [SDNPInGlue]>; 130def SPselectfcc : SDNode<"SPISD::SELECT_FCC", SDTSPselectcc, [SDNPInGlue]>; 131 132// These are target-independent nodes, but have target-specific formats. 133def SDT_SPCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>; 134def SDT_SPCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, 135 SDTCisVT<1, i32> ]>; 136 137def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_SPCallSeqStart, 138 [SDNPHasChain, SDNPOutGlue]>; 139def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_SPCallSeqEnd, 140 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 141 142def SDT_SPCall : SDTypeProfile<0, -1, [SDTCisVT<0, i32>]>; 143def call : SDNode<"SPISD::CALL", SDT_SPCall, 144 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 145 SDNPVariadic]>; 146 147def SDT_SPRet : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>; 148def retflag : SDNode<"SPISD::RET_FLAG", SDT_SPRet, 149 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 150 151def flushw : SDNode<"SPISD::FLUSHW", SDTNone, 152 [SDNPHasChain, SDNPSideEffect, SDNPMayStore]>; 153 154def tlsadd : SDNode<"SPISD::TLS_ADD", SDTSPtlsadd>; 155def tlsld : SDNode<"SPISD::TLS_LD", SDTSPtlsld>; 156def tlscall : SDNode<"SPISD::TLS_CALL", SDT_SPCall, 157 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 158 SDNPVariadic]>; 159 160def getPCX : Operand<i32> { 161 let PrintMethod = "printGetPCX"; 162} 163 164//===----------------------------------------------------------------------===// 165// SPARC Flag Conditions 166//===----------------------------------------------------------------------===// 167 168// Note that these values must be kept in sync with the CCOp::CondCode enum 169// values. 170class ICC_VAL<int N> : PatLeaf<(i32 N)>; 171def ICC_NE : ICC_VAL< 9>; // Not Equal 172def ICC_E : ICC_VAL< 1>; // Equal 173def ICC_G : ICC_VAL<10>; // Greater 174def ICC_LE : ICC_VAL< 2>; // Less or Equal 175def ICC_GE : ICC_VAL<11>; // Greater or Equal 176def ICC_L : ICC_VAL< 3>; // Less 177def ICC_GU : ICC_VAL<12>; // Greater Unsigned 178def ICC_LEU : ICC_VAL< 4>; // Less or Equal Unsigned 179def ICC_CC : ICC_VAL<13>; // Carry Clear/Great or Equal Unsigned 180def ICC_CS : ICC_VAL< 5>; // Carry Set/Less Unsigned 181def ICC_POS : ICC_VAL<14>; // Positive 182def ICC_NEG : ICC_VAL< 6>; // Negative 183def ICC_VC : ICC_VAL<15>; // Overflow Clear 184def ICC_VS : ICC_VAL< 7>; // Overflow Set 185 186class FCC_VAL<int N> : PatLeaf<(i32 N)>; 187def FCC_U : FCC_VAL<23>; // Unordered 188def FCC_G : FCC_VAL<22>; // Greater 189def FCC_UG : FCC_VAL<21>; // Unordered or Greater 190def FCC_L : FCC_VAL<20>; // Less 191def FCC_UL : FCC_VAL<19>; // Unordered or Less 192def FCC_LG : FCC_VAL<18>; // Less or Greater 193def FCC_NE : FCC_VAL<17>; // Not Equal 194def FCC_E : FCC_VAL<25>; // Equal 195def FCC_UE : FCC_VAL<24>; // Unordered or Equal 196def FCC_GE : FCC_VAL<25>; // Greater or Equal 197def FCC_UGE : FCC_VAL<26>; // Unordered or Greater or Equal 198def FCC_LE : FCC_VAL<27>; // Less or Equal 199def FCC_ULE : FCC_VAL<28>; // Unordered or Less or Equal 200def FCC_O : FCC_VAL<29>; // Ordered 201 202//===----------------------------------------------------------------------===// 203// Instruction Class Templates 204//===----------------------------------------------------------------------===// 205 206/// F3_12 multiclass - Define a normal F3_1/F3_2 pattern in one shot. 207multiclass F3_12<string OpcStr, bits<6> Op3Val, SDNode OpNode> { 208 def rr : F3_1<2, Op3Val, 209 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c), 210 !strconcat(OpcStr, " $b, $c, $dst"), 211 [(set i32:$dst, (OpNode i32:$b, i32:$c))]>; 212 def ri : F3_2<2, Op3Val, 213 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c), 214 !strconcat(OpcStr, " $b, $c, $dst"), 215 [(set i32:$dst, (OpNode i32:$b, (i32 simm13:$c)))]>; 216} 217 218/// F3_12np multiclass - Define a normal F3_1/F3_2 pattern in one shot, with no 219/// pattern. 220multiclass F3_12np<string OpcStr, bits<6> Op3Val> { 221 def rr : F3_1<2, Op3Val, 222 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c), 223 !strconcat(OpcStr, " $b, $c, $dst"), []>; 224 def ri : F3_2<2, Op3Val, 225 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c), 226 !strconcat(OpcStr, " $b, $c, $dst"), []>; 227} 228 229//===----------------------------------------------------------------------===// 230// Instructions 231//===----------------------------------------------------------------------===// 232 233// Pseudo instructions. 234class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern> 235 : InstSP<outs, ins, asmstr, pattern>; 236 237// GETPCX for PIC 238let Defs = [O7] in { 239 def GETPCX : Pseudo<(outs getPCX:$getpcseq), (ins), "$getpcseq", [] >; 240} 241 242let Defs = [O6], Uses = [O6] in { 243def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt), 244 "!ADJCALLSTACKDOWN $amt", 245 [(callseq_start timm:$amt)]>; 246def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2), 247 "!ADJCALLSTACKUP $amt1", 248 [(callseq_end timm:$amt1, timm:$amt2)]>; 249} 250 251let hasSideEffects = 1, mayStore = 1 in { 252 let rd = 0, rs1 = 0, rs2 = 0 in 253 def FLUSHW : F3_1<0b10, 0b101011, (outs), (ins), 254 "flushw", 255 [(flushw)]>, Requires<[HasV9]>; 256 let rd = 0, rs1 = 1, simm13 = 3 in 257 def TA3 : F3_2<0b10, 0b111010, (outs), (ins), 258 "ta 3", 259 [(flushw)]>; 260} 261 262def UNIMP : F2_1<0b000, (outs), (ins i32imm:$val), 263 "unimp $val", []>; 264 265// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after 266// instruction selection into a branch sequence. This has to handle all 267// permutations of selection between i32/f32/f64 on ICC and FCC. 268// Expanded after instruction selection. 269let Uses = [ICC], usesCustomInserter = 1 in { 270 def SELECT_CC_Int_ICC 271 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond), 272 "; SELECT_CC_Int_ICC PSEUDO!", 273 [(set i32:$dst, (SPselecticc i32:$T, i32:$F, imm:$Cond))]>; 274 def SELECT_CC_FP_ICC 275 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, i32imm:$Cond), 276 "; SELECT_CC_FP_ICC PSEUDO!", 277 [(set f32:$dst, (SPselecticc f32:$T, f32:$F, imm:$Cond))]>; 278 279 def SELECT_CC_DFP_ICC 280 : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, i32imm:$Cond), 281 "; SELECT_CC_DFP_ICC PSEUDO!", 282 [(set f64:$dst, (SPselecticc f64:$T, f64:$F, imm:$Cond))]>; 283 284 def SELECT_CC_QFP_ICC 285 : Pseudo<(outs QFPRegs:$dst), (ins QFPRegs:$T, QFPRegs:$F, i32imm:$Cond), 286 "; SELECT_CC_QFP_ICC PSEUDO!", 287 [(set f128:$dst, (SPselecticc f128:$T, f128:$F, imm:$Cond))]>; 288} 289 290let usesCustomInserter = 1, Uses = [FCC] in { 291 292 def SELECT_CC_Int_FCC 293 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond), 294 "; SELECT_CC_Int_FCC PSEUDO!", 295 [(set i32:$dst, (SPselectfcc i32:$T, i32:$F, imm:$Cond))]>; 296 297 def SELECT_CC_FP_FCC 298 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, i32imm:$Cond), 299 "; SELECT_CC_FP_FCC PSEUDO!", 300 [(set f32:$dst, (SPselectfcc f32:$T, f32:$F, imm:$Cond))]>; 301 def SELECT_CC_DFP_FCC 302 : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, i32imm:$Cond), 303 "; SELECT_CC_DFP_FCC PSEUDO!", 304 [(set f64:$dst, (SPselectfcc f64:$T, f64:$F, imm:$Cond))]>; 305 def SELECT_CC_QFP_FCC 306 : Pseudo<(outs QFPRegs:$dst), (ins QFPRegs:$T, QFPRegs:$F, i32imm:$Cond), 307 "; SELECT_CC_QFP_FCC PSEUDO!", 308 [(set f128:$dst, (SPselectfcc f128:$T, f128:$F, imm:$Cond))]>; 309} 310 311 312// Section A.3 - Synthetic Instructions, p. 85 313// special cases of JMPL: 314let isReturn = 1, isTerminator = 1, hasDelaySlot = 1, isBarrier = 1 in { 315 let rd = 0, rs1 = 15 in 316 def RETL: F3_2<2, 0b111000, (outs), (ins i32imm:$val), 317 "jmp %o7+$val", [(retflag simm13:$val)]>; 318 319 let rd = 0, rs1 = 31 in 320 def RET: F3_2<2, 0b111000, (outs), (ins i32imm:$val), 321 "jmp %i7+$val", []>; 322} 323 324// Section B.1 - Load Integer Instructions, p. 90 325def LDSBrr : F3_1<3, 0b001001, 326 (outs IntRegs:$dst), (ins MEMrr:$addr), 327 "ldsb [$addr], $dst", 328 [(set i32:$dst, (sextloadi8 ADDRrr:$addr))]>; 329def LDSBri : F3_2<3, 0b001001, 330 (outs IntRegs:$dst), (ins MEMri:$addr), 331 "ldsb [$addr], $dst", 332 [(set i32:$dst, (sextloadi8 ADDRri:$addr))]>; 333def LDSHrr : F3_1<3, 0b001010, 334 (outs IntRegs:$dst), (ins MEMrr:$addr), 335 "ldsh [$addr], $dst", 336 [(set i32:$dst, (sextloadi16 ADDRrr:$addr))]>; 337def LDSHri : F3_2<3, 0b001010, 338 (outs IntRegs:$dst), (ins MEMri:$addr), 339 "ldsh [$addr], $dst", 340 [(set i32:$dst, (sextloadi16 ADDRri:$addr))]>; 341def LDUBrr : F3_1<3, 0b000001, 342 (outs IntRegs:$dst), (ins MEMrr:$addr), 343 "ldub [$addr], $dst", 344 [(set i32:$dst, (zextloadi8 ADDRrr:$addr))]>; 345def LDUBri : F3_2<3, 0b000001, 346 (outs IntRegs:$dst), (ins MEMri:$addr), 347 "ldub [$addr], $dst", 348 [(set i32:$dst, (zextloadi8 ADDRri:$addr))]>; 349def LDUHrr : F3_1<3, 0b000010, 350 (outs IntRegs:$dst), (ins MEMrr:$addr), 351 "lduh [$addr], $dst", 352 [(set i32:$dst, (zextloadi16 ADDRrr:$addr))]>; 353def LDUHri : F3_2<3, 0b000010, 354 (outs IntRegs:$dst), (ins MEMri:$addr), 355 "lduh [$addr], $dst", 356 [(set i32:$dst, (zextloadi16 ADDRri:$addr))]>; 357def LDrr : F3_1<3, 0b000000, 358 (outs IntRegs:$dst), (ins MEMrr:$addr), 359 "ld [$addr], $dst", 360 [(set i32:$dst, (load ADDRrr:$addr))]>; 361def LDri : F3_2<3, 0b000000, 362 (outs IntRegs:$dst), (ins MEMri:$addr), 363 "ld [$addr], $dst", 364 [(set i32:$dst, (load ADDRri:$addr))]>; 365 366// Section B.2 - Load Floating-point Instructions, p. 92 367def LDFrr : F3_1<3, 0b100000, 368 (outs FPRegs:$dst), (ins MEMrr:$addr), 369 "ld [$addr], $dst", 370 [(set f32:$dst, (load ADDRrr:$addr))]>; 371def LDFri : F3_2<3, 0b100000, 372 (outs FPRegs:$dst), (ins MEMri:$addr), 373 "ld [$addr], $dst", 374 [(set f32:$dst, (load ADDRri:$addr))]>; 375def LDDFrr : F3_1<3, 0b100011, 376 (outs DFPRegs:$dst), (ins MEMrr:$addr), 377 "ldd [$addr], $dst", 378 [(set f64:$dst, (load ADDRrr:$addr))]>; 379def LDDFri : F3_2<3, 0b100011, 380 (outs DFPRegs:$dst), (ins MEMri:$addr), 381 "ldd [$addr], $dst", 382 [(set f64:$dst, (load ADDRri:$addr))]>; 383def LDQFrr : F3_1<3, 0b100010, 384 (outs QFPRegs:$dst), (ins MEMrr:$addr), 385 "ldq [$addr], $dst", 386 [(set f128:$dst, (load ADDRrr:$addr))]>, 387 Requires<[HasV9, HasHardQuad]>; 388def LDQFri : F3_2<3, 0b100010, 389 (outs QFPRegs:$dst), (ins MEMri:$addr), 390 "ldq [$addr], $dst", 391 [(set f128:$dst, (load ADDRri:$addr))]>, 392 Requires<[HasV9, HasHardQuad]>; 393 394// Section B.4 - Store Integer Instructions, p. 95 395def STBrr : F3_1<3, 0b000101, 396 (outs), (ins MEMrr:$addr, IntRegs:$src), 397 "stb $src, [$addr]", 398 [(truncstorei8 i32:$src, ADDRrr:$addr)]>; 399def STBri : F3_2<3, 0b000101, 400 (outs), (ins MEMri:$addr, IntRegs:$src), 401 "stb $src, [$addr]", 402 [(truncstorei8 i32:$src, ADDRri:$addr)]>; 403def STHrr : F3_1<3, 0b000110, 404 (outs), (ins MEMrr:$addr, IntRegs:$src), 405 "sth $src, [$addr]", 406 [(truncstorei16 i32:$src, ADDRrr:$addr)]>; 407def STHri : F3_2<3, 0b000110, 408 (outs), (ins MEMri:$addr, IntRegs:$src), 409 "sth $src, [$addr]", 410 [(truncstorei16 i32:$src, ADDRri:$addr)]>; 411def STrr : F3_1<3, 0b000100, 412 (outs), (ins MEMrr:$addr, IntRegs:$src), 413 "st $src, [$addr]", 414 [(store i32:$src, ADDRrr:$addr)]>; 415def STri : F3_2<3, 0b000100, 416 (outs), (ins MEMri:$addr, IntRegs:$src), 417 "st $src, [$addr]", 418 [(store i32:$src, ADDRri:$addr)]>; 419 420// Section B.5 - Store Floating-point Instructions, p. 97 421def STFrr : F3_1<3, 0b100100, 422 (outs), (ins MEMrr:$addr, FPRegs:$src), 423 "st $src, [$addr]", 424 [(store f32:$src, ADDRrr:$addr)]>; 425def STFri : F3_2<3, 0b100100, 426 (outs), (ins MEMri:$addr, FPRegs:$src), 427 "st $src, [$addr]", 428 [(store f32:$src, ADDRri:$addr)]>; 429def STDFrr : F3_1<3, 0b100111, 430 (outs), (ins MEMrr:$addr, DFPRegs:$src), 431 "std $src, [$addr]", 432 [(store f64:$src, ADDRrr:$addr)]>; 433def STDFri : F3_2<3, 0b100111, 434 (outs), (ins MEMri:$addr, DFPRegs:$src), 435 "std $src, [$addr]", 436 [(store f64:$src, ADDRri:$addr)]>; 437def STQFrr : F3_1<3, 0b100110, 438 (outs), (ins MEMrr:$addr, QFPRegs:$src), 439 "stq $src, [$addr]", 440 [(store f128:$src, ADDRrr:$addr)]>, 441 Requires<[HasV9, HasHardQuad]>; 442def STQFri : F3_2<3, 0b100110, 443 (outs), (ins MEMri:$addr, QFPRegs:$src), 444 "stq $src, [$addr]", 445 [(store f128:$src, ADDRri:$addr)]>, 446 Requires<[HasV9, HasHardQuad]>; 447 448// Section B.9 - SETHI Instruction, p. 104 449def SETHIi: F2_1<0b100, 450 (outs IntRegs:$dst), (ins i32imm:$src), 451 "sethi $src, $dst", 452 [(set i32:$dst, SETHIimm:$src)]>; 453 454// Section B.10 - NOP Instruction, p. 105 455// (It's a special case of SETHI) 456let rd = 0, imm22 = 0 in 457 def NOP : F2_1<0b100, (outs), (ins), "nop", []>; 458 459// Section B.11 - Logical Instructions, p. 106 460defm AND : F3_12<"and", 0b000001, and>; 461 462def ANDNrr : F3_1<2, 0b000101, 463 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c), 464 "andn $b, $c, $dst", 465 [(set i32:$dst, (and i32:$b, (not i32:$c)))]>; 466def ANDNri : F3_2<2, 0b000101, 467 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c), 468 "andn $b, $c, $dst", []>; 469 470defm OR : F3_12<"or", 0b000010, or>; 471 472def ORNrr : F3_1<2, 0b000110, 473 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c), 474 "orn $b, $c, $dst", 475 [(set i32:$dst, (or i32:$b, (not i32:$c)))]>; 476def ORNri : F3_2<2, 0b000110, 477 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c), 478 "orn $b, $c, $dst", []>; 479defm XOR : F3_12<"xor", 0b000011, xor>; 480 481def XNORrr : F3_1<2, 0b000111, 482 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c), 483 "xnor $b, $c, $dst", 484 [(set i32:$dst, (not (xor i32:$b, i32:$c)))]>; 485def XNORri : F3_2<2, 0b000111, 486 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c), 487 "xnor $b, $c, $dst", []>; 488 489// Section B.12 - Shift Instructions, p. 107 490defm SLL : F3_12<"sll", 0b100101, shl>; 491defm SRL : F3_12<"srl", 0b100110, srl>; 492defm SRA : F3_12<"sra", 0b100111, sra>; 493 494// Section B.13 - Add Instructions, p. 108 495defm ADD : F3_12<"add", 0b000000, add>; 496 497// "LEA" forms of add (patterns to make tblgen happy) 498def LEA_ADDri : F3_2<2, 0b000000, 499 (outs IntRegs:$dst), (ins MEMri:$addr), 500 "add ${addr:arith}, $dst", 501 [(set iPTR:$dst, ADDRri:$addr)]>; 502 503let Defs = [ICC] in 504 defm ADDCC : F3_12<"addcc", 0b010000, addc>; 505 506let Uses = [ICC] in 507 defm ADDX : F3_12<"addx", 0b001000, adde>; 508 509// Section B.15 - Subtract Instructions, p. 110 510defm SUB : F3_12 <"sub" , 0b000100, sub>; 511let Uses = [ICC] in 512 defm SUBX : F3_12 <"subx" , 0b001100, sube>; 513 514let Defs = [ICC] in { 515 defm SUBCC : F3_12 <"subcc", 0b010100, subc>; 516 517 def CMPrr : F3_1<2, 0b010100, 518 (outs), (ins IntRegs:$b, IntRegs:$c), 519 "cmp $b, $c", 520 [(SPcmpicc i32:$b, i32:$c)]>; 521 def CMPri : F3_1<2, 0b010100, 522 (outs), (ins IntRegs:$b, i32imm:$c), 523 "cmp $b, $c", 524 [(SPcmpicc i32:$b, (i32 simm13:$c))]>; 525} 526 527let Uses = [ICC], Defs = [ICC] in 528 def SUBXCCrr: F3_1<2, 0b011100, 529 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c), 530 "subxcc $b, $c, $dst", []>; 531 532 533// Section B.18 - Multiply Instructions, p. 113 534let Defs = [Y] in { 535 defm UMUL : F3_12np<"umul", 0b001010>; 536 defm SMUL : F3_12 <"smul", 0b001011, mul>; 537} 538 539// Section B.19 - Divide Instructions, p. 115 540let Defs = [Y] in { 541 defm UDIV : F3_12np<"udiv", 0b001110>; 542 defm SDIV : F3_12np<"sdiv", 0b001111>; 543} 544 545// Section B.20 - SAVE and RESTORE, p. 117 546defm SAVE : F3_12np<"save" , 0b111100>; 547defm RESTORE : F3_12np<"restore", 0b111101>; 548 549// Section B.21 - Branch on Integer Condition Codes Instructions, p. 119 550 551// unconditional branch class. 552class BranchAlways<dag ins, string asmstr, list<dag> pattern> 553 : F2_2<0b010, (outs), ins, asmstr, pattern> { 554 let isBranch = 1; 555 let isTerminator = 1; 556 let hasDelaySlot = 1; 557 let isBarrier = 1; 558} 559 560let cond = 8 in 561 def BA : BranchAlways<(ins brtarget:$imm22), "ba $imm22", [(br bb:$imm22)]>; 562 563// conditional branch class: 564class BranchSP<dag ins, string asmstr, list<dag> pattern> 565 : F2_2<0b010, (outs), ins, asmstr, pattern> { 566 let isBranch = 1; 567 let isTerminator = 1; 568 let hasDelaySlot = 1; 569} 570 571// Indirect branch instructions. 572let isTerminator = 1, isBarrier = 1, 573 hasDelaySlot = 1, isBranch =1, 574 isIndirectBranch = 1 in { 575 def BINDrr : F3_1<2, 0b111000, 576 (outs), (ins MEMrr:$ptr), 577 "jmp $ptr", 578 [(brind ADDRrr:$ptr)]>; 579 def BINDri : F3_2<2, 0b111000, 580 (outs), (ins MEMri:$ptr), 581 "jmp $ptr", 582 [(brind ADDRri:$ptr)]>; 583} 584 585let Uses = [ICC] in 586 def BCOND : BranchSP<(ins brtarget:$imm22, CCOp:$cond), 587 "b$cond $imm22", 588 [(SPbricc bb:$imm22, imm:$cond)]>; 589 590// Section B.22 - Branch on Floating-point Condition Codes Instructions, p. 121 591 592// floating-point conditional branch class: 593class FPBranchSP<dag ins, string asmstr, list<dag> pattern> 594 : F2_2<0b110, (outs), ins, asmstr, pattern> { 595 let isBranch = 1; 596 let isTerminator = 1; 597 let hasDelaySlot = 1; 598} 599 600let Uses = [FCC] in 601 def FBCOND : FPBranchSP<(ins brtarget:$imm22, CCOp:$cond), 602 "fb$cond $imm22", 603 [(SPbrfcc bb:$imm22, imm:$cond)]>; 604 605 606// Section B.24 - Call and Link Instruction, p. 125 607// This is the only Format 1 instruction 608let Uses = [O6], 609 hasDelaySlot = 1, isCall = 1 in { 610 def CALL : InstSP<(outs), (ins calltarget:$dst, variable_ops), 611 "call $dst", []> { 612 bits<30> disp; 613 let op = 1; 614 let Inst{29-0} = disp; 615 } 616 617 // indirect calls 618 def JMPLrr : F3_1<2, 0b111000, 619 (outs), (ins MEMrr:$ptr, variable_ops), 620 "call $ptr", 621 [(call ADDRrr:$ptr)]>; 622 def JMPLri : F3_2<2, 0b111000, 623 (outs), (ins MEMri:$ptr, variable_ops), 624 "call $ptr", 625 [(call ADDRri:$ptr)]>; 626} 627 628// Section B.28 - Read State Register Instructions 629let Uses = [Y] in 630 def RDY : F3_1<2, 0b101000, 631 (outs IntRegs:$dst), (ins), 632 "rd %y, $dst", []>; 633 634// Section B.29 - Write State Register Instructions 635let Defs = [Y] in { 636 def WRYrr : F3_1<2, 0b110000, 637 (outs), (ins IntRegs:$b, IntRegs:$c), 638 "wr $b, $c, %y", []>; 639 def WRYri : F3_2<2, 0b110000, 640 (outs), (ins IntRegs:$b, i32imm:$c), 641 "wr $b, $c, %y", []>; 642} 643// Convert Integer to Floating-point Instructions, p. 141 644def FITOS : F3_3<2, 0b110100, 0b011000100, 645 (outs FPRegs:$dst), (ins FPRegs:$src), 646 "fitos $src, $dst", 647 [(set FPRegs:$dst, (SPitof FPRegs:$src))]>; 648def FITOD : F3_3<2, 0b110100, 0b011001000, 649 (outs DFPRegs:$dst), (ins FPRegs:$src), 650 "fitod $src, $dst", 651 [(set DFPRegs:$dst, (SPitof FPRegs:$src))]>; 652def FITOQ : F3_3<2, 0b110100, 0b011001100, 653 (outs QFPRegs:$dst), (ins FPRegs:$src), 654 "fitoq $src, $dst", 655 [(set QFPRegs:$dst, (SPitof FPRegs:$src))]>, 656 Requires<[HasHardQuad]>; 657 658// Convert Floating-point to Integer Instructions, p. 142 659def FSTOI : F3_3<2, 0b110100, 0b011010001, 660 (outs FPRegs:$dst), (ins FPRegs:$src), 661 "fstoi $src, $dst", 662 [(set FPRegs:$dst, (SPftoi FPRegs:$src))]>; 663def FDTOI : F3_3<2, 0b110100, 0b011010010, 664 (outs FPRegs:$dst), (ins DFPRegs:$src), 665 "fdtoi $src, $dst", 666 [(set FPRegs:$dst, (SPftoi DFPRegs:$src))]>; 667def FQTOI : F3_3<2, 0b110100, 0b011010011, 668 (outs FPRegs:$dst), (ins QFPRegs:$src), 669 "fqtoi $src, $dst", 670 [(set FPRegs:$dst, (SPftoi QFPRegs:$src))]>, 671 Requires<[HasHardQuad]>; 672 673// Convert between Floating-point Formats Instructions, p. 143 674def FSTOD : F3_3<2, 0b110100, 0b011001001, 675 (outs DFPRegs:$dst), (ins FPRegs:$src), 676 "fstod $src, $dst", 677 [(set f64:$dst, (fextend f32:$src))]>; 678def FSTOQ : F3_3<2, 0b110100, 0b011001101, 679 (outs QFPRegs:$dst), (ins FPRegs:$src), 680 "fstoq $src, $dst", 681 [(set f128:$dst, (fextend f32:$src))]>, 682 Requires<[HasHardQuad]>; 683def FDTOS : F3_3<2, 0b110100, 0b011000110, 684 (outs FPRegs:$dst), (ins DFPRegs:$src), 685 "fdtos $src, $dst", 686 [(set f32:$dst, (fround f64:$src))]>; 687def FDTOQ : F3_3<2, 0b110100, 0b01101110, 688 (outs QFPRegs:$dst), (ins DFPRegs:$src), 689 "fdtoq $src, $dst", 690 [(set f128:$dst, (fextend f64:$src))]>, 691 Requires<[HasHardQuad]>; 692def FQTOS : F3_3<2, 0b110100, 0b011000111, 693 (outs FPRegs:$dst), (ins QFPRegs:$src), 694 "fqtos $src, $dst", 695 [(set f32:$dst, (fround f128:$src))]>, 696 Requires<[HasHardQuad]>; 697def FQTOD : F3_3<2, 0b110100, 0b011001011, 698 (outs DFPRegs:$dst), (ins QFPRegs:$src), 699 "fqtod $src, $dst", 700 [(set f64:$dst, (fround f128:$src))]>, 701 Requires<[HasHardQuad]>; 702 703// Floating-point Move Instructions, p. 144 704def FMOVS : F3_3<2, 0b110100, 0b000000001, 705 (outs FPRegs:$dst), (ins FPRegs:$src), 706 "fmovs $src, $dst", []>; 707def FNEGS : F3_3<2, 0b110100, 0b000000101, 708 (outs FPRegs:$dst), (ins FPRegs:$src), 709 "fnegs $src, $dst", 710 [(set f32:$dst, (fneg f32:$src))]>; 711def FABSS : F3_3<2, 0b110100, 0b000001001, 712 (outs FPRegs:$dst), (ins FPRegs:$src), 713 "fabss $src, $dst", 714 [(set f32:$dst, (fabs f32:$src))]>; 715 716 717// Floating-point Square Root Instructions, p.145 718def FSQRTS : F3_3<2, 0b110100, 0b000101001, 719 (outs FPRegs:$dst), (ins FPRegs:$src), 720 "fsqrts $src, $dst", 721 [(set f32:$dst, (fsqrt f32:$src))]>; 722def FSQRTD : F3_3<2, 0b110100, 0b000101010, 723 (outs DFPRegs:$dst), (ins DFPRegs:$src), 724 "fsqrtd $src, $dst", 725 [(set f64:$dst, (fsqrt f64:$src))]>; 726def FSQRTQ : F3_3<2, 0b110100, 0b000101011, 727 (outs QFPRegs:$dst), (ins QFPRegs:$src), 728 "fsqrtq $src, $dst", 729 [(set f128:$dst, (fsqrt f128:$src))]>, 730 Requires<[HasHardQuad]>; 731 732 733 734// Floating-point Add and Subtract Instructions, p. 146 735def FADDS : F3_3<2, 0b110100, 0b001000001, 736 (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2), 737 "fadds $src1, $src2, $dst", 738 [(set f32:$dst, (fadd f32:$src1, f32:$src2))]>; 739def FADDD : F3_3<2, 0b110100, 0b001000010, 740 (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2), 741 "faddd $src1, $src2, $dst", 742 [(set f64:$dst, (fadd f64:$src1, f64:$src2))]>; 743def FADDQ : F3_3<2, 0b110100, 0b001000011, 744 (outs QFPRegs:$dst), (ins QFPRegs:$src1, QFPRegs:$src2), 745 "faddq $src1, $src2, $dst", 746 [(set f128:$dst, (fadd f128:$src1, f128:$src2))]>, 747 Requires<[HasHardQuad]>; 748 749def FSUBS : F3_3<2, 0b110100, 0b001000101, 750 (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2), 751 "fsubs $src1, $src2, $dst", 752 [(set f32:$dst, (fsub f32:$src1, f32:$src2))]>; 753def FSUBD : F3_3<2, 0b110100, 0b001000110, 754 (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2), 755 "fsubd $src1, $src2, $dst", 756 [(set f64:$dst, (fsub f64:$src1, f64:$src2))]>; 757def FSUBQ : F3_3<2, 0b110100, 0b001000111, 758 (outs QFPRegs:$dst), (ins QFPRegs:$src1, QFPRegs:$src2), 759 "fsubq $src1, $src2, $dst", 760 [(set f128:$dst, (fsub f128:$src1, f128:$src2))]>, 761 Requires<[HasHardQuad]>; 762 763 764// Floating-point Multiply and Divide Instructions, p. 147 765def FMULS : F3_3<2, 0b110100, 0b001001001, 766 (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2), 767 "fmuls $src1, $src2, $dst", 768 [(set f32:$dst, (fmul f32:$src1, f32:$src2))]>; 769def FMULD : F3_3<2, 0b110100, 0b001001010, 770 (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2), 771 "fmuld $src1, $src2, $dst", 772 [(set f64:$dst, (fmul f64:$src1, f64:$src2))]>; 773def FMULQ : F3_3<2, 0b110100, 0b001001011, 774 (outs QFPRegs:$dst), (ins QFPRegs:$src1, QFPRegs:$src2), 775 "fmulq $src1, $src2, $dst", 776 [(set f128:$dst, (fmul f128:$src1, f128:$src2))]>, 777 Requires<[HasHardQuad]>; 778 779def FSMULD : F3_3<2, 0b110100, 0b001101001, 780 (outs DFPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2), 781 "fsmuld $src1, $src2, $dst", 782 [(set f64:$dst, (fmul (fextend f32:$src1), 783 (fextend f32:$src2)))]>; 784def FDMULQ : F3_3<2, 0b110100, 0b001101110, 785 (outs QFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2), 786 "fdmulq $src1, $src2, $dst", 787 [(set f128:$dst, (fmul (fextend f64:$src1), 788 (fextend f64:$src2)))]>, 789 Requires<[HasHardQuad]>; 790 791def FDIVS : F3_3<2, 0b110100, 0b001001101, 792 (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2), 793 "fdivs $src1, $src2, $dst", 794 [(set f32:$dst, (fdiv f32:$src1, f32:$src2))]>; 795def FDIVD : F3_3<2, 0b110100, 0b001001110, 796 (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2), 797 "fdivd $src1, $src2, $dst", 798 [(set f64:$dst, (fdiv f64:$src1, f64:$src2))]>; 799def FDIVQ : F3_3<2, 0b110100, 0b001001111, 800 (outs QFPRegs:$dst), (ins QFPRegs:$src1, QFPRegs:$src2), 801 "fdivq $src1, $src2, $dst", 802 [(set f128:$dst, (fdiv f128:$src1, f128:$src2))]>, 803 Requires<[HasHardQuad]>; 804 805// Floating-point Compare Instructions, p. 148 806// Note: the 2nd template arg is different for these guys. 807// Note 2: the result of a FCMP is not available until the 2nd cycle 808// after the instr is retired, but there is no interlock. This behavior 809// is modelled with a forced noop after the instruction. 810let Defs = [FCC] in { 811 def FCMPS : F3_3<2, 0b110101, 0b001010001, 812 (outs), (ins FPRegs:$src1, FPRegs:$src2), 813 "fcmps $src1, $src2\n\tnop", 814 [(SPcmpfcc f32:$src1, f32:$src2)]>; 815 def FCMPD : F3_3<2, 0b110101, 0b001010010, 816 (outs), (ins DFPRegs:$src1, DFPRegs:$src2), 817 "fcmpd $src1, $src2\n\tnop", 818 [(SPcmpfcc f64:$src1, f64:$src2)]>; 819 def FCMPQ : F3_3<2, 0b110101, 0b001010011, 820 (outs), (ins QFPRegs:$src1, QFPRegs:$src2), 821 "fcmpq $src1, $src2\n\tnop", 822 [(SPcmpfcc f128:$src1, f128:$src2)]>, 823 Requires<[HasHardQuad]>; 824} 825 826//===----------------------------------------------------------------------===// 827// Instructions for Thread Local Storage(TLS). 828//===----------------------------------------------------------------------===// 829 830def TLS_ADDrr : F3_1<2, 0b000000, 831 (outs IntRegs:$rd), 832 (ins IntRegs:$rs1, IntRegs:$rs2, TLSSym:$sym), 833 "add $rs1, $rs2, $rd, $sym", 834 [(set i32:$rd, 835 (tlsadd i32:$rs1, i32:$rs2, tglobaltlsaddr:$sym))]>; 836 837let mayLoad = 1 in 838 def TLS_LDrr : F3_1<3, 0b000000, 839 (outs IntRegs:$dst), (ins MEMrr:$addr, TLSSym:$sym), 840 "ld [$addr], $dst, $sym", 841 [(set i32:$dst, 842 (tlsld ADDRrr:$addr, tglobaltlsaddr:$sym))]>; 843 844let Uses = [O6], isCall = 1 in 845 def TLS_CALL : InstSP<(outs), 846 (ins calltarget:$disp, TLSSym:$sym, variable_ops), 847 "call $disp, $sym\n\tnop", 848 [(tlscall texternalsym:$disp, tglobaltlsaddr:$sym)]> { 849 bits<30> disp; 850 let op = 1; 851 let Inst{29-0} = disp; 852} 853 854//===----------------------------------------------------------------------===// 855// V9 Instructions 856//===----------------------------------------------------------------------===// 857 858// V9 Conditional Moves. 859let Predicates = [HasV9], Constraints = "$f = $rd" in { 860 // Move Integer Register on Condition (MOVcc) p. 194 of the V9 manual. 861 // FIXME: Add instruction encodings for the JIT some day. 862 let Uses = [ICC] in { 863 def MOVICCrr 864 : Pseudo<(outs IntRegs:$rd), (ins IntRegs:$rs2, IntRegs:$f, CCOp:$cc), 865 "mov$cc %icc, $rs2, $rd", 866 [(set i32:$rd, (SPselecticc i32:$rs2, i32:$f, imm:$cc))]>; 867 def MOVICCri 868 : Pseudo<(outs IntRegs:$rd), (ins i32imm:$i, IntRegs:$f, CCOp:$cc), 869 "mov$cc %icc, $i, $rd", 870 [(set i32:$rd, (SPselecticc simm11:$i, i32:$f, imm:$cc))]>; 871 } 872 873 let Uses = [FCC] in { 874 def MOVFCCrr 875 : Pseudo<(outs IntRegs:$rd), (ins IntRegs:$rs2, IntRegs:$f, CCOp:$cc), 876 "mov$cc %fcc0, $rs2, $rd", 877 [(set i32:$rd, (SPselectfcc i32:$rs2, i32:$f, imm:$cc))]>; 878 def MOVFCCri 879 : Pseudo<(outs IntRegs:$rd), (ins i32imm:$i, IntRegs:$f, CCOp:$cc), 880 "mov$cc %fcc0, $i, $rd", 881 [(set i32:$rd, (SPselectfcc simm11:$i, i32:$f, imm:$cc))]>; 882 } 883 884 let Uses = [ICC] in { 885 def FMOVS_ICC 886 : Pseudo<(outs FPRegs:$rd), (ins FPRegs:$rs2, FPRegs:$f, CCOp:$cc), 887 "fmovs$cc %icc, $rs2, $rd", 888 [(set f32:$rd, (SPselecticc f32:$rs2, f32:$f, imm:$cc))]>; 889 def FMOVD_ICC 890 : Pseudo<(outs DFPRegs:$rd), (ins DFPRegs:$rs2, DFPRegs:$f, CCOp:$cc), 891 "fmovd$cc %icc, $rs2, $rd", 892 [(set f64:$rd, (SPselecticc f64:$rs2, f64:$f, imm:$cc))]>; 893 } 894 895 let Uses = [FCC] in { 896 def FMOVS_FCC 897 : Pseudo<(outs FPRegs:$rd), (ins FPRegs:$rs2, FPRegs:$f, CCOp:$cc), 898 "fmovs$cc %fcc0, $rs2, $rd", 899 [(set f32:$rd, (SPselectfcc f32:$rs2, f32:$f, imm:$cc))]>; 900 def FMOVD_FCC 901 : Pseudo<(outs DFPRegs:$rd), (ins DFPRegs:$rs2, DFPRegs:$f, CCOp:$cc), 902 "fmovd$cc %fcc0, $rs2, $rd", 903 [(set f64:$rd, (SPselectfcc f64:$rs2, f64:$f, imm:$cc))]>; 904 } 905 906} 907 908// Floating-Point Move Instructions, p. 164 of the V9 manual. 909let Predicates = [HasV9] in { 910 def FMOVD : F3_3<2, 0b110100, 0b000000010, 911 (outs DFPRegs:$dst), (ins DFPRegs:$src), 912 "fmovd $src, $dst", []>; 913 def FMOVQ : F3_3<2, 0b110100, 0b000000011, 914 (outs QFPRegs:$dst), (ins QFPRegs:$src), 915 "fmovq $src, $dst", []>, 916 Requires<[HasHardQuad]>; 917 def FNEGD : F3_3<2, 0b110100, 0b000000110, 918 (outs DFPRegs:$dst), (ins DFPRegs:$src), 919 "fnegd $src, $dst", 920 [(set f64:$dst, (fneg f64:$src))]>; 921 def FNEGQ : F3_3<2, 0b110100, 0b000000111, 922 (outs QFPRegs:$dst), (ins QFPRegs:$src), 923 "fnegq $src, $dst", 924 [(set f128:$dst, (fneg f128:$src))]>, 925 Requires<[HasHardQuad]>; 926 def FABSD : F3_3<2, 0b110100, 0b000001010, 927 (outs DFPRegs:$dst), (ins DFPRegs:$src), 928 "fabsd $src, $dst", 929 [(set f64:$dst, (fabs f64:$src))]>; 930 def FABSQ : F3_3<2, 0b110100, 0b000001011, 931 (outs QFPRegs:$dst), (ins QFPRegs:$src), 932 "fabsq $src, $dst", 933 [(set f128:$dst, (fabs f128:$src))]>, 934 Requires<[HasHardQuad]>; 935} 936 937// POPCrr - This does a ctpop of a 64-bit register. As such, we have to clear 938// the top 32-bits before using it. To do this clearing, we use a SLLri X,0. 939def POPCrr : F3_1<2, 0b101110, 940 (outs IntRegs:$dst), (ins IntRegs:$src), 941 "popc $src, $dst", []>, Requires<[HasV9]>; 942def : Pat<(ctpop i32:$src), 943 (POPCrr (SLLri $src, 0))>; 944 945//===----------------------------------------------------------------------===// 946// Non-Instruction Patterns 947//===----------------------------------------------------------------------===// 948 949// Small immediates. 950def : Pat<(i32 simm13:$val), 951 (ORri (i32 G0), imm:$val)>; 952// Arbitrary immediates. 953def : Pat<(i32 imm:$val), 954 (ORri (SETHIi (HI22 imm:$val)), (LO10 imm:$val))>; 955 956 957// Global addresses, constant pool entries 958def : Pat<(SPhi tglobaladdr:$in), (SETHIi tglobaladdr:$in)>; 959def : Pat<(SPlo tglobaladdr:$in), (ORri (i32 G0), tglobaladdr:$in)>; 960def : Pat<(SPhi tconstpool:$in), (SETHIi tconstpool:$in)>; 961def : Pat<(SPlo tconstpool:$in), (ORri (i32 G0), tconstpool:$in)>; 962 963// GlobalTLS addresses 964def : Pat<(SPhi tglobaltlsaddr:$in), (SETHIi tglobaltlsaddr:$in)>; 965def : Pat<(SPlo tglobaltlsaddr:$in), (ORri (i32 G0), tglobaltlsaddr:$in)>; 966def : Pat<(add (SPhi tglobaltlsaddr:$in1), (SPlo tglobaltlsaddr:$in2)), 967 (ADDri (SETHIi tglobaltlsaddr:$in1), (tglobaltlsaddr:$in2))>; 968def : Pat<(xor (SPhi tglobaltlsaddr:$in1), (SPlo tglobaltlsaddr:$in2)), 969 (XORri (SETHIi tglobaltlsaddr:$in1), (tglobaltlsaddr:$in2))>; 970 971// Blockaddress 972def : Pat<(SPhi tblockaddress:$in), (SETHIi tblockaddress:$in)>; 973def : Pat<(SPlo tblockaddress:$in), (ORri (i32 G0), tblockaddress:$in)>; 974 975// Add reg, lo. This is used when taking the addr of a global/constpool entry. 976def : Pat<(add iPTR:$r, (SPlo tglobaladdr:$in)), (ADDri $r, tglobaladdr:$in)>; 977def : Pat<(add iPTR:$r, (SPlo tconstpool:$in)), (ADDri $r, tconstpool:$in)>; 978def : Pat<(add iPTR:$r, (SPlo tblockaddress:$in)), 979 (ADDri $r, tblockaddress:$in)>; 980 981// Calls: 982def : Pat<(call tglobaladdr:$dst), 983 (CALL tglobaladdr:$dst)>; 984def : Pat<(call texternalsym:$dst), 985 (CALL texternalsym:$dst)>; 986 987// Map integer extload's to zextloads. 988def : Pat<(i32 (extloadi1 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>; 989def : Pat<(i32 (extloadi1 ADDRri:$src)), (LDUBri ADDRri:$src)>; 990def : Pat<(i32 (extloadi8 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>; 991def : Pat<(i32 (extloadi8 ADDRri:$src)), (LDUBri ADDRri:$src)>; 992def : Pat<(i32 (extloadi16 ADDRrr:$src)), (LDUHrr ADDRrr:$src)>; 993def : Pat<(i32 (extloadi16 ADDRri:$src)), (LDUHri ADDRri:$src)>; 994 995// zextload bool -> zextload byte 996def : Pat<(i32 (zextloadi1 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>; 997def : Pat<(i32 (zextloadi1 ADDRri:$src)), (LDUBri ADDRri:$src)>; 998 999// store 0, addr -> store %g0, addr 1000def : Pat<(store (i32 0), ADDRrr:$dst), (STrr ADDRrr:$dst, (i32 G0))>; 1001def : Pat<(store (i32 0), ADDRri:$dst), (STri ADDRri:$dst, (i32 G0))>; 1002 1003include "SparcInstr64Bit.td" 1004