SparcInstrInfo.td revision adaace8aa8df16f1fa2b097f32ded38a49d89208
1//===- SparcInstrInfo.td - Target Description for Sparc Target ------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the Sparc instructions in TableGen format. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// Instruction format superclass 16//===----------------------------------------------------------------------===// 17 18include "SparcInstrFormats.td" 19 20//===----------------------------------------------------------------------===// 21// Feature predicates. 22//===----------------------------------------------------------------------===// 23 24// HasV9 - This predicate is true when the target processor supports V9 25// instructions. Note that the machine may be running in 32-bit mode. 26def HasV9 : Predicate<"Subtarget.isV9()">; 27 28// HasNoV9 - This predicate is true when the target doesn't have V9 29// instructions. Use of this is just a hack for the isel not having proper 30// costs for V8 instructions that are more expensive than their V9 ones. 31def HasNoV9 : Predicate<"!Subtarget.isV9()">; 32 33// HasVIS - This is true when the target processor has VIS extensions. 34def HasVIS : Predicate<"Subtarget.isVIS()">; 35 36// UseDeprecatedInsts - This predicate is true when the target processor is a 37// V8, or when it is V9 but the V8 deprecated instructions are efficient enough 38// to use when appropriate. In either of these cases, the instruction selector 39// will pick deprecated instructions. 40def UseDeprecatedInsts : Predicate<"Subtarget.useDeprecatedV8Instructions()">; 41 42//===----------------------------------------------------------------------===// 43// Instruction Pattern Stuff 44//===----------------------------------------------------------------------===// 45 46def simm11 : PatLeaf<(imm), [{ 47 // simm11 predicate - True if the imm fits in a 11-bit sign extended field. 48 return (((int)N->getZExtValue() << (32-11)) >> (32-11)) == 49 (int)N->getZExtValue(); 50}]>; 51 52def simm13 : PatLeaf<(imm), [{ 53 // simm13 predicate - True if the imm fits in a 13-bit sign extended field. 54 return (((int)N->getZExtValue() << (32-13)) >> (32-13)) == 55 (int)N->getZExtValue(); 56}]>; 57 58def LO10 : SDNodeXForm<imm, [{ 59 return CurDAG->getTargetConstant((unsigned)N->getZExtValue() & 1023, 60 MVT::i32); 61}]>; 62 63def HI22 : SDNodeXForm<imm, [{ 64 // Transformation function: shift the immediate value down into the low bits. 65 return CurDAG->getTargetConstant((unsigned)N->getZExtValue() >> 10, MVT::i32); 66}]>; 67 68def SETHIimm : PatLeaf<(imm), [{ 69 return (((unsigned)N->getZExtValue() >> 10) << 10) == 70 (unsigned)N->getZExtValue(); 71}], HI22>; 72 73// Addressing modes. 74def ADDRrr : ComplexPattern<i32, 2, "SelectADDRrr", [], []>; 75def ADDRri : ComplexPattern<i32, 2, "SelectADDRri", [frameindex], []>; 76 77// Address operands 78def MEMrr : Operand<i32> { 79 let PrintMethod = "printMemOperand"; 80 let MIOperandInfo = (ops IntRegs, IntRegs); 81} 82def MEMri : Operand<i32> { 83 let PrintMethod = "printMemOperand"; 84 let MIOperandInfo = (ops IntRegs, i32imm); 85} 86 87// Branch targets have OtherVT type. 88def brtarget : Operand<OtherVT>; 89def calltarget : Operand<i32>; 90 91// Operand for printing out a condition code. 92let PrintMethod = "printCCOperand" in 93 def CCOp : Operand<i32>; 94 95def SDTSPcmpfcc : 96SDTypeProfile<0, 2, [SDTCisFP<0>, SDTCisSameAs<0, 1>]>; 97def SDTSPbrcc : 98SDTypeProfile<0, 2, [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>; 99def SDTSPselectcc : 100SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>]>; 101def SDTSPFTOI : 102SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisFP<1>]>; 103def SDTSPITOF : 104SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f32>]>; 105 106def SPcmpicc : SDNode<"SPISD::CMPICC", SDTIntBinOp, [SDNPOutFlag]>; 107def SPcmpfcc : SDNode<"SPISD::CMPFCC", SDTSPcmpfcc, [SDNPOutFlag]>; 108def SPbricc : SDNode<"SPISD::BRICC", SDTSPbrcc, [SDNPHasChain, SDNPInFlag]>; 109def SPbrfcc : SDNode<"SPISD::BRFCC", SDTSPbrcc, [SDNPHasChain, SDNPInFlag]>; 110 111def SPhi : SDNode<"SPISD::Hi", SDTIntUnaryOp>; 112def SPlo : SDNode<"SPISD::Lo", SDTIntUnaryOp>; 113 114def SPftoi : SDNode<"SPISD::FTOI", SDTSPFTOI>; 115def SPitof : SDNode<"SPISD::ITOF", SDTSPITOF>; 116 117def SPselecticc : SDNode<"SPISD::SELECT_ICC", SDTSPselectcc, [SDNPInFlag]>; 118def SPselectfcc : SDNode<"SPISD::SELECT_FCC", SDTSPselectcc, [SDNPInFlag]>; 119 120// These are target-independent nodes, but have target-specific formats. 121def SDT_SPCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>; 122def SDT_SPCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, 123 SDTCisVT<1, i32> ]>; 124 125def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_SPCallSeqStart, 126 [SDNPHasChain, SDNPOutFlag]>; 127def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_SPCallSeqEnd, 128 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; 129 130def SDT_SPCall : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>; 131def call : SDNode<"SPISD::CALL", SDT_SPCall, 132 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; 133 134def retflag : SDNode<"SPISD::RET_FLAG", SDTNone, 135 [SDNPHasChain, SDNPOptInFlag]>; 136 137def getPCX : Operand<i32> { 138 let PrintMethod = "printGetPCX"; 139} 140 141//===----------------------------------------------------------------------===// 142// SPARC Flag Conditions 143//===----------------------------------------------------------------------===// 144 145// Note that these values must be kept in sync with the CCOp::CondCode enum 146// values. 147class ICC_VAL<int N> : PatLeaf<(i32 N)>; 148def ICC_NE : ICC_VAL< 9>; // Not Equal 149def ICC_E : ICC_VAL< 1>; // Equal 150def ICC_G : ICC_VAL<10>; // Greater 151def ICC_LE : ICC_VAL< 2>; // Less or Equal 152def ICC_GE : ICC_VAL<11>; // Greater or Equal 153def ICC_L : ICC_VAL< 3>; // Less 154def ICC_GU : ICC_VAL<12>; // Greater Unsigned 155def ICC_LEU : ICC_VAL< 4>; // Less or Equal Unsigned 156def ICC_CC : ICC_VAL<13>; // Carry Clear/Great or Equal Unsigned 157def ICC_CS : ICC_VAL< 5>; // Carry Set/Less Unsigned 158def ICC_POS : ICC_VAL<14>; // Positive 159def ICC_NEG : ICC_VAL< 6>; // Negative 160def ICC_VC : ICC_VAL<15>; // Overflow Clear 161def ICC_VS : ICC_VAL< 7>; // Overflow Set 162 163class FCC_VAL<int N> : PatLeaf<(i32 N)>; 164def FCC_U : FCC_VAL<23>; // Unordered 165def FCC_G : FCC_VAL<22>; // Greater 166def FCC_UG : FCC_VAL<21>; // Unordered or Greater 167def FCC_L : FCC_VAL<20>; // Less 168def FCC_UL : FCC_VAL<19>; // Unordered or Less 169def FCC_LG : FCC_VAL<18>; // Less or Greater 170def FCC_NE : FCC_VAL<17>; // Not Equal 171def FCC_E : FCC_VAL<25>; // Equal 172def FCC_UE : FCC_VAL<24>; // Unordered or Equal 173def FCC_GE : FCC_VAL<25>; // Greater or Equal 174def FCC_UGE : FCC_VAL<26>; // Unordered or Greater or Equal 175def FCC_LE : FCC_VAL<27>; // Less or Equal 176def FCC_ULE : FCC_VAL<28>; // Unordered or Less or Equal 177def FCC_O : FCC_VAL<29>; // Ordered 178 179//===----------------------------------------------------------------------===// 180// Instruction Class Templates 181//===----------------------------------------------------------------------===// 182 183/// F3_12 multiclass - Define a normal F3_1/F3_2 pattern in one shot. 184multiclass F3_12<string OpcStr, bits<6> Op3Val, SDNode OpNode> { 185 def rr : F3_1<2, Op3Val, 186 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c), 187 !strconcat(OpcStr, " $b, $c, $dst"), 188 [(set IntRegs:$dst, (OpNode IntRegs:$b, IntRegs:$c))]>; 189 def ri : F3_2<2, Op3Val, 190 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c), 191 !strconcat(OpcStr, " $b, $c, $dst"), 192 [(set IntRegs:$dst, (OpNode IntRegs:$b, simm13:$c))]>; 193} 194 195/// F3_12np multiclass - Define a normal F3_1/F3_2 pattern in one shot, with no 196/// pattern. 197multiclass F3_12np<string OpcStr, bits<6> Op3Val> { 198 def rr : F3_1<2, Op3Val, 199 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c), 200 !strconcat(OpcStr, " $b, $c, $dst"), []>; 201 def ri : F3_2<2, Op3Val, 202 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c), 203 !strconcat(OpcStr, " $b, $c, $dst"), []>; 204} 205 206//===----------------------------------------------------------------------===// 207// Instructions 208//===----------------------------------------------------------------------===// 209 210// Pseudo instructions. 211class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern> 212 : InstSP<outs, ins, asmstr, pattern>; 213 214// GETPCX for PIC 215let Defs = [O7], Uses = [O7] in { 216 def GETPCX : Pseudo<(outs getPCX:$getpcseq), (ins), "$getpcseq", [] >; 217} 218 219let Defs = [O6], Uses = [O6] in { 220def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt), 221 "!ADJCALLSTACKDOWN $amt", 222 [(callseq_start timm:$amt)]>; 223def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2), 224 "!ADJCALLSTACKUP $amt1", 225 [(callseq_end timm:$amt1, timm:$amt2)]>; 226} 227 228// FpMOVD/FpNEGD/FpABSD - These are lowered to single-precision ops by the 229// fpmover pass. 230let Predicates = [HasNoV9] in { // Only emit these in V8 mode. 231 def FpMOVD : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$src), 232 "!FpMOVD $src, $dst", []>; 233 def FpNEGD : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$src), 234 "!FpNEGD $src, $dst", 235 [(set DFPRegs:$dst, (fneg DFPRegs:$src))]>; 236 def FpABSD : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$src), 237 "!FpABSD $src, $dst", 238 [(set DFPRegs:$dst, (fabs DFPRegs:$src))]>; 239} 240 241// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after 242// instruction selection into a branch sequence. This has to handle all 243// permutations of selection between i32/f32/f64 on ICC and FCC. 244let usesCustomInserter = 1 in { // Expanded after instruction selection. 245 def SELECT_CC_Int_ICC 246 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond), 247 "; SELECT_CC_Int_ICC PSEUDO!", 248 [(set IntRegs:$dst, (SPselecticc IntRegs:$T, IntRegs:$F, 249 imm:$Cond))]>; 250 def SELECT_CC_Int_FCC 251 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond), 252 "; SELECT_CC_Int_FCC PSEUDO!", 253 [(set IntRegs:$dst, (SPselectfcc IntRegs:$T, IntRegs:$F, 254 imm:$Cond))]>; 255 def SELECT_CC_FP_ICC 256 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, i32imm:$Cond), 257 "; SELECT_CC_FP_ICC PSEUDO!", 258 [(set FPRegs:$dst, (SPselecticc FPRegs:$T, FPRegs:$F, 259 imm:$Cond))]>; 260 def SELECT_CC_FP_FCC 261 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, i32imm:$Cond), 262 "; SELECT_CC_FP_FCC PSEUDO!", 263 [(set FPRegs:$dst, (SPselectfcc FPRegs:$T, FPRegs:$F, 264 imm:$Cond))]>; 265 def SELECT_CC_DFP_ICC 266 : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, i32imm:$Cond), 267 "; SELECT_CC_DFP_ICC PSEUDO!", 268 [(set DFPRegs:$dst, (SPselecticc DFPRegs:$T, DFPRegs:$F, 269 imm:$Cond))]>; 270 def SELECT_CC_DFP_FCC 271 : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, i32imm:$Cond), 272 "; SELECT_CC_DFP_FCC PSEUDO!", 273 [(set DFPRegs:$dst, (SPselectfcc DFPRegs:$T, DFPRegs:$F, 274 imm:$Cond))]>; 275} 276 277 278// Section A.3 - Synthetic Instructions, p. 85 279// special cases of JMPL: 280let isReturn = 1, isTerminator = 1, hasDelaySlot = 1, isBarrier = 1 in { 281 let rd = O7.Num, rs1 = G0.Num, simm13 = 8 in 282 def RETL: F3_2<2, 0b111000, (outs), (ins), "retl", [(retflag)]>; 283} 284 285// Section B.1 - Load Integer Instructions, p. 90 286def LDSBrr : F3_1<3, 0b001001, 287 (outs IntRegs:$dst), (ins MEMrr:$addr), 288 "ldsb [$addr], $dst", 289 [(set IntRegs:$dst, (sextloadi8 ADDRrr:$addr))]>; 290def LDSBri : F3_2<3, 0b001001, 291 (outs IntRegs:$dst), (ins MEMri:$addr), 292 "ldsb [$addr], $dst", 293 [(set IntRegs:$dst, (sextloadi8 ADDRri:$addr))]>; 294def LDSHrr : F3_1<3, 0b001010, 295 (outs IntRegs:$dst), (ins MEMrr:$addr), 296 "ldsh [$addr], $dst", 297 [(set IntRegs:$dst, (sextloadi16 ADDRrr:$addr))]>; 298def LDSHri : F3_2<3, 0b001010, 299 (outs IntRegs:$dst), (ins MEMri:$addr), 300 "ldsh [$addr], $dst", 301 [(set IntRegs:$dst, (sextloadi16 ADDRri:$addr))]>; 302def LDUBrr : F3_1<3, 0b000001, 303 (outs IntRegs:$dst), (ins MEMrr:$addr), 304 "ldub [$addr], $dst", 305 [(set IntRegs:$dst, (zextloadi8 ADDRrr:$addr))]>; 306def LDUBri : F3_2<3, 0b000001, 307 (outs IntRegs:$dst), (ins MEMri:$addr), 308 "ldub [$addr], $dst", 309 [(set IntRegs:$dst, (zextloadi8 ADDRri:$addr))]>; 310def LDUHrr : F3_1<3, 0b000010, 311 (outs IntRegs:$dst), (ins MEMrr:$addr), 312 "lduh [$addr], $dst", 313 [(set IntRegs:$dst, (zextloadi16 ADDRrr:$addr))]>; 314def LDUHri : F3_2<3, 0b000010, 315 (outs IntRegs:$dst), (ins MEMri:$addr), 316 "lduh [$addr], $dst", 317 [(set IntRegs:$dst, (zextloadi16 ADDRri:$addr))]>; 318def LDrr : F3_1<3, 0b000000, 319 (outs IntRegs:$dst), (ins MEMrr:$addr), 320 "ld [$addr], $dst", 321 [(set IntRegs:$dst, (load ADDRrr:$addr))]>; 322def LDri : F3_2<3, 0b000000, 323 (outs IntRegs:$dst), (ins MEMri:$addr), 324 "ld [$addr], $dst", 325 [(set IntRegs:$dst, (load ADDRri:$addr))]>; 326 327// Section B.2 - Load Floating-point Instructions, p. 92 328def LDFrr : F3_1<3, 0b100000, 329 (outs FPRegs:$dst), (ins MEMrr:$addr), 330 "ld [$addr], $dst", 331 [(set FPRegs:$dst, (load ADDRrr:$addr))]>; 332def LDFri : F3_2<3, 0b100000, 333 (outs FPRegs:$dst), (ins MEMri:$addr), 334 "ld [$addr], $dst", 335 [(set FPRegs:$dst, (load ADDRri:$addr))]>; 336def LDDFrr : F3_1<3, 0b100011, 337 (outs DFPRegs:$dst), (ins MEMrr:$addr), 338 "ldd [$addr], $dst", 339 [(set DFPRegs:$dst, (load ADDRrr:$addr))]>; 340def LDDFri : F3_2<3, 0b100011, 341 (outs DFPRegs:$dst), (ins MEMri:$addr), 342 "ldd [$addr], $dst", 343 [(set DFPRegs:$dst, (load ADDRri:$addr))]>; 344 345// Section B.4 - Store Integer Instructions, p. 95 346def STBrr : F3_1<3, 0b000101, 347 (outs), (ins MEMrr:$addr, IntRegs:$src), 348 "stb $src, [$addr]", 349 [(truncstorei8 IntRegs:$src, ADDRrr:$addr)]>; 350def STBri : F3_2<3, 0b000101, 351 (outs), (ins MEMri:$addr, IntRegs:$src), 352 "stb $src, [$addr]", 353 [(truncstorei8 IntRegs:$src, ADDRri:$addr)]>; 354def STHrr : F3_1<3, 0b000110, 355 (outs), (ins MEMrr:$addr, IntRegs:$src), 356 "sth $src, [$addr]", 357 [(truncstorei16 IntRegs:$src, ADDRrr:$addr)]>; 358def STHri : F3_2<3, 0b000110, 359 (outs), (ins MEMri:$addr, IntRegs:$src), 360 "sth $src, [$addr]", 361 [(truncstorei16 IntRegs:$src, ADDRri:$addr)]>; 362def STrr : F3_1<3, 0b000100, 363 (outs), (ins MEMrr:$addr, IntRegs:$src), 364 "st $src, [$addr]", 365 [(store IntRegs:$src, ADDRrr:$addr)]>; 366def STri : F3_2<3, 0b000100, 367 (outs), (ins MEMri:$addr, IntRegs:$src), 368 "st $src, [$addr]", 369 [(store IntRegs:$src, ADDRri:$addr)]>; 370 371// Section B.5 - Store Floating-point Instructions, p. 97 372def STFrr : F3_1<3, 0b100100, 373 (outs), (ins MEMrr:$addr, FPRegs:$src), 374 "st $src, [$addr]", 375 [(store FPRegs:$src, ADDRrr:$addr)]>; 376def STFri : F3_2<3, 0b100100, 377 (outs), (ins MEMri:$addr, FPRegs:$src), 378 "st $src, [$addr]", 379 [(store FPRegs:$src, ADDRri:$addr)]>; 380def STDFrr : F3_1<3, 0b100111, 381 (outs), (ins MEMrr:$addr, DFPRegs:$src), 382 "std $src, [$addr]", 383 [(store DFPRegs:$src, ADDRrr:$addr)]>; 384def STDFri : F3_2<3, 0b100111, 385 (outs), (ins MEMri:$addr, DFPRegs:$src), 386 "std $src, [$addr]", 387 [(store DFPRegs:$src, ADDRri:$addr)]>; 388 389// Section B.9 - SETHI Instruction, p. 104 390def SETHIi: F2_1<0b100, 391 (outs IntRegs:$dst), (ins i32imm:$src), 392 "sethi $src, $dst", 393 [(set IntRegs:$dst, SETHIimm:$src)]>; 394 395// Section B.10 - NOP Instruction, p. 105 396// (It's a special case of SETHI) 397let rd = 0, imm22 = 0 in 398 def NOP : F2_1<0b100, (outs), (ins), "nop", []>; 399 400// Section B.11 - Logical Instructions, p. 106 401defm AND : F3_12<"and", 0b000001, and>; 402 403def ANDNrr : F3_1<2, 0b000101, 404 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c), 405 "andn $b, $c, $dst", 406 [(set IntRegs:$dst, (and IntRegs:$b, (not IntRegs:$c)))]>; 407def ANDNri : F3_2<2, 0b000101, 408 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c), 409 "andn $b, $c, $dst", []>; 410 411defm OR : F3_12<"or", 0b000010, or>; 412 413def ORNrr : F3_1<2, 0b000110, 414 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c), 415 "orn $b, $c, $dst", 416 [(set IntRegs:$dst, (or IntRegs:$b, (not IntRegs:$c)))]>; 417def ORNri : F3_2<2, 0b000110, 418 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c), 419 "orn $b, $c, $dst", []>; 420defm XOR : F3_12<"xor", 0b000011, xor>; 421 422def XNORrr : F3_1<2, 0b000111, 423 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c), 424 "xnor $b, $c, $dst", 425 [(set IntRegs:$dst, (not (xor IntRegs:$b, IntRegs:$c)))]>; 426def XNORri : F3_2<2, 0b000111, 427 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c), 428 "xnor $b, $c, $dst", []>; 429 430// Section B.12 - Shift Instructions, p. 107 431defm SLL : F3_12<"sll", 0b100101, shl>; 432defm SRL : F3_12<"srl", 0b100110, srl>; 433defm SRA : F3_12<"sra", 0b100111, sra>; 434 435// Section B.13 - Add Instructions, p. 108 436defm ADD : F3_12<"add", 0b000000, add>; 437 438// "LEA" forms of add (patterns to make tblgen happy) 439def LEA_ADDri : F3_2<2, 0b000000, 440 (outs IntRegs:$dst), (ins MEMri:$addr), 441 "add ${addr:arith}, $dst", 442 [(set IntRegs:$dst, ADDRri:$addr)]>; 443 444let Defs = [ICC] in 445 defm ADDCC : F3_12<"addcc", 0b010000, addc>; 446 447defm ADDX : F3_12<"addx", 0b001000, adde>; 448 449// Section B.15 - Subtract Instructions, p. 110 450defm SUB : F3_12 <"sub" , 0b000100, sub>; 451defm SUBX : F3_12 <"subx" , 0b001100, sube>; 452 453let Defs = [ICC] in { 454 defm SUBCC : F3_12 <"subcc", 0b010100, SPcmpicc>; 455 456 def SUBXCCrr: F3_1<2, 0b011100, 457 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c), 458 "subxcc $b, $c, $dst", []>; 459} 460 461// Section B.18 - Multiply Instructions, p. 113 462defm UMUL : F3_12np<"umul", 0b001010>; 463defm SMUL : F3_12 <"smul", 0b001011, mul>; 464 465 466// Section B.19 - Divide Instructions, p. 115 467defm UDIV : F3_12np<"udiv", 0b001110>; 468defm SDIV : F3_12np<"sdiv", 0b001111>; 469 470// Section B.20 - SAVE and RESTORE, p. 117 471defm SAVE : F3_12np<"save" , 0b111100>; 472defm RESTORE : F3_12np<"restore", 0b111101>; 473 474// Section B.21 - Branch on Integer Condition Codes Instructions, p. 119 475 476// conditional branch class: 477class BranchSP<bits<4> cc, dag ins, string asmstr, list<dag> pattern> 478 : F2_2<cc, 0b010, (outs), ins, asmstr, pattern> { 479 let isBranch = 1; 480 let isTerminator = 1; 481 let hasDelaySlot = 1; 482} 483 484let isBarrier = 1 in 485 def BA : BranchSP<0b1000, (ins brtarget:$dst), 486 "ba $dst", 487 [(br bb:$dst)]>; 488 489// FIXME: the encoding for the JIT should look at the condition field. 490let Uses = [ICC] in 491 def BCOND : BranchSP<0, (ins brtarget:$dst, CCOp:$cc), 492 "b$cc $dst", 493 [(SPbricc bb:$dst, imm:$cc)]>; 494 495 496// Section B.22 - Branch on Floating-point Condition Codes Instructions, p. 121 497 498// floating-point conditional branch class: 499class FPBranchSP<bits<4> cc, dag ins, string asmstr, list<dag> pattern> 500 : F2_2<cc, 0b110, (outs), ins, asmstr, pattern> { 501 let isBranch = 1; 502 let isTerminator = 1; 503 let hasDelaySlot = 1; 504} 505 506// FIXME: the encoding for the JIT should look at the condition field. 507let Uses = [FCC] in 508 def FBCOND : FPBranchSP<0, (ins brtarget:$dst, CCOp:$cc), 509 "fb$cc $dst", 510 [(SPbrfcc bb:$dst, imm:$cc)]>; 511 512 513// Section B.24 - Call and Link Instruction, p. 125 514// This is the only Format 1 instruction 515let Uses = [O0, O1, O2, O3, O4, O5], 516 hasDelaySlot = 1, isCall = 1, 517 Defs = [O0, O1, O2, O3, O4, O5, O7, G1, G2, G3, G4, G5, G6, G7, 518 D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15] in { 519 def CALL : InstSP<(outs), (ins calltarget:$dst), 520 "call $dst", []> { 521 bits<30> disp; 522 let op = 1; 523 let Inst{29-0} = disp; 524 } 525 526 // indirect calls 527 def JMPLrr : F3_1<2, 0b111000, 528 (outs), (ins MEMrr:$ptr), 529 "call $ptr", 530 [(call ADDRrr:$ptr)]>; 531 def JMPLri : F3_2<2, 0b111000, 532 (outs), (ins MEMri:$ptr), 533 "call $ptr", 534 [(call ADDRri:$ptr)]>; 535} 536 537// Section B.28 - Read State Register Instructions 538def RDY : F3_1<2, 0b101000, 539 (outs IntRegs:$dst), (ins), 540 "rd %y, $dst", []>; 541 542// Section B.29 - Write State Register Instructions 543def WRYrr : F3_1<2, 0b110000, 544 (outs), (ins IntRegs:$b, IntRegs:$c), 545 "wr $b, $c, %y", []>; 546def WRYri : F3_2<2, 0b110000, 547 (outs), (ins IntRegs:$b, i32imm:$c), 548 "wr $b, $c, %y", []>; 549 550// Convert Integer to Floating-point Instructions, p. 141 551def FITOS : F3_3<2, 0b110100, 0b011000100, 552 (outs FPRegs:$dst), (ins FPRegs:$src), 553 "fitos $src, $dst", 554 [(set FPRegs:$dst, (SPitof FPRegs:$src))]>; 555def FITOD : F3_3<2, 0b110100, 0b011001000, 556 (outs DFPRegs:$dst), (ins FPRegs:$src), 557 "fitod $src, $dst", 558 [(set DFPRegs:$dst, (SPitof FPRegs:$src))]>; 559 560// Convert Floating-point to Integer Instructions, p. 142 561def FSTOI : F3_3<2, 0b110100, 0b011010001, 562 (outs FPRegs:$dst), (ins FPRegs:$src), 563 "fstoi $src, $dst", 564 [(set FPRegs:$dst, (SPftoi FPRegs:$src))]>; 565def FDTOI : F3_3<2, 0b110100, 0b011010010, 566 (outs FPRegs:$dst), (ins DFPRegs:$src), 567 "fdtoi $src, $dst", 568 [(set FPRegs:$dst, (SPftoi DFPRegs:$src))]>; 569 570// Convert between Floating-point Formats Instructions, p. 143 571def FSTOD : F3_3<2, 0b110100, 0b011001001, 572 (outs DFPRegs:$dst), (ins FPRegs:$src), 573 "fstod $src, $dst", 574 [(set DFPRegs:$dst, (fextend FPRegs:$src))]>; 575def FDTOS : F3_3<2, 0b110100, 0b011000110, 576 (outs FPRegs:$dst), (ins DFPRegs:$src), 577 "fdtos $src, $dst", 578 [(set FPRegs:$dst, (fround DFPRegs:$src))]>; 579 580// Floating-point Move Instructions, p. 144 581def FMOVS : F3_3<2, 0b110100, 0b000000001, 582 (outs FPRegs:$dst), (ins FPRegs:$src), 583 "fmovs $src, $dst", []>; 584def FNEGS : F3_3<2, 0b110100, 0b000000101, 585 (outs FPRegs:$dst), (ins FPRegs:$src), 586 "fnegs $src, $dst", 587 [(set FPRegs:$dst, (fneg FPRegs:$src))]>; 588def FABSS : F3_3<2, 0b110100, 0b000001001, 589 (outs FPRegs:$dst), (ins FPRegs:$src), 590 "fabss $src, $dst", 591 [(set FPRegs:$dst, (fabs FPRegs:$src))]>; 592 593 594// Floating-point Square Root Instructions, p.145 595def FSQRTS : F3_3<2, 0b110100, 0b000101001, 596 (outs FPRegs:$dst), (ins FPRegs:$src), 597 "fsqrts $src, $dst", 598 [(set FPRegs:$dst, (fsqrt FPRegs:$src))]>; 599def FSQRTD : F3_3<2, 0b110100, 0b000101010, 600 (outs DFPRegs:$dst), (ins DFPRegs:$src), 601 "fsqrtd $src, $dst", 602 [(set DFPRegs:$dst, (fsqrt DFPRegs:$src))]>; 603 604 605 606// Floating-point Add and Subtract Instructions, p. 146 607def FADDS : F3_3<2, 0b110100, 0b001000001, 608 (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2), 609 "fadds $src1, $src2, $dst", 610 [(set FPRegs:$dst, (fadd FPRegs:$src1, FPRegs:$src2))]>; 611def FADDD : F3_3<2, 0b110100, 0b001000010, 612 (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2), 613 "faddd $src1, $src2, $dst", 614 [(set DFPRegs:$dst, (fadd DFPRegs:$src1, DFPRegs:$src2))]>; 615def FSUBS : F3_3<2, 0b110100, 0b001000101, 616 (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2), 617 "fsubs $src1, $src2, $dst", 618 [(set FPRegs:$dst, (fsub FPRegs:$src1, FPRegs:$src2))]>; 619def FSUBD : F3_3<2, 0b110100, 0b001000110, 620 (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2), 621 "fsubd $src1, $src2, $dst", 622 [(set DFPRegs:$dst, (fsub DFPRegs:$src1, DFPRegs:$src2))]>; 623 624// Floating-point Multiply and Divide Instructions, p. 147 625def FMULS : F3_3<2, 0b110100, 0b001001001, 626 (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2), 627 "fmuls $src1, $src2, $dst", 628 [(set FPRegs:$dst, (fmul FPRegs:$src1, FPRegs:$src2))]>; 629def FMULD : F3_3<2, 0b110100, 0b001001010, 630 (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2), 631 "fmuld $src1, $src2, $dst", 632 [(set DFPRegs:$dst, (fmul DFPRegs:$src1, DFPRegs:$src2))]>; 633def FSMULD : F3_3<2, 0b110100, 0b001101001, 634 (outs DFPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2), 635 "fsmuld $src1, $src2, $dst", 636 [(set DFPRegs:$dst, (fmul (fextend FPRegs:$src1), 637 (fextend FPRegs:$src2)))]>; 638def FDIVS : F3_3<2, 0b110100, 0b001001101, 639 (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2), 640 "fdivs $src1, $src2, $dst", 641 [(set FPRegs:$dst, (fdiv FPRegs:$src1, FPRegs:$src2))]>; 642def FDIVD : F3_3<2, 0b110100, 0b001001110, 643 (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2), 644 "fdivd $src1, $src2, $dst", 645 [(set DFPRegs:$dst, (fdiv DFPRegs:$src1, DFPRegs:$src2))]>; 646 647// Floating-point Compare Instructions, p. 148 648// Note: the 2nd template arg is different for these guys. 649// Note 2: the result of a FCMP is not available until the 2nd cycle 650// after the instr is retired, but there is no interlock. This behavior 651// is modelled with a forced noop after the instruction. 652let Defs = [FCC] in { 653 def FCMPS : F3_3<2, 0b110101, 0b001010001, 654 (outs), (ins FPRegs:$src1, FPRegs:$src2), 655 "fcmps $src1, $src2\n\tnop", 656 [(SPcmpfcc FPRegs:$src1, FPRegs:$src2)]>; 657 def FCMPD : F3_3<2, 0b110101, 0b001010010, 658 (outs), (ins DFPRegs:$src1, DFPRegs:$src2), 659 "fcmpd $src1, $src2\n\tnop", 660 [(SPcmpfcc DFPRegs:$src1, DFPRegs:$src2)]>; 661} 662 663//===----------------------------------------------------------------------===// 664// V9 Instructions 665//===----------------------------------------------------------------------===// 666 667// V9 Conditional Moves. 668let Predicates = [HasV9], isTwoAddress = 1 in { 669 // Move Integer Register on Condition (MOVcc) p. 194 of the V9 manual. 670 // FIXME: Add instruction encodings for the JIT some day. 671 def MOVICCrr 672 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, CCOp:$cc), 673 "mov$cc %icc, $F, $dst", 674 [(set IntRegs:$dst, 675 (SPselecticc IntRegs:$F, IntRegs:$T, imm:$cc))]>; 676 def MOVICCri 677 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, i32imm:$F, CCOp:$cc), 678 "mov$cc %icc, $F, $dst", 679 [(set IntRegs:$dst, 680 (SPselecticc simm11:$F, IntRegs:$T, imm:$cc))]>; 681 682 def MOVFCCrr 683 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, CCOp:$cc), 684 "mov$cc %fcc0, $F, $dst", 685 [(set IntRegs:$dst, 686 (SPselectfcc IntRegs:$F, IntRegs:$T, imm:$cc))]>; 687 def MOVFCCri 688 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, i32imm:$F, CCOp:$cc), 689 "mov$cc %fcc0, $F, $dst", 690 [(set IntRegs:$dst, 691 (SPselectfcc simm11:$F, IntRegs:$T, imm:$cc))]>; 692 693 def FMOVS_ICC 694 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, CCOp:$cc), 695 "fmovs$cc %icc, $F, $dst", 696 [(set FPRegs:$dst, 697 (SPselecticc FPRegs:$F, FPRegs:$T, imm:$cc))]>; 698 def FMOVD_ICC 699 : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, CCOp:$cc), 700 "fmovd$cc %icc, $F, $dst", 701 [(set DFPRegs:$dst, 702 (SPselecticc DFPRegs:$F, DFPRegs:$T, imm:$cc))]>; 703 def FMOVS_FCC 704 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, CCOp:$cc), 705 "fmovs$cc %fcc0, $F, $dst", 706 [(set FPRegs:$dst, 707 (SPselectfcc FPRegs:$F, FPRegs:$T, imm:$cc))]>; 708 def FMOVD_FCC 709 : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, CCOp:$cc), 710 "fmovd$cc %fcc0, $F, $dst", 711 [(set DFPRegs:$dst, 712 (SPselectfcc DFPRegs:$F, DFPRegs:$T, imm:$cc))]>; 713 714} 715 716// Floating-Point Move Instructions, p. 164 of the V9 manual. 717let Predicates = [HasV9] in { 718 def FMOVD : F3_3<2, 0b110100, 0b000000010, 719 (outs DFPRegs:$dst), (ins DFPRegs:$src), 720 "fmovd $src, $dst", []>; 721 def FNEGD : F3_3<2, 0b110100, 0b000000110, 722 (outs DFPRegs:$dst), (ins DFPRegs:$src), 723 "fnegd $src, $dst", 724 [(set DFPRegs:$dst, (fneg DFPRegs:$src))]>; 725 def FABSD : F3_3<2, 0b110100, 0b000001010, 726 (outs DFPRegs:$dst), (ins DFPRegs:$src), 727 "fabsd $src, $dst", 728 [(set DFPRegs:$dst, (fabs DFPRegs:$src))]>; 729} 730 731// POPCrr - This does a ctpop of a 64-bit register. As such, we have to clear 732// the top 32-bits before using it. To do this clearing, we use a SLLri X,0. 733def POPCrr : F3_1<2, 0b101110, 734 (outs IntRegs:$dst), (ins IntRegs:$src), 735 "popc $src, $dst", []>, Requires<[HasV9]>; 736def : Pat<(ctpop IntRegs:$src), 737 (POPCrr (SLLri IntRegs:$src, 0))>; 738 739//===----------------------------------------------------------------------===// 740// Non-Instruction Patterns 741//===----------------------------------------------------------------------===// 742 743// Small immediates. 744def : Pat<(i32 simm13:$val), 745 (ORri G0, imm:$val)>; 746// Arbitrary immediates. 747def : Pat<(i32 imm:$val), 748 (ORri (SETHIi (HI22 imm:$val)), (LO10 imm:$val))>; 749 750// subc 751def : Pat<(subc IntRegs:$b, IntRegs:$c), 752 (SUBCCrr IntRegs:$b, IntRegs:$c)>; 753def : Pat<(subc IntRegs:$b, simm13:$val), 754 (SUBCCri IntRegs:$b, imm:$val)>; 755 756// Global addresses, constant pool entries 757def : Pat<(SPhi tglobaladdr:$in), (SETHIi tglobaladdr:$in)>; 758def : Pat<(SPlo tglobaladdr:$in), (ORri G0, tglobaladdr:$in)>; 759def : Pat<(SPhi tconstpool:$in), (SETHIi tconstpool:$in)>; 760def : Pat<(SPlo tconstpool:$in), (ORri G0, tconstpool:$in)>; 761 762// Add reg, lo. This is used when taking the addr of a global/constpool entry. 763def : Pat<(add IntRegs:$r, (SPlo tglobaladdr:$in)), 764 (ADDri IntRegs:$r, tglobaladdr:$in)>; 765def : Pat<(add IntRegs:$r, (SPlo tconstpool:$in)), 766 (ADDri IntRegs:$r, tconstpool:$in)>; 767 768// Calls: 769def : Pat<(call tglobaladdr:$dst), 770 (CALL tglobaladdr:$dst)>; 771def : Pat<(call texternalsym:$dst), 772 (CALL texternalsym:$dst)>; 773 774// Map integer extload's to zextloads. 775def : Pat<(i32 (extloadi1 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>; 776def : Pat<(i32 (extloadi1 ADDRri:$src)), (LDUBri ADDRri:$src)>; 777def : Pat<(i32 (extloadi8 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>; 778def : Pat<(i32 (extloadi8 ADDRri:$src)), (LDUBri ADDRri:$src)>; 779def : Pat<(i32 (extloadi16 ADDRrr:$src)), (LDUHrr ADDRrr:$src)>; 780def : Pat<(i32 (extloadi16 ADDRri:$src)), (LDUHri ADDRri:$src)>; 781 782// zextload bool -> zextload byte 783def : Pat<(i32 (zextloadi1 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>; 784def : Pat<(i32 (zextloadi1 ADDRri:$src)), (LDUBri ADDRri:$src)>; 785