SparcInstrInfo.td revision b354b7148eadcd5d30ceac80a2ddc1bbdfffbaef
1//===- SparcV8Instrs.td - Target Description for SparcV8 Target -----------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the SparcV8 instructions in TableGen format. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// Instruction format superclass 16//===----------------------------------------------------------------------===// 17 18class InstV8 : Instruction { // SparcV8 instruction baseline 19 field bits<32> Inst; 20 21 let Namespace = "V8"; 22 23 bits<2> op; 24 let Inst{31-30} = op; // Top two bits are the 'op' field 25 26 // Bit attributes specific to SparcV8 instructions 27 bit isPasi = 0; // Does this instruction affect an alternate addr space? 28 bit isPrivileged = 0; // Is this a privileged instruction? 29} 30 31include "SparcV8InstrFormats.td" 32 33//===----------------------------------------------------------------------===// 34// Instructions 35//===----------------------------------------------------------------------===// 36 37// Pseudo instructions. 38class PseudoInstV8<string nm> : InstV8 { 39 let Name = nm; 40} 41def PHI : PseudoInstV8<"PHI">; 42def ADJCALLSTACKDOWN : PseudoInstV8<"ADJCALLSTACKDOWN">; 43def ADJCALLSTACKUP : PseudoInstV8<"ADJCALLSTACKUP">; 44def IMPLICIT_USE : PseudoInstV8<"IMPLICIT_USE">; 45def IMPLICIT_DEF : PseudoInstV8<"IMPLICIT_DEF">; 46def FpMOVD : PseudoInstV8<"FpMOVD">; // pseudo 64-bit double move 47 48// Section A.3 - Synthetic Instructions, p. 85 49// special cases of JMPL: 50let isReturn = 1, isTerminator = 1, hasDelaySlot = 1 in { 51 let rd = I7.Num, rs1 = G0.Num, simm13 = 8 in 52 def RET : F3_2<2, 0b111000, "ret">; 53 let rd = O7.Num, rs1 = G0.Num, simm13 = 8 in 54 def RETL: F3_2<2, 0b111000, "retl">; 55} 56// CMP is a special case of SUBCC where destination is ignored, by setting it to 57// %g0 (hardwired zero). 58// FIXME: should keep track of the fact that it defs the integer condition codes 59let rd = 0 in 60 def CMPri: F3_2<2, 0b010100, "cmp">; 61 62// Section B.1 - Load Integer Instructions, p. 90 63def LDSB: F3_2<3, 0b001001, "ldsb">; 64def LDSH: F3_2<3, 0b001010, "ldsh">; 65def LDUB: F3_2<3, 0b000001, "ldub">; 66def LDUH: F3_2<3, 0b000010, "lduh">; 67def LD : F3_2<3, 0b000000, "ld">; 68def LDD : F3_2<3, 0b000011, "ldd">; 69 70// Section B.2 - Load Floating-point Instructions, p. 92 71def LDFrr : F3_1<3, 0b100000, "ld">; 72def LDFri : F3_2<3, 0b100000, "ld">; 73def LDDFrr : F3_1<3, 0b100011, "ldd">; 74def LDDFri : F3_2<3, 0b100011, "ldd">; 75def LDFSRrr: F3_1<3, 0b100001, "ld">; 76def LDFSRri: F3_2<3, 0b100001, "ld">; 77 78// Section B.4 - Store Integer Instructions, p. 95 79def STB : F3_2<3, 0b000101, "stb">; 80def STH : F3_2<3, 0b000110, "sth">; 81def ST : F3_2<3, 0b000100, "st">; 82def STD : F3_2<3, 0b000111, "std">; 83 84// Section B.5 - Store Floating-point Instructions, p. 97 85def STFrr : F3_1<3, 0b100100, "st">; 86def STFri : F3_2<3, 0b100100, "st">; 87def STDFrr : F3_1<3, 0b100111, "std">; 88def STDFri : F3_2<3, 0b100111, "std">; 89def STFSRrr : F3_1<3, 0b100101, "st">; 90def STFSRri : F3_2<3, 0b100101, "st">; 91def STDFQrr : F3_1<3, 0b100110, "std">; 92def STDFQri : F3_2<3, 0b100110, "std">; 93 94// Section B.9 - SETHI Instruction, p. 104 95def SETHIi: F2_1<0b100, "sethi">; 96 97// Section B.10 - NOP Instruction, p. 105 98// (It's a special case of SETHI) 99let rd = 0, imm22 = 0 in 100 def NOP : F2_1<0b100, "nop">; 101 102// Section B.11 - Logical Instructions, p. 106 103def ANDrr : F3_1<2, 0b000001, "and">; 104def ANDri : F3_2<2, 0b000001, "and">; 105def ORrr : F3_1<2, 0b000010, "or">; 106def ORri : F3_2<2, 0b000010, "or">; 107def XORrr : F3_1<2, 0b000011, "xor">; 108def XORri : F3_2<2, 0b000011, "xor">; 109 110// Section B.12 - Shift Instructions, p. 107 111def SLLrr : F3_1<2, 0b100101, "sll">; 112def SLLri : F3_2<2, 0b100101, "sll">; 113def SRLrr : F3_1<2, 0b100110, "srl">; 114def SRLri : F3_2<2, 0b100110, "srl">; 115def SRArr : F3_1<2, 0b100111, "sra">; 116def SRAri : F3_2<2, 0b100111, "sra">; 117 118// Section B.13 - Add Instructions, p. 108 119def ADDrr : F3_1<2, 0b000000, "add">; 120def ADDri : F3_2<2, 0b000000, "add">; 121 122// Section B.15 - Subtract Instructions, p. 110 123def SUBrr : F3_1<2, 0b000100, "sub">; 124def SUBCCrr : F3_1<2, 0b010100, "subcc">; 125def SUBCCri : F3_2<2, 0b010100, "subcc">; 126 127// Section B.18 - Multiply Instructions, p. 113 128def UMULrr : F3_1<2, 0b001010, "umul">; 129def SMULrr : F3_1<2, 0b001011, "smul">; 130 131// Section B.19 - Divide Instructions, p. 115 132def UDIVrr : F3_1<2, 0b001110, "udiv">; 133def UDIVri : F3_2<2, 0b001110, "udiv">; 134def SDIVrr : F3_1<2, 0b001111, "sdiv">; 135def SDIVri : F3_2<2, 0b001111, "sdiv">; 136def UDIVCCrr : F3_1<2, 0b011110, "udivcc">; 137def UDIVCCri : F3_2<2, 0b011110, "udivcc">; 138def SDIVCCrr : F3_1<2, 0b011111, "sdivcc">; 139def SDIVCCri : F3_2<2, 0b011111, "sdivcc">; 140 141// Section B.20 - SAVE and RESTORE, p. 117 142def SAVErr : F3_1<2, 0b111100, "save">; // save r, r, r 143def SAVEri : F3_2<2, 0b111100, "save">; // save r, i, r 144def RESTORErr : F3_1<2, 0b111101, "restore">; // restore r, r, r 145def RESTOREri : F3_2<2, 0b111101, "restore">; // restore r, i, r 146 147// Section B.21 - Branch on Integer Condition Codes Instructions, p. 119 148 149// conditional branch class: 150class BranchV8<bits<4> cc, string nm> : F2_2<cc, 0b010, nm> { 151 let isBranch = 1; 152 let isTerminator = 1; 153 let hasDelaySlot = 1; 154} 155 156let isBarrier = 1 in 157 def BA : BranchV8<0b1000, "ba">; 158def BN : BranchV8<0b0000, "bn">; 159def BNE : BranchV8<0b1001, "bne">; 160def BE : BranchV8<0b0001, "be">; 161def BG : BranchV8<0b1010, "bg">; 162def BLE : BranchV8<0b0010, "ble">; 163def BGE : BranchV8<0b1011, "bge">; 164def BL : BranchV8<0b0011, "bl">; 165def BGU : BranchV8<0b1100, "bgu">; 166def BLEU : BranchV8<0b0100, "bleu">; 167def BCC : BranchV8<0b1101, "bcc">; 168def BCS : BranchV8<0b0101, "bcs">; 169 170// Section B.22 - Branch on Floating-point Condition Codes Instructions, p. 121 171 172// floating-point conditional branch class: 173class FPBranchV8<bits<4> cc, string nm> : F2_2<cc, 0b110, nm> { 174 let isBranch = 1; 175 let isTerminator = 1; 176 let hasDelaySlot = 1; 177} 178 179def FBA : FPBranchV8<0b1000, "fba">; 180def FBN : FPBranchV8<0b0000, "fbn">; 181def FBU : FPBranchV8<0b0111, "fbu">; 182def FBG : FPBranchV8<0b0110, "fbg">; 183def FBUG : FPBranchV8<0b0101, "fbug">; 184def FBL : FPBranchV8<0b0100, "fbl">; 185def FBUL : FPBranchV8<0b0011, "fbul">; 186def FBLG : FPBranchV8<0b0010, "fblg">; 187def FBNE : FPBranchV8<0b0001, "fbne">; 188def FBE : FPBranchV8<0b1001, "fbe">; 189def FBUE : FPBranchV8<0b1010, "fbue">; 190def FBGE : FPBranchV8<0b1011, "fbge">; 191def FBUGE: FPBranchV8<0b1100, "fbuge">; 192def FBLE : FPBranchV8<0b1101, "fble">; 193def FBULE: FPBranchV8<0b1110, "fbule">; 194def FBO : FPBranchV8<0b1111, "fbo">; 195 196 197 198// Section B.24 - Call and Link Instruction, p. 125 199// This is the only Format 1 instruction 200let Uses = [O0, O1, O2, O3, O4, O5], hasDelaySlot = 1, isCall = 1 in { 201 // pc-relative call: 202 let Defs = [O0, O1, O2, O3, O4, O5, O7, G1, G2, G3, G4, G5, G6, G7, 203 D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15] in 204 def CALL : InstV8 { 205 bits<30> disp; 206 let op = 1; 207 let Inst{29-0} = disp; 208 let Name = "call"; 209 } 210 211 // indirect call (O7 is an EXPLICIT def in indirect calls, so it cannot also 212 // be an implicit def): 213 let Defs = [O0, O1, O2, O3, O4, O5, G1, G2, G3, G4, G5, G6, G7, 214 D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15] in 215 def JMPLrr : F3_1<2, 0b111000, "jmpl">; // jmpl [rs1+rs2], rd 216} 217 218// Section B.29 - Write State Register Instructions 219def WRrr : F3_1<2, 0b110000, "wr">; // wr rs1, rs2, rd 220def WRri : F3_2<2, 0b110000, "wr">; // wr rs1, imm, rd 221 222// Convert Integer to Floating-point Instructions, p. 141 223def FITOS : F3_3<2, 0b110100, 0b011000100, "fitos">; 224def FITOD : F3_3<2, 0b110100, 0b011001000, "fitod">; 225 226// Convert Floating-point to Integer Instructions, p. 142 227def FSTOI : F3_3<2, 0b110100, 0b011010001, "fstoi">; 228def FDTOI : F3_3<2, 0b110100, 0b011010010, "fdtoi">; 229 230// Convert between Floating-point Formats Instructions, p. 143 231def FSTOD : F3_3<2, 0b110100, 0b011001001, "fstod">; 232def FDTOS : F3_3<2, 0b110100, 0b011000110, "fdtos">; 233 234// Floating-point Move Instructions, p. 144 235def FMOVS : F3_3<2, 0b110100, 0b000000001, "fmovs">; 236def FNEGS : F3_3<2, 0b110100, 0b000000101, "fnegs">; 237def FABSS : F3_3<2, 0b110100, 0b000001001, "fabss">; 238 239// Floating-point Add and Subtract Instructions, p. 146 240def FADDS : F3_3<2, 0b110100, 0b001000001, "fadds">; 241def FADDD : F3_3<2, 0b110100, 0b001000010, "faddd">; 242def FSUBS : F3_3<2, 0b110100, 0b001000101, "fsubs">; 243def FSUBD : F3_3<2, 0b110100, 0b001000110, "fsubd">; 244 245// Floating-point Multiply and Divide Instructions, p. 147 246def FMULS : F3_3<2, 0b110100, 0b001001001, "fmuls">; 247def FMULD : F3_3<2, 0b110100, 0b001001010, "fmuld">; 248def FSMULD : F3_3<2, 0b110100, 0b001101001, "fsmuld">; 249def FDIVS : F3_3<2, 0b110100, 0b001001101, "fdivs">; 250def FDIVD : F3_3<2, 0b110100, 0b001001110, "fdivd">; 251 252// Floating-point Compare Instructions, p. 148 253// Note: the 2nd template arg is different for these guys. 254// Note 2: the result of a FCMP is not available until the 2nd cycle 255// after the instr is retired, but there is no interlock. This behavior 256// is modelled as a delay slot. 257let hasDelaySlot = 1 in { 258 def FCMPS : F3_3<2, 0b110101, 0b001010001, "fcmps">; 259 def FCMPD : F3_3<2, 0b110101, 0b001010010, "fcmpd">; 260 def FCMPES : F3_3<2, 0b110101, 0b001010101, "fcmpes">; 261 def FCMPED : F3_3<2, 0b110101, 0b001010110, "fcmped">; 262} 263 264