SparcInstrInfo.td revision bc83fd96721eda272d90eafcb3a2a31ef9a2c366
1//===- SparcV8Instrs.td - Target Description for SparcV8 Target -----------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the SparcV8 instructions in TableGen format. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// Instruction format superclass 16//===----------------------------------------------------------------------===// 17 18class InstV8 : Instruction { // SparcV8 instruction baseline 19 field bits<32> Inst; 20 21 let Namespace = "V8"; 22 23 bits<2> op; 24 let Inst{31-30} = op; // Top two bits are the 'op' field 25 26 // Bit attributes specific to SparcV8 instructions 27 bit isPasi = 0; // Does this instruction affect an alternate addr space? 28 bit isPrivileged = 0; // Is this a privileged instruction? 29} 30 31include "SparcV8InstrFormats.td" 32 33//===----------------------------------------------------------------------===// 34// Instruction Pattern Stuff 35//===----------------------------------------------------------------------===// 36 37def simm13 : PatLeaf<(imm), [{ 38 // simm13 predicate - True if the imm fits in a 13-bit sign extended field. 39 return (((int)N->getValue() << (32-13)) >> (32-13)) == (int)N->getValue(); 40}]>; 41 42def LO10 : SDNodeXForm<imm, [{ 43 return CurDAG->getTargetConstant((unsigned)N->getValue() & 1023, MVT::i32); 44}]>; 45 46def HI22 : SDNodeXForm<imm, [{ 47 // Transformation function: shift the immediate value down into the low bits. 48 return CurDAG->getTargetConstant((unsigned)N->getValue() >> 10, MVT::i32); 49}]>; 50 51def SETHIimm : PatLeaf<(imm), [{ 52 return (((unsigned)N->getValue() >> 10) << 10) == (unsigned)N->getValue(); 53}], HI22>; 54 55// Addressing modes. 56def ADDRrr : ComplexPattern<i32, 2, "SelectADDRrr", []>; 57def ADDRri : ComplexPattern<i32, 2, "SelectADDRri", []>; 58 59// Address operands 60def MEMrr : Operand<i32> { 61 let PrintMethod = "printMemOperand"; 62 let NumMIOperands = 2; 63 let MIOperandInfo = (ops IntRegs, IntRegs); 64} 65def MEMri : Operand<i32> { 66 let PrintMethod = "printMemOperand"; 67 let NumMIOperands = 2; 68 let MIOperandInfo = (ops IntRegs, i32imm); 69} 70 71//===----------------------------------------------------------------------===// 72// Instructions 73//===----------------------------------------------------------------------===// 74 75// Pseudo instructions. 76class PseudoInstV8<string asmstr, dag ops> : InstV8 { 77 let AsmString = asmstr; 78 dag OperandList = ops; 79} 80def PHI : PseudoInstV8<"PHI", (ops variable_ops)>; 81def ADJCALLSTACKDOWN : PseudoInstV8<"!ADJCALLSTACKDOWN $amt", 82 (ops i32imm:$amt)>; 83def ADJCALLSTACKUP : PseudoInstV8<"!ADJCALLSTACKUP $amt", 84 (ops i32imm:$amt)>; 85//def IMPLICIT_USE : PseudoInstV8<"!IMPLICIT_USE",(ops variable_ops)>; 86def IMPLICIT_DEF : PseudoInstV8<"!IMPLICIT_DEF $dst", 87 (ops IntRegs:$dst)>; 88def FpMOVD : PseudoInstV8<"!FpMOVD", (ops)>; // pseudo 64-bit double move 89 90// Section A.3 - Synthetic Instructions, p. 85 91// special cases of JMPL: 92let isReturn = 1, isTerminator = 1, hasDelaySlot = 1 in { 93 let rd = I7.Num, rs1 = G0.Num, simm13 = 8 in 94 def RET : F3_2<2, 0b111000, 95 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 96 "ret $b, $c, $dst", []>; 97 let rd = O7.Num, rs1 = G0.Num, simm13 = 8 in 98 def RETL: F3_2<2, 0b111000, (ops), 99 "retl", [(ret)]>; 100} 101// CMP is a special case of SUBCC where destination is ignored, by setting it to 102// %g0 (hardwired zero). 103// FIXME: should keep track of the fact that it defs the integer condition codes 104let rd = 0 in 105 def CMPri: F3_2<2, 0b010100, 106 (ops IntRegs:$b, i32imm:$c), 107 "cmp $b, $c", []>; 108 109// Section B.1 - Load Integer Instructions, p. 90 110def LDSB: F3_2<3, 0b001001, 111 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 112 "ldsb [$b+$c], $dst", []>; 113def LDSH: F3_2<3, 0b001010, 114 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 115 "ldsh [$b+$c], $dst", []>; 116def LDUB: F3_2<3, 0b000001, 117 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 118 "ldub [$b+$c], $dst", []>; 119def LDUH: F3_2<3, 0b000010, 120 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 121 "lduh [$b+$c], $dst", []>; 122def LD : F3_2<3, 0b000000, 123 (ops IntRegs:$dst, MEMri:$addr), 124 "ld [$addr], $dst", 125 [(set IntRegs:$dst, (load ADDRri:$addr))]>; 126def LDD : F3_2<3, 0b000011, 127 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 128 "ldd [$b+$c], $dst", []>; 129 130// Section B.2 - Load Floating-point Instructions, p. 92 131def LDFrr : F3_1<3, 0b100000, 132 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 133 "ld [$b+$c], $dst", []>; 134def LDFri : F3_2<3, 0b100000, 135 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 136 "ld [$b+$c], $dst", []>; 137def LDDFrr : F3_1<3, 0b100011, 138 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 139 "ldd [$b+$c], $dst", []>; 140def LDDFri : F3_2<3, 0b100011, 141 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 142 "ldd [$b+$c], $dst", []>; 143def LDFSRrr: F3_1<3, 0b100001, 144 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 145 "ld [$b+$c], $dst", []>; 146def LDFSRri: F3_2<3, 0b100001, 147 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 148 "ld [$b+$c], $dst", []>; 149 150// Section B.4 - Store Integer Instructions, p. 95 151def STB : F3_2<3, 0b000101, 152 (ops IntRegs:$base, IntRegs:$offset, i32imm:$src), 153 "stb $src, [$base+$offset]", []>; 154def STH : F3_2<3, 0b000110, 155 (ops IntRegs:$base, IntRegs:$offset, i32imm:$src), 156 "sth $src, [$base+$offset]", []>; 157def ST : F3_2<3, 0b000100, 158 (ops IntRegs:$base, IntRegs:$offset, i32imm:$src), 159 "st $src, [$base+$offset]", []>; 160def STD : F3_2<3, 0b000111, 161 (ops IntRegs:$base, IntRegs:$offset, i32imm:$src), 162 "std $src, [$base+$offset]", []>; 163 164// Section B.5 - Store Floating-point Instructions, p. 97 165def STFrr : F3_1<3, 0b100100, 166 (ops IntRegs:$base, IntRegs:$offset, IntRegs:$src), 167 "st $src, [$base+$offset]", []>; 168def STFri : F3_2<3, 0b100100, 169 (ops IntRegs:$base, IntRegs:$offset, i32imm:$src), 170 "st $src, [$base+$offset]", []>; 171def STDFrr : F3_1<3, 0b100111, 172 (ops IntRegs:$base, IntRegs:$offset, IntRegs:$src), 173 "std $src, [$base+$offset]", []>; 174def STDFri : F3_2<3, 0b100111, 175 (ops IntRegs:$base, IntRegs:$offset, i32imm:$src), 176 "std $src, [$base+$offset]", []>; 177def STFSRrr : F3_1<3, 0b100101, 178 (ops IntRegs:$base, IntRegs:$offset, IntRegs:$src), 179 "st $src, [$base+$offset]", []>; 180def STFSRri : F3_2<3, 0b100101, 181 (ops IntRegs:$base, IntRegs:$offset, i32imm:$src), 182 "st $src, [$base+$offset]", []>; 183def STDFQrr : F3_1<3, 0b100110, 184 (ops IntRegs:$base, IntRegs:$offset, IntRegs:$src), 185 "std $src, [$base+$offset]", []>; 186def STDFQri : F3_2<3, 0b100110, 187 (ops IntRegs:$base, IntRegs:$offset, i32imm:$src), 188 "std $src, [$base+$offset]", []>; 189 190// Section B.9 - SETHI Instruction, p. 104 191def SETHIi: F2_1<0b100, 192 (ops IntRegs:$dst, i32imm:$src), 193 "sethi $src, $dst", 194 [(set IntRegs:$dst, SETHIimm:$src)]>; 195 196// Section B.10 - NOP Instruction, p. 105 197// (It's a special case of SETHI) 198let rd = 0, imm22 = 0 in 199 def NOP : F2_1<0b100, (ops), "nop", []>; 200 201// Section B.11 - Logical Instructions, p. 106 202def ANDrr : F3_1<2, 0b000001, 203 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 204 "and $b, $c, $dst", 205 [(set IntRegs:$dst, (and IntRegs:$b, IntRegs:$c))]>; 206def ANDri : F3_2<2, 0b000001, 207 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 208 "and $b, $c, $dst", 209 [(set IntRegs:$dst, (and IntRegs:$b, simm13:$c))]>; 210def ANDCCrr : F3_1<2, 0b010001, 211 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 212 "andcc $b, $c, $dst", []>; 213def ANDCCri : F3_2<2, 0b010001, 214 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 215 "andcc $b, $c, $dst", []>; 216def ANDNrr : F3_1<2, 0b000101, 217 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 218 "andn $b, $c, $dst", []>; 219def ANDNri : F3_2<2, 0b000101, 220 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 221 "andn $b, $c, $dst", []>; 222def ANDNCCrr: F3_1<2, 0b010101, 223 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 224 "andncc $b, $c, $dst", []>; 225def ANDNCCri: F3_2<2, 0b010101, 226 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 227 "andncc $b, $c, $dst", []>; 228def ORrr : F3_1<2, 0b000010, 229 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 230 "or $b, $c, $dst", 231 [(set IntRegs:$dst, (or IntRegs:$b, IntRegs:$c))]>; 232def ORri : F3_2<2, 0b000010, 233 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 234 "or $b, $c, $dst", 235 [(set IntRegs:$dst, (or IntRegs:$b, simm13:$c))]>; 236def ORCCrr : F3_1<2, 0b010010, 237 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 238 "orcc $b, $c, $dst", []>; 239def ORCCri : F3_2<2, 0b010010, 240 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 241 "orcc $b, $c, $dst", []>; 242def ORNrr : F3_1<2, 0b000110, 243 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 244 "orn $b, $c, $dst", []>; 245def ORNri : F3_2<2, 0b000110, 246 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 247 "orn $b, $c, $dst", []>; 248def ORNCCrr : F3_1<2, 0b010110, 249 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 250 "orncc $b, $c, $dst", []>; 251def ORNCCri : F3_2<2, 0b010110, 252 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 253 "orncc $b, $c, $dst", []>; 254def XORrr : F3_1<2, 0b000011, 255 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 256 "xor $b, $c, $dst", 257 [(set IntRegs:$dst, (xor IntRegs:$b, IntRegs:$c))]>; 258def XORri : F3_2<2, 0b000011, 259 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 260 "xor $b, $c, $dst", 261 [(set IntRegs:$dst, (xor IntRegs:$b, simm13:$c))]>; 262def XORCCrr : F3_1<2, 0b010011, 263 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 264 "xorcc $b, $c, $dst", []>; 265def XORCCri : F3_2<2, 0b010011, 266 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 267 "xorcc $b, $c, $dst", []>; 268def XNORrr : F3_1<2, 0b000111, 269 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 270 "xnor $b, $c, $dst", []>; 271def XNORri : F3_2<2, 0b000111, 272 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 273 "xnor $b, $c, $dst", []>; 274def XNORCCrr: F3_1<2, 0b010111, 275 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 276 "xnorcc $b, $c, $dst", []>; 277def XNORCCri: F3_2<2, 0b010111, 278 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 279 "xnorcc $b, $c, $dst", []>; 280 281// Section B.12 - Shift Instructions, p. 107 282def SLLrr : F3_1<2, 0b100101, 283 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 284 "sll $b, $c, $dst", 285 [(set IntRegs:$dst, (shl IntRegs:$b, IntRegs:$c))]>; 286def SLLri : F3_2<2, 0b100101, 287 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 288 "sll $b, $c, $dst", 289 [(set IntRegs:$dst, (shl IntRegs:$b, simm13:$c))]>; 290def SRLrr : F3_1<2, 0b100110, 291 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 292 "srl $b, $c, $dst", 293 [(set IntRegs:$dst, (srl IntRegs:$b, IntRegs:$c))]>; 294def SRLri : F3_2<2, 0b100110, 295 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 296 "srl $b, $c, $dst", 297 [(set IntRegs:$dst, (srl IntRegs:$b, simm13:$c))]>; 298def SRArr : F3_1<2, 0b100111, 299 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 300 "sra $b, $c, $dst", 301 [(set IntRegs:$dst, (sra IntRegs:$b, IntRegs:$c))]>; 302def SRAri : F3_2<2, 0b100111, 303 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 304 "sra $b, $c, $dst", 305 [(set IntRegs:$dst, (sra IntRegs:$b, simm13:$c))]>; 306 307// Section B.13 - Add Instructions, p. 108 308def ADDrr : F3_1<2, 0b000000, 309 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 310 "add $b, $c, $dst", 311 [(set IntRegs:$dst, (add IntRegs:$b, IntRegs:$c))]>; 312def ADDri : F3_2<2, 0b000000, 313 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 314 "add $b, $c, $dst", 315 [(set IntRegs:$dst, (add IntRegs:$b, simm13:$c))]>; 316def ADDCCrr : F3_1<2, 0b010000, 317 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 318 "addcc $b, $c, $dst", []>; 319def ADDCCri : F3_2<2, 0b010000, 320 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 321 "addcc $b, $c, $dst", []>; 322def ADDXrr : F3_1<2, 0b001000, 323 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 324 "addx $b, $c, $dst", []>; 325def ADDXri : F3_2<2, 0b001000, 326 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 327 "addx $b, $c, $dst", []>; 328def ADDXCCrr: F3_1<2, 0b011000, 329 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 330 "addxcc $b, $c, $dst", []>; 331def ADDXCCri: F3_2<2, 0b011000, 332 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 333 "addxcc $b, $c, $dst", []>; 334 335// Section B.15 - Subtract Instructions, p. 110 336def SUBrr : F3_1<2, 0b000100, 337 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 338 "sub $b, $c, $dst", 339 [(set IntRegs:$dst, (sub IntRegs:$b, IntRegs:$c))]>; 340def SUBri : F3_2<2, 0b000100, 341 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 342 "sub $b, $c, $dst", 343 [(set IntRegs:$dst, (sub IntRegs:$b, simm13:$c))]>; 344def SUBCCrr : F3_1<2, 0b010100, 345 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 346 "subcc $b, $c, $dst", []>; 347def SUBCCri : F3_2<2, 0b010100, 348 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 349 "subcc $b, $c, $dst", []>; 350def SUBXrr : F3_1<2, 0b001100, 351 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 352 "subx $b, $c, $dst", []>; 353def SUBXri : F3_2<2, 0b001100, 354 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 355 "subx $b, $c, $dst", []>; 356def SUBXCCrr: F3_1<2, 0b011100, 357 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 358 "subxcc $b, $c, $dst", []>; 359def SUBXCCri: F3_2<2, 0b011100, 360 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 361 "subxcc $b, $c, $dst", []>; 362 363// Section B.18 - Multiply Instructions, p. 113 364def UMULrr : F3_1<2, 0b001010, 365 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 366 "umul $b, $c, $dst", []>; 367def UMULri : F3_2<2, 0b001010, 368 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 369 "umul $b, $c, $dst", []>; 370def SMULrr : F3_1<2, 0b001011, 371 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 372 "smul $b, $c, $dst", []>; 373def SMULri : F3_2<2, 0b001011, 374 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 375 "smul $b, $c, $dst", []>; 376def UMULCCrr: F3_1<2, 0b011010, 377 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 378 "umulcc $b, $c, $dst", []>; 379def UMULCCri: F3_2<2, 0b011010, 380 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 381 "umulcc $b, $c, $dst", []>; 382def SMULCCrr: F3_1<2, 0b011011, 383 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 384 "smulcc $b, $c, $dst", []>; 385def SMULCCri: F3_2<2, 0b011011, 386 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 387 "smulcc $b, $c, $dst", []>; 388 389// Section B.19 - Divide Instructions, p. 115 390def UDIVrr : F3_1<2, 0b001110, 391 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 392 "udiv $b, $c, $dst", []>; 393def UDIVri : F3_2<2, 0b001110, 394 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 395 "udiv $b, $c, $dst", []>; 396def SDIVrr : F3_1<2, 0b001111, 397 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 398 "sdiv $b, $c, $dst", []>; 399def SDIVri : F3_2<2, 0b001111, 400 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 401 "sdiv $b, $c, $dst", []>; 402def UDIVCCrr : F3_1<2, 0b011110, 403 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 404 "udivcc $b, $c, $dst", []>; 405def UDIVCCri : F3_2<2, 0b011110, 406 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 407 "udivcc $b, $c, $dst", []>; 408def SDIVCCrr : F3_1<2, 0b011111, 409 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 410 "sdivcc $b, $c, $dst", []>; 411def SDIVCCri : F3_2<2, 0b011111, 412 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 413 "sdivcc $b, $c, $dst", []>; 414 415// Section B.20 - SAVE and RESTORE, p. 117 416def SAVErr : F3_1<2, 0b111100, 417 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 418 "save $b, $c, $dst", []>; 419def SAVEri : F3_2<2, 0b111100, 420 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 421 "save $b, $c, $dst", []>; 422def RESTORErr : F3_1<2, 0b111101, 423 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 424 "restore $b, $c, $dst", []>; 425def RESTOREri : F3_2<2, 0b111101, 426 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 427 "restore $b, $c, $dst", []>; 428 429// Section B.21 - Branch on Integer Condition Codes Instructions, p. 119 430 431// conditional branch class: 432class BranchV8<bits<4> cc, dag ops, string asmstr> 433 : F2_2<cc, 0b010, ops, asmstr> { 434 let isBranch = 1; 435 let isTerminator = 1; 436 let hasDelaySlot = 1; 437} 438 439let isBarrier = 1 in 440 def BA : BranchV8<0b1000, (ops IntRegs:$dst), "ba $dst">; 441def BN : BranchV8<0b0000, (ops IntRegs:$dst), "bn $dst">; 442def BNE : BranchV8<0b1001, (ops IntRegs:$dst), "bne $dst">; 443def BE : BranchV8<0b0001, (ops IntRegs:$dst), "be $dst">; 444def BG : BranchV8<0b1010, (ops IntRegs:$dst), "bg $dst">; 445def BLE : BranchV8<0b0010, (ops IntRegs:$dst), "ble $dst">; 446def BGE : BranchV8<0b1011, (ops IntRegs:$dst), "bge $dst">; 447def BL : BranchV8<0b0011, (ops IntRegs:$dst), "bl $dst">; 448def BGU : BranchV8<0b1100, (ops IntRegs:$dst), "bgu $dst">; 449def BLEU : BranchV8<0b0100, (ops IntRegs:$dst), "bleu $dst">; 450def BCC : BranchV8<0b1101, (ops IntRegs:$dst), "bcc $dst">; 451def BCS : BranchV8<0b0101, (ops IntRegs:$dst), "bcs $dst">; 452 453// Section B.22 - Branch on Floating-point Condition Codes Instructions, p. 121 454 455// floating-point conditional branch class: 456class FPBranchV8<bits<4> cc, dag ops, string asmstr> 457 : F2_2<cc, 0b110, ops, asmstr> { 458 let isBranch = 1; 459 let isTerminator = 1; 460 let hasDelaySlot = 1; 461} 462 463def FBA : FPBranchV8<0b1000, (ops IntRegs:$dst), "fba $dst">; 464def FBN : FPBranchV8<0b0000, (ops IntRegs:$dst), "fbn $dst">; 465def FBU : FPBranchV8<0b0111, (ops IntRegs:$dst), "fbu $dst">; 466def FBG : FPBranchV8<0b0110, (ops IntRegs:$dst), "fbg $dst">; 467def FBUG : FPBranchV8<0b0101, (ops IntRegs:$dst), "fbug $dst">; 468def FBL : FPBranchV8<0b0100, (ops IntRegs:$dst), "fbl $dst">; 469def FBUL : FPBranchV8<0b0011, (ops IntRegs:$dst), "fbul $dst">; 470def FBLG : FPBranchV8<0b0010, (ops IntRegs:$dst), "fblg $dst">; 471def FBNE : FPBranchV8<0b0001, (ops IntRegs:$dst), "fbne $dst">; 472def FBE : FPBranchV8<0b1001, (ops IntRegs:$dst), "fbe $dst">; 473def FBUE : FPBranchV8<0b1010, (ops IntRegs:$dst), "fbue $dst">; 474def FBGE : FPBranchV8<0b1011, (ops IntRegs:$dst), "fbge $dst">; 475def FBUGE: FPBranchV8<0b1100, (ops IntRegs:$dst), "fbuge $dst">; 476def FBLE : FPBranchV8<0b1101, (ops IntRegs:$dst), "fble $dst">; 477def FBULE: FPBranchV8<0b1110, (ops IntRegs:$dst), "fbule $dst">; 478def FBO : FPBranchV8<0b1111, (ops IntRegs:$dst), "fbo $dst">; 479 480 481 482// Section B.24 - Call and Link Instruction, p. 125 483// This is the only Format 1 instruction 484let Uses = [O0, O1, O2, O3, O4, O5], hasDelaySlot = 1, isCall = 1 in { 485 // pc-relative call: 486 let Defs = [O0, O1, O2, O3, O4, O5, O7, G1, G2, G3, G4, G5, G6, G7, 487 D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15] in 488 def CALL : InstV8 { 489 let OperandList = (ops IntRegs:$dst); 490 bits<30> disp; 491 let op = 1; 492 let Inst{29-0} = disp; 493 let AsmString = "call $dst"; 494 } 495 496 // indirect call (O7 is an EXPLICIT def in indirect calls, so it cannot also 497 // be an implicit def): 498 let Defs = [O0, O1, O2, O3, O4, O5, G1, G2, G3, G4, G5, G6, G7, 499 D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15] in 500 def JMPLrr : F3_1<2, 0b111000, 501 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 502 "jmpl $b+$c, $dst", []>; 503} 504 505// Section B.29 - Write State Register Instructions 506def WRrr : F3_1<2, 0b110000, 507 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 508 "wr $b, $c, $dst", []>; 509def WRri : F3_2<2, 0b110000, 510 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 511 "wr $b, $c, $dst", []>; 512 513// Convert Integer to Floating-point Instructions, p. 141 514def FITOS : F3_3<2, 0b110100, 0b011000100, 515 (ops FPRegs:$dst, FPRegs:$src), 516 "fitos $src, $dst">; 517def FITOD : F3_3<2, 0b110100, 0b011001000, 518 (ops DFPRegs:$dst, DFPRegs:$src), 519 "fitod $src, $dst">; 520 521// Convert Floating-point to Integer Instructions, p. 142 522def FSTOI : F3_3<2, 0b110100, 0b011010001, 523 (ops FPRegs:$dst, FPRegs:$src), 524 "fstoi $src, $dst">; 525def FDTOI : F3_3<2, 0b110100, 0b011010010, 526 (ops DFPRegs:$dst, DFPRegs:$src), 527 "fdtoi $src, $dst">; 528 529// Convert between Floating-point Formats Instructions, p. 143 530def FSTOD : F3_3<2, 0b110100, 0b011001001, 531 (ops DFPRegs:$dst, FPRegs:$src), 532 "fstod $src, $dst">; 533def FDTOS : F3_3<2, 0b110100, 0b011000110, 534 (ops FPRegs:$dst, DFPRegs:$src), 535 "fdtos $src, $dst">; 536 537// Floating-point Move Instructions, p. 144 538def FMOVS : F3_3<2, 0b110100, 0b000000001, 539 (ops FPRegs:$dst, FPRegs:$src), 540 "fmovs $src, $dst">; 541def FNEGS : F3_3<2, 0b110100, 0b000000101, 542 (ops FPRegs:$dst, FPRegs:$src), 543 "fnegs $src, $dst">; 544def FABSS : F3_3<2, 0b110100, 0b000001001, 545 (ops FPRegs:$dst, FPRegs:$src), 546 "fabss $src, $dst">; 547 548// Floating-point Add and Subtract Instructions, p. 146 549def FADDS : F3_3<2, 0b110100, 0b001000001, 550 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2), 551 "fadds $src1, $src2, $dst">; 552def FADDD : F3_3<2, 0b110100, 0b001000010, 553 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2), 554 "faddd $src1, $src2, $dst">; 555def FSUBS : F3_3<2, 0b110100, 0b001000101, 556 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2), 557 "fsubs $src1, $src2, $dst">; 558def FSUBD : F3_3<2, 0b110100, 0b001000110, 559 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2), 560 "fsubd $src1, $src2, $dst">; 561 562// Floating-point Multiply and Divide Instructions, p. 147 563def FMULS : F3_3<2, 0b110100, 0b001001001, 564 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2), 565 "fmuls $src1, $src2, $dst">; 566def FMULD : F3_3<2, 0b110100, 0b001001010, 567 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2), 568 "fmuld $src1, $src2, $dst">; 569def FSMULD : F3_3<2, 0b110100, 0b001101001, 570 (ops DFPRegs:$dst, FPRegs:$src1, FPRegs:$src2), 571 "fsmuld $src1, $src2, $dst">; 572def FDIVS : F3_3<2, 0b110100, 0b001001101, 573 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2), 574 "fdivs $src1, $src2, $dst">; 575def FDIVD : F3_3<2, 0b110100, 0b001001110, 576 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2), 577 "fdivd $src1, $src2, $dst">; 578 579// Floating-point Compare Instructions, p. 148 580// Note: the 2nd template arg is different for these guys. 581// Note 2: the result of a FCMP is not available until the 2nd cycle 582// after the instr is retired, but there is no interlock. This behavior 583// is modelled with a forced noop after the instruction. 584def FCMPS : F3_3<2, 0b110101, 0b001010001, 585 (ops FPRegs:$src1, FPRegs:$src2), 586 "fcmps $src1, $src2\n\tnop">; 587def FCMPD : F3_3<2, 0b110101, 0b001010010, 588 (ops DFPRegs:$src1, DFPRegs:$src2), 589 "fcmpd $src1, $src2\n\tnop">; 590def FCMPES : F3_3<2, 0b110101, 0b001010101, 591 (ops FPRegs:$src1, FPRegs:$src2), 592 "fcmpes $src1, $src2\n\tnop">; 593def FCMPED : F3_3<2, 0b110101, 0b001010110, 594 (ops DFPRegs:$src1, DFPRegs:$src2), 595 "fcmped $src1, $src2\n\tnop">; 596 597//===----------------------------------------------------------------------===// 598// Non-Instruction Patterns 599//===----------------------------------------------------------------------===// 600 601// Small immediates. 602def : Pat<(i32 simm13:$val), 603 (ORri G0, imm:$val)>; 604// Arbitrary immediates. 605def : Pat<(i32 imm:$val), 606 (ORri (SETHIi (HI22 imm:$val)), (LO10 imm:$val))>; 607