SparcInstrInfo.td revision c3ff3f42ee9a9fb755b0eb0718a31d701b93b3e0
1//===-- SparcInstrInfo.td - Target Description for Sparc Target -----------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the Sparc instructions in TableGen format. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// Instruction format superclass 16//===----------------------------------------------------------------------===// 17 18include "SparcInstrFormats.td" 19 20//===----------------------------------------------------------------------===// 21// Feature predicates. 22//===----------------------------------------------------------------------===// 23 24// True when generating 32-bit code. 25def Is32Bit : Predicate<"!Subtarget.is64Bit()">; 26 27// True when generating 64-bit code. This also implies HasV9. 28def Is64Bit : Predicate<"Subtarget.is64Bit()">; 29 30// HasV9 - This predicate is true when the target processor supports V9 31// instructions. Note that the machine may be running in 32-bit mode. 32def HasV9 : Predicate<"Subtarget.isV9()">; 33 34// HasNoV9 - This predicate is true when the target doesn't have V9 35// instructions. Use of this is just a hack for the isel not having proper 36// costs for V8 instructions that are more expensive than their V9 ones. 37def HasNoV9 : Predicate<"!Subtarget.isV9()">; 38 39// HasVIS - This is true when the target processor has VIS extensions. 40def HasVIS : Predicate<"Subtarget.isVIS()">; 41 42// UseDeprecatedInsts - This predicate is true when the target processor is a 43// V8, or when it is V9 but the V8 deprecated instructions are efficient enough 44// to use when appropriate. In either of these cases, the instruction selector 45// will pick deprecated instructions. 46def UseDeprecatedInsts : Predicate<"Subtarget.useDeprecatedV8Instructions()">; 47 48//===----------------------------------------------------------------------===// 49// Instruction Pattern Stuff 50//===----------------------------------------------------------------------===// 51 52def simm11 : PatLeaf<(imm), [{ return isInt<11>(N->getSExtValue()); }]>; 53 54def simm13 : PatLeaf<(imm), [{ return isInt<13>(N->getSExtValue()); }]>; 55 56def LO10 : SDNodeXForm<imm, [{ 57 return CurDAG->getTargetConstant((unsigned)N->getZExtValue() & 1023, 58 MVT::i32); 59}]>; 60 61def HI22 : SDNodeXForm<imm, [{ 62 // Transformation function: shift the immediate value down into the low bits. 63 return CurDAG->getTargetConstant((unsigned)N->getZExtValue() >> 10, MVT::i32); 64}]>; 65 66def SETHIimm : PatLeaf<(imm), [{ 67 return (((unsigned)N->getZExtValue() >> 10) << 10) == 68 (unsigned)N->getZExtValue(); 69}], HI22>; 70 71// Addressing modes. 72def ADDRrr : ComplexPattern<iPTR, 2, "SelectADDRrr", [], []>; 73def ADDRri : ComplexPattern<iPTR, 2, "SelectADDRri", [frameindex], []>; 74 75// Address operands 76def MEMrr : Operand<iPTR> { 77 let PrintMethod = "printMemOperand"; 78 let MIOperandInfo = (ops ptr_rc, ptr_rc); 79} 80def MEMri : Operand<iPTR> { 81 let PrintMethod = "printMemOperand"; 82 let MIOperandInfo = (ops ptr_rc, i32imm); 83} 84 85// Branch targets have OtherVT type. 86def brtarget : Operand<OtherVT>; 87def calltarget : Operand<i32>; 88 89// Operand for printing out a condition code. 90let PrintMethod = "printCCOperand" in 91 def CCOp : Operand<i32>; 92 93def SDTSPcmpfcc : 94SDTypeProfile<0, 2, [SDTCisFP<0>, SDTCisSameAs<0, 1>]>; 95def SDTSPbrcc : 96SDTypeProfile<0, 2, [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>; 97def SDTSPselectcc : 98SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>]>; 99def SDTSPFTOI : 100SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisFP<1>]>; 101def SDTSPITOF : 102SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f32>]>; 103 104def SPcmpicc : SDNode<"SPISD::CMPICC", SDTIntBinOp, [SDNPOutGlue]>; 105def SPcmpfcc : SDNode<"SPISD::CMPFCC", SDTSPcmpfcc, [SDNPOutGlue]>; 106def SPbricc : SDNode<"SPISD::BRICC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>; 107def SPbrfcc : SDNode<"SPISD::BRFCC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>; 108 109def SPhi : SDNode<"SPISD::Hi", SDTIntUnaryOp>; 110def SPlo : SDNode<"SPISD::Lo", SDTIntUnaryOp>; 111 112def SPftoi : SDNode<"SPISD::FTOI", SDTSPFTOI>; 113def SPitof : SDNode<"SPISD::ITOF", SDTSPITOF>; 114 115def SPselecticc : SDNode<"SPISD::SELECT_ICC", SDTSPselectcc, [SDNPInGlue]>; 116def SPselectfcc : SDNode<"SPISD::SELECT_FCC", SDTSPselectcc, [SDNPInGlue]>; 117 118// These are target-independent nodes, but have target-specific formats. 119def SDT_SPCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>; 120def SDT_SPCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, 121 SDTCisVT<1, i32> ]>; 122 123def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_SPCallSeqStart, 124 [SDNPHasChain, SDNPOutGlue]>; 125def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_SPCallSeqEnd, 126 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 127 128def SDT_SPCall : SDTypeProfile<0, -1, [SDTCisVT<0, i32>]>; 129def call : SDNode<"SPISD::CALL", SDT_SPCall, 130 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 131 SDNPVariadic]>; 132 133def SDT_SPRet : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>; 134def retflag : SDNode<"SPISD::RET_FLAG", SDT_SPRet, 135 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 136 137def flushw : SDNode<"SPISD::FLUSHW", SDTNone, 138 [SDNPHasChain, SDNPSideEffect, SDNPMayStore]>; 139 140def getPCX : Operand<i32> { 141 let PrintMethod = "printGetPCX"; 142} 143 144//===----------------------------------------------------------------------===// 145// SPARC Flag Conditions 146//===----------------------------------------------------------------------===// 147 148// Note that these values must be kept in sync with the CCOp::CondCode enum 149// values. 150class ICC_VAL<int N> : PatLeaf<(i32 N)>; 151def ICC_NE : ICC_VAL< 9>; // Not Equal 152def ICC_E : ICC_VAL< 1>; // Equal 153def ICC_G : ICC_VAL<10>; // Greater 154def ICC_LE : ICC_VAL< 2>; // Less or Equal 155def ICC_GE : ICC_VAL<11>; // Greater or Equal 156def ICC_L : ICC_VAL< 3>; // Less 157def ICC_GU : ICC_VAL<12>; // Greater Unsigned 158def ICC_LEU : ICC_VAL< 4>; // Less or Equal Unsigned 159def ICC_CC : ICC_VAL<13>; // Carry Clear/Great or Equal Unsigned 160def ICC_CS : ICC_VAL< 5>; // Carry Set/Less Unsigned 161def ICC_POS : ICC_VAL<14>; // Positive 162def ICC_NEG : ICC_VAL< 6>; // Negative 163def ICC_VC : ICC_VAL<15>; // Overflow Clear 164def ICC_VS : ICC_VAL< 7>; // Overflow Set 165 166class FCC_VAL<int N> : PatLeaf<(i32 N)>; 167def FCC_U : FCC_VAL<23>; // Unordered 168def FCC_G : FCC_VAL<22>; // Greater 169def FCC_UG : FCC_VAL<21>; // Unordered or Greater 170def FCC_L : FCC_VAL<20>; // Less 171def FCC_UL : FCC_VAL<19>; // Unordered or Less 172def FCC_LG : FCC_VAL<18>; // Less or Greater 173def FCC_NE : FCC_VAL<17>; // Not Equal 174def FCC_E : FCC_VAL<25>; // Equal 175def FCC_UE : FCC_VAL<24>; // Unordered or Equal 176def FCC_GE : FCC_VAL<25>; // Greater or Equal 177def FCC_UGE : FCC_VAL<26>; // Unordered or Greater or Equal 178def FCC_LE : FCC_VAL<27>; // Less or Equal 179def FCC_ULE : FCC_VAL<28>; // Unordered or Less or Equal 180def FCC_O : FCC_VAL<29>; // Ordered 181 182//===----------------------------------------------------------------------===// 183// Instruction Class Templates 184//===----------------------------------------------------------------------===// 185 186/// F3_12 multiclass - Define a normal F3_1/F3_2 pattern in one shot. 187multiclass F3_12<string OpcStr, bits<6> Op3Val, SDNode OpNode> { 188 def rr : F3_1<2, Op3Val, 189 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c), 190 !strconcat(OpcStr, " $b, $c, $dst"), 191 [(set i32:$dst, (OpNode i32:$b, i32:$c))]>; 192 def ri : F3_2<2, Op3Val, 193 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c), 194 !strconcat(OpcStr, " $b, $c, $dst"), 195 [(set i32:$dst, (OpNode i32:$b, (i32 simm13:$c)))]>; 196} 197 198/// F3_12np multiclass - Define a normal F3_1/F3_2 pattern in one shot, with no 199/// pattern. 200multiclass F3_12np<string OpcStr, bits<6> Op3Val> { 201 def rr : F3_1<2, Op3Val, 202 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c), 203 !strconcat(OpcStr, " $b, $c, $dst"), []>; 204 def ri : F3_2<2, Op3Val, 205 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c), 206 !strconcat(OpcStr, " $b, $c, $dst"), []>; 207} 208 209//===----------------------------------------------------------------------===// 210// Instructions 211//===----------------------------------------------------------------------===// 212 213// Pseudo instructions. 214class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern> 215 : InstSP<outs, ins, asmstr, pattern>; 216 217// GETPCX for PIC 218let Defs = [O7] in { 219 def GETPCX : Pseudo<(outs getPCX:$getpcseq), (ins), "$getpcseq", [] >; 220} 221 222let Defs = [O6], Uses = [O6] in { 223def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt), 224 "!ADJCALLSTACKDOWN $amt", 225 [(callseq_start timm:$amt)]>; 226def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2), 227 "!ADJCALLSTACKUP $amt1", 228 [(callseq_end timm:$amt1, timm:$amt2)]>; 229} 230 231let hasSideEffects = 1, mayStore = 1 in { 232 let rd = 0, rs1 = 0, rs2 = 0 in 233 def FLUSHW : F3_1<0b10, 0b101011, (outs), (ins), 234 "flushw", 235 [(flushw)]>, Requires<[HasV9]>; 236 let rd = 0, rs1 = 1, simm13 = 3 in 237 def TA3 : F3_2<0b10, 0b111010, (outs), (ins), 238 "ta 3", 239 [(flushw)]>; 240} 241 242def UNIMP : F2_1<0b000, (outs), (ins i32imm:$val), 243 "unimp $val", []>; 244 245// FpMOVD/FpNEGD/FpABSD - These are lowered to single-precision ops by the 246// fpmover pass. 247let Predicates = [HasNoV9] in { // Only emit these in V8 mode. 248 def FpMOVD : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$src), 249 "!FpMOVD $src, $dst", []>; 250 def FpNEGD : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$src), 251 "!FpNEGD $src, $dst", 252 [(set f64:$dst, (fneg f64:$src))]>; 253 def FpABSD : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$src), 254 "!FpABSD $src, $dst", 255 [(set f64:$dst, (fabs f64:$src))]>; 256} 257 258// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after 259// instruction selection into a branch sequence. This has to handle all 260// permutations of selection between i32/f32/f64 on ICC and FCC. 261 // Expanded after instruction selection. 262let Uses = [ICC], usesCustomInserter = 1 in { 263 def SELECT_CC_Int_ICC 264 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond), 265 "; SELECT_CC_Int_ICC PSEUDO!", 266 [(set i32:$dst, (SPselecticc i32:$T, i32:$F, imm:$Cond))]>; 267 def SELECT_CC_FP_ICC 268 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, i32imm:$Cond), 269 "; SELECT_CC_FP_ICC PSEUDO!", 270 [(set f32:$dst, (SPselecticc f32:$T, f32:$F, imm:$Cond))]>; 271 272 def SELECT_CC_DFP_ICC 273 : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, i32imm:$Cond), 274 "; SELECT_CC_DFP_ICC PSEUDO!", 275 [(set f64:$dst, (SPselecticc f64:$T, f64:$F, imm:$Cond))]>; 276} 277 278let usesCustomInserter = 1, Uses = [FCC] in { 279 280 def SELECT_CC_Int_FCC 281 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond), 282 "; SELECT_CC_Int_FCC PSEUDO!", 283 [(set i32:$dst, (SPselectfcc i32:$T, i32:$F, imm:$Cond))]>; 284 285 def SELECT_CC_FP_FCC 286 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, i32imm:$Cond), 287 "; SELECT_CC_FP_FCC PSEUDO!", 288 [(set f32:$dst, (SPselectfcc f32:$T, f32:$F, imm:$Cond))]>; 289 def SELECT_CC_DFP_FCC 290 : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, i32imm:$Cond), 291 "; SELECT_CC_DFP_FCC PSEUDO!", 292 [(set f64:$dst, (SPselectfcc f64:$T, f64:$F, imm:$Cond))]>; 293} 294 295 296// Section A.3 - Synthetic Instructions, p. 85 297// special cases of JMPL: 298let isReturn = 1, isTerminator = 1, hasDelaySlot = 1, isBarrier = 1 in { 299 let rd = O7.Num, rs1 = G0.Num in 300 def RETL: F3_2<2, 0b111000, (outs), (ins i32imm:$val), 301 "jmp %o7+$val", [(retflag simm13:$val)]>; 302 303 let rd = I7.Num, rs1 = G0.Num in 304 def RET: F3_2<2, 0b111000, (outs), (ins i32imm:$val), 305 "jmp %i7+$val", []>; 306} 307 308// Section B.1 - Load Integer Instructions, p. 90 309def LDSBrr : F3_1<3, 0b001001, 310 (outs IntRegs:$dst), (ins MEMrr:$addr), 311 "ldsb [$addr], $dst", 312 [(set i32:$dst, (sextloadi8 ADDRrr:$addr))]>; 313def LDSBri : F3_2<3, 0b001001, 314 (outs IntRegs:$dst), (ins MEMri:$addr), 315 "ldsb [$addr], $dst", 316 [(set i32:$dst, (sextloadi8 ADDRri:$addr))]>; 317def LDSHrr : F3_1<3, 0b001010, 318 (outs IntRegs:$dst), (ins MEMrr:$addr), 319 "ldsh [$addr], $dst", 320 [(set i32:$dst, (sextloadi16 ADDRrr:$addr))]>; 321def LDSHri : F3_2<3, 0b001010, 322 (outs IntRegs:$dst), (ins MEMri:$addr), 323 "ldsh [$addr], $dst", 324 [(set i32:$dst, (sextloadi16 ADDRri:$addr))]>; 325def LDUBrr : F3_1<3, 0b000001, 326 (outs IntRegs:$dst), (ins MEMrr:$addr), 327 "ldub [$addr], $dst", 328 [(set i32:$dst, (zextloadi8 ADDRrr:$addr))]>; 329def LDUBri : F3_2<3, 0b000001, 330 (outs IntRegs:$dst), (ins MEMri:$addr), 331 "ldub [$addr], $dst", 332 [(set i32:$dst, (zextloadi8 ADDRri:$addr))]>; 333def LDUHrr : F3_1<3, 0b000010, 334 (outs IntRegs:$dst), (ins MEMrr:$addr), 335 "lduh [$addr], $dst", 336 [(set i32:$dst, (zextloadi16 ADDRrr:$addr))]>; 337def LDUHri : F3_2<3, 0b000010, 338 (outs IntRegs:$dst), (ins MEMri:$addr), 339 "lduh [$addr], $dst", 340 [(set i32:$dst, (zextloadi16 ADDRri:$addr))]>; 341def LDrr : F3_1<3, 0b000000, 342 (outs IntRegs:$dst), (ins MEMrr:$addr), 343 "ld [$addr], $dst", 344 [(set i32:$dst, (load ADDRrr:$addr))]>; 345def LDri : F3_2<3, 0b000000, 346 (outs IntRegs:$dst), (ins MEMri:$addr), 347 "ld [$addr], $dst", 348 [(set i32:$dst, (load ADDRri:$addr))]>; 349 350// Section B.2 - Load Floating-point Instructions, p. 92 351def LDFrr : F3_1<3, 0b100000, 352 (outs FPRegs:$dst), (ins MEMrr:$addr), 353 "ld [$addr], $dst", 354 [(set f32:$dst, (load ADDRrr:$addr))]>; 355def LDFri : F3_2<3, 0b100000, 356 (outs FPRegs:$dst), (ins MEMri:$addr), 357 "ld [$addr], $dst", 358 [(set f32:$dst, (load ADDRri:$addr))]>; 359def LDDFrr : F3_1<3, 0b100011, 360 (outs DFPRegs:$dst), (ins MEMrr:$addr), 361 "ldd [$addr], $dst", 362 [(set f64:$dst, (load ADDRrr:$addr))]>; 363def LDDFri : F3_2<3, 0b100011, 364 (outs DFPRegs:$dst), (ins MEMri:$addr), 365 "ldd [$addr], $dst", 366 [(set f64:$dst, (load ADDRri:$addr))]>; 367 368// Section B.4 - Store Integer Instructions, p. 95 369def STBrr : F3_1<3, 0b000101, 370 (outs), (ins MEMrr:$addr, IntRegs:$src), 371 "stb $src, [$addr]", 372 [(truncstorei8 i32:$src, ADDRrr:$addr)]>; 373def STBri : F3_2<3, 0b000101, 374 (outs), (ins MEMri:$addr, IntRegs:$src), 375 "stb $src, [$addr]", 376 [(truncstorei8 i32:$src, ADDRri:$addr)]>; 377def STHrr : F3_1<3, 0b000110, 378 (outs), (ins MEMrr:$addr, IntRegs:$src), 379 "sth $src, [$addr]", 380 [(truncstorei16 i32:$src, ADDRrr:$addr)]>; 381def STHri : F3_2<3, 0b000110, 382 (outs), (ins MEMri:$addr, IntRegs:$src), 383 "sth $src, [$addr]", 384 [(truncstorei16 i32:$src, ADDRri:$addr)]>; 385def STrr : F3_1<3, 0b000100, 386 (outs), (ins MEMrr:$addr, IntRegs:$src), 387 "st $src, [$addr]", 388 [(store i32:$src, ADDRrr:$addr)]>; 389def STri : F3_2<3, 0b000100, 390 (outs), (ins MEMri:$addr, IntRegs:$src), 391 "st $src, [$addr]", 392 [(store i32:$src, ADDRri:$addr)]>; 393 394// Section B.5 - Store Floating-point Instructions, p. 97 395def STFrr : F3_1<3, 0b100100, 396 (outs), (ins MEMrr:$addr, FPRegs:$src), 397 "st $src, [$addr]", 398 [(store f32:$src, ADDRrr:$addr)]>; 399def STFri : F3_2<3, 0b100100, 400 (outs), (ins MEMri:$addr, FPRegs:$src), 401 "st $src, [$addr]", 402 [(store f32:$src, ADDRri:$addr)]>; 403def STDFrr : F3_1<3, 0b100111, 404 (outs), (ins MEMrr:$addr, DFPRegs:$src), 405 "std $src, [$addr]", 406 [(store f64:$src, ADDRrr:$addr)]>; 407def STDFri : F3_2<3, 0b100111, 408 (outs), (ins MEMri:$addr, DFPRegs:$src), 409 "std $src, [$addr]", 410 [(store f64:$src, ADDRri:$addr)]>; 411 412// Section B.9 - SETHI Instruction, p. 104 413def SETHIi: F2_1<0b100, 414 (outs IntRegs:$dst), (ins i32imm:$src), 415 "sethi $src, $dst", 416 [(set i32:$dst, SETHIimm:$src)]>; 417 418// Section B.10 - NOP Instruction, p. 105 419// (It's a special case of SETHI) 420let rd = 0, imm22 = 0 in 421 def NOP : F2_1<0b100, (outs), (ins), "nop", []>; 422 423// Section B.11 - Logical Instructions, p. 106 424defm AND : F3_12<"and", 0b000001, and>; 425 426def ANDNrr : F3_1<2, 0b000101, 427 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c), 428 "andn $b, $c, $dst", 429 [(set i32:$dst, (and i32:$b, (not i32:$c)))]>; 430def ANDNri : F3_2<2, 0b000101, 431 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c), 432 "andn $b, $c, $dst", []>; 433 434defm OR : F3_12<"or", 0b000010, or>; 435 436def ORNrr : F3_1<2, 0b000110, 437 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c), 438 "orn $b, $c, $dst", 439 [(set i32:$dst, (or i32:$b, (not i32:$c)))]>; 440def ORNri : F3_2<2, 0b000110, 441 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c), 442 "orn $b, $c, $dst", []>; 443defm XOR : F3_12<"xor", 0b000011, xor>; 444 445def XNORrr : F3_1<2, 0b000111, 446 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c), 447 "xnor $b, $c, $dst", 448 [(set i32:$dst, (not (xor i32:$b, i32:$c)))]>; 449def XNORri : F3_2<2, 0b000111, 450 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c), 451 "xnor $b, $c, $dst", []>; 452 453// Section B.12 - Shift Instructions, p. 107 454defm SLL : F3_12<"sll", 0b100101, shl>; 455defm SRL : F3_12<"srl", 0b100110, srl>; 456defm SRA : F3_12<"sra", 0b100111, sra>; 457 458// Section B.13 - Add Instructions, p. 108 459defm ADD : F3_12<"add", 0b000000, add>; 460 461// "LEA" forms of add (patterns to make tblgen happy) 462def LEA_ADDri : F3_2<2, 0b000000, 463 (outs IntRegs:$dst), (ins MEMri:$addr), 464 "add ${addr:arith}, $dst", 465 [(set i32:$dst, ADDRri:$addr)]>; 466 467let Defs = [ICC] in 468 defm ADDCC : F3_12<"addcc", 0b010000, addc>; 469 470let Uses = [ICC] in 471 defm ADDX : F3_12<"addx", 0b001000, adde>; 472 473// Section B.15 - Subtract Instructions, p. 110 474defm SUB : F3_12 <"sub" , 0b000100, sub>; 475let Uses = [ICC] in 476 defm SUBX : F3_12 <"subx" , 0b001100, sube>; 477 478let Defs = [ICC] in 479 defm SUBCC : F3_12 <"subcc", 0b010100, SPcmpicc>; 480 481let Uses = [ICC], Defs = [ICC] in 482 def SUBXCCrr: F3_1<2, 0b011100, 483 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c), 484 "subxcc $b, $c, $dst", []>; 485 486 487// Section B.18 - Multiply Instructions, p. 113 488let Defs = [Y] in { 489 defm UMUL : F3_12np<"umul", 0b001010>; 490 defm SMUL : F3_12 <"smul", 0b001011, mul>; 491} 492 493// Section B.19 - Divide Instructions, p. 115 494let Defs = [Y] in { 495 defm UDIV : F3_12np<"udiv", 0b001110>; 496 defm SDIV : F3_12np<"sdiv", 0b001111>; 497} 498 499// Section B.20 - SAVE and RESTORE, p. 117 500defm SAVE : F3_12np<"save" , 0b111100>; 501defm RESTORE : F3_12np<"restore", 0b111101>; 502 503// Section B.21 - Branch on Integer Condition Codes Instructions, p. 119 504 505// conditional branch class: 506class BranchSP<bits<4> cc, dag ins, string asmstr, list<dag> pattern> 507 : F2_2<cc, 0b010, (outs), ins, asmstr, pattern> { 508 let isBranch = 1; 509 let isTerminator = 1; 510 let hasDelaySlot = 1; 511} 512 513let isBarrier = 1 in 514 def BA : BranchSP<0b1000, (ins brtarget:$dst), 515 "ba $dst", 516 [(br bb:$dst)]>; 517 518// FIXME: the encoding for the JIT should look at the condition field. 519let Uses = [ICC] in 520 def BCOND : BranchSP<0, (ins brtarget:$dst, CCOp:$cc), 521 "b$cc $dst", 522 [(SPbricc bb:$dst, imm:$cc)]>; 523 524 525// Section B.22 - Branch on Floating-point Condition Codes Instructions, p. 121 526 527// floating-point conditional branch class: 528class FPBranchSP<bits<4> cc, dag ins, string asmstr, list<dag> pattern> 529 : F2_2<cc, 0b110, (outs), ins, asmstr, pattern> { 530 let isBranch = 1; 531 let isTerminator = 1; 532 let hasDelaySlot = 1; 533} 534 535// FIXME: the encoding for the JIT should look at the condition field. 536let Uses = [FCC] in 537 def FBCOND : FPBranchSP<0, (ins brtarget:$dst, CCOp:$cc), 538 "fb$cc $dst", 539 [(SPbrfcc bb:$dst, imm:$cc)]>; 540 541 542// Section B.24 - Call and Link Instruction, p. 125 543// This is the only Format 1 instruction 544let Uses = [O6], 545 hasDelaySlot = 1, isCall = 1, 546 Defs = [O0, O1, O2, O3, O4, O5, O7, G1, G2, G3, G4, G5, G6, G7, 547 D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15, 548 ICC, FCC, Y] in { 549 def CALL : InstSP<(outs), (ins calltarget:$dst, variable_ops), 550 "call $dst", []> { 551 bits<30> disp; 552 let op = 1; 553 let Inst{29-0} = disp; 554 } 555 556 // indirect calls 557 def JMPLrr : F3_1<2, 0b111000, 558 (outs), (ins MEMrr:$ptr, variable_ops), 559 "call $ptr", 560 [(call ADDRrr:$ptr)]>; 561 def JMPLri : F3_2<2, 0b111000, 562 (outs), (ins MEMri:$ptr, variable_ops), 563 "call $ptr", 564 [(call ADDRri:$ptr)]>; 565} 566 567// Section B.28 - Read State Register Instructions 568let Uses = [Y] in 569 def RDY : F3_1<2, 0b101000, 570 (outs IntRegs:$dst), (ins), 571 "rd %y, $dst", []>; 572 573// Section B.29 - Write State Register Instructions 574let Defs = [Y] in { 575 def WRYrr : F3_1<2, 0b110000, 576 (outs), (ins IntRegs:$b, IntRegs:$c), 577 "wr $b, $c, %y", []>; 578 def WRYri : F3_2<2, 0b110000, 579 (outs), (ins IntRegs:$b, i32imm:$c), 580 "wr $b, $c, %y", []>; 581} 582// Convert Integer to Floating-point Instructions, p. 141 583def FITOS : F3_3<2, 0b110100, 0b011000100, 584 (outs FPRegs:$dst), (ins FPRegs:$src), 585 "fitos $src, $dst", 586 [(set FPRegs:$dst, (SPitof FPRegs:$src))]>; 587def FITOD : F3_3<2, 0b110100, 0b011001000, 588 (outs DFPRegs:$dst), (ins FPRegs:$src), 589 "fitod $src, $dst", 590 [(set DFPRegs:$dst, (SPitof FPRegs:$src))]>; 591 592// Convert Floating-point to Integer Instructions, p. 142 593def FSTOI : F3_3<2, 0b110100, 0b011010001, 594 (outs FPRegs:$dst), (ins FPRegs:$src), 595 "fstoi $src, $dst", 596 [(set FPRegs:$dst, (SPftoi FPRegs:$src))]>; 597def FDTOI : F3_3<2, 0b110100, 0b011010010, 598 (outs FPRegs:$dst), (ins DFPRegs:$src), 599 "fdtoi $src, $dst", 600 [(set FPRegs:$dst, (SPftoi DFPRegs:$src))]>; 601 602// Convert between Floating-point Formats Instructions, p. 143 603def FSTOD : F3_3<2, 0b110100, 0b011001001, 604 (outs DFPRegs:$dst), (ins FPRegs:$src), 605 "fstod $src, $dst", 606 [(set f64:$dst, (fextend f32:$src))]>; 607def FDTOS : F3_3<2, 0b110100, 0b011000110, 608 (outs FPRegs:$dst), (ins DFPRegs:$src), 609 "fdtos $src, $dst", 610 [(set f32:$dst, (fround f64:$src))]>; 611 612// Floating-point Move Instructions, p. 144 613def FMOVS : F3_3<2, 0b110100, 0b000000001, 614 (outs FPRegs:$dst), (ins FPRegs:$src), 615 "fmovs $src, $dst", []>; 616def FNEGS : F3_3<2, 0b110100, 0b000000101, 617 (outs FPRegs:$dst), (ins FPRegs:$src), 618 "fnegs $src, $dst", 619 [(set f32:$dst, (fneg f32:$src))]>; 620def FABSS : F3_3<2, 0b110100, 0b000001001, 621 (outs FPRegs:$dst), (ins FPRegs:$src), 622 "fabss $src, $dst", 623 [(set f32:$dst, (fabs f32:$src))]>; 624 625 626// Floating-point Square Root Instructions, p.145 627def FSQRTS : F3_3<2, 0b110100, 0b000101001, 628 (outs FPRegs:$dst), (ins FPRegs:$src), 629 "fsqrts $src, $dst", 630 [(set f32:$dst, (fsqrt f32:$src))]>; 631def FSQRTD : F3_3<2, 0b110100, 0b000101010, 632 (outs DFPRegs:$dst), (ins DFPRegs:$src), 633 "fsqrtd $src, $dst", 634 [(set f64:$dst, (fsqrt f64:$src))]>; 635 636 637 638// Floating-point Add and Subtract Instructions, p. 146 639def FADDS : F3_3<2, 0b110100, 0b001000001, 640 (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2), 641 "fadds $src1, $src2, $dst", 642 [(set f32:$dst, (fadd f32:$src1, f32:$src2))]>; 643def FADDD : F3_3<2, 0b110100, 0b001000010, 644 (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2), 645 "faddd $src1, $src2, $dst", 646 [(set f64:$dst, (fadd f64:$src1, f64:$src2))]>; 647def FSUBS : F3_3<2, 0b110100, 0b001000101, 648 (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2), 649 "fsubs $src1, $src2, $dst", 650 [(set f32:$dst, (fsub f32:$src1, f32:$src2))]>; 651def FSUBD : F3_3<2, 0b110100, 0b001000110, 652 (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2), 653 "fsubd $src1, $src2, $dst", 654 [(set f64:$dst, (fsub f64:$src1, f64:$src2))]>; 655 656// Floating-point Multiply and Divide Instructions, p. 147 657def FMULS : F3_3<2, 0b110100, 0b001001001, 658 (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2), 659 "fmuls $src1, $src2, $dst", 660 [(set f32:$dst, (fmul f32:$src1, f32:$src2))]>; 661def FMULD : F3_3<2, 0b110100, 0b001001010, 662 (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2), 663 "fmuld $src1, $src2, $dst", 664 [(set f64:$dst, (fmul f64:$src1, f64:$src2))]>; 665def FSMULD : F3_3<2, 0b110100, 0b001101001, 666 (outs DFPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2), 667 "fsmuld $src1, $src2, $dst", 668 [(set f64:$dst, (fmul (fextend f32:$src1), 669 (fextend f32:$src2)))]>; 670def FDIVS : F3_3<2, 0b110100, 0b001001101, 671 (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2), 672 "fdivs $src1, $src2, $dst", 673 [(set f32:$dst, (fdiv f32:$src1, f32:$src2))]>; 674def FDIVD : F3_3<2, 0b110100, 0b001001110, 675 (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2), 676 "fdivd $src1, $src2, $dst", 677 [(set f64:$dst, (fdiv f64:$src1, f64:$src2))]>; 678 679// Floating-point Compare Instructions, p. 148 680// Note: the 2nd template arg is different for these guys. 681// Note 2: the result of a FCMP is not available until the 2nd cycle 682// after the instr is retired, but there is no interlock. This behavior 683// is modelled with a forced noop after the instruction. 684let Defs = [FCC] in { 685 def FCMPS : F3_3<2, 0b110101, 0b001010001, 686 (outs), (ins FPRegs:$src1, FPRegs:$src2), 687 "fcmps $src1, $src2\n\tnop", 688 [(SPcmpfcc f32:$src1, f32:$src2)]>; 689 def FCMPD : F3_3<2, 0b110101, 0b001010010, 690 (outs), (ins DFPRegs:$src1, DFPRegs:$src2), 691 "fcmpd $src1, $src2\n\tnop", 692 [(SPcmpfcc f64:$src1, f64:$src2)]>; 693} 694 695//===----------------------------------------------------------------------===// 696// V9 Instructions 697//===----------------------------------------------------------------------===// 698 699// V9 Conditional Moves. 700let Predicates = [HasV9], Constraints = "$T = $dst" in { 701 // Move Integer Register on Condition (MOVcc) p. 194 of the V9 manual. 702 // FIXME: Add instruction encodings for the JIT some day. 703 let Uses = [ICC] in { 704 def MOVICCrr 705 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, CCOp:$cc), 706 "mov$cc %icc, $F, $dst", 707 [(set i32:$dst, (SPselecticc i32:$F, i32:$T, imm:$cc))]>; 708 def MOVICCri 709 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, i32imm:$F, CCOp:$cc), 710 "mov$cc %icc, $F, $dst", 711 [(set i32:$dst, (SPselecticc simm11:$F, i32:$T, imm:$cc))]>; 712 } 713 714 let Uses = [FCC] in { 715 def MOVFCCrr 716 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, CCOp:$cc), 717 "mov$cc %fcc0, $F, $dst", 718 [(set i32:$dst, (SPselectfcc i32:$F, i32:$T, imm:$cc))]>; 719 def MOVFCCri 720 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, i32imm:$F, CCOp:$cc), 721 "mov$cc %fcc0, $F, $dst", 722 [(set i32:$dst, (SPselectfcc simm11:$F, i32:$T, imm:$cc))]>; 723 } 724 725 let Uses = [ICC] in { 726 def FMOVS_ICC 727 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, CCOp:$cc), 728 "fmovs$cc %icc, $F, $dst", 729 [(set f32:$dst, 730 (SPselecticc f32:$F, f32:$T, imm:$cc))]>; 731 def FMOVD_ICC 732 : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, CCOp:$cc), 733 "fmovd$cc %icc, $F, $dst", 734 [(set f64:$dst, (SPselecticc f64:$F, f64:$T, imm:$cc))]>; 735 } 736 737 let Uses = [FCC] in { 738 def FMOVS_FCC 739 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, CCOp:$cc), 740 "fmovs$cc %fcc0, $F, $dst", 741 [(set f32:$dst, (SPselectfcc f32:$F, f32:$T, imm:$cc))]>; 742 def FMOVD_FCC 743 : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, CCOp:$cc), 744 "fmovd$cc %fcc0, $F, $dst", 745 [(set f64:$dst, (SPselectfcc f64:$F, f64:$T, imm:$cc))]>; 746 } 747 748} 749 750// Floating-Point Move Instructions, p. 164 of the V9 manual. 751let Predicates = [HasV9] in { 752 def FMOVD : F3_3<2, 0b110100, 0b000000010, 753 (outs DFPRegs:$dst), (ins DFPRegs:$src), 754 "fmovd $src, $dst", []>; 755 def FNEGD : F3_3<2, 0b110100, 0b000000110, 756 (outs DFPRegs:$dst), (ins DFPRegs:$src), 757 "fnegd $src, $dst", 758 [(set f64:$dst, (fneg f64:$src))]>; 759 def FABSD : F3_3<2, 0b110100, 0b000001010, 760 (outs DFPRegs:$dst), (ins DFPRegs:$src), 761 "fabsd $src, $dst", 762 [(set f64:$dst, (fabs f64:$src))]>; 763} 764 765// POPCrr - This does a ctpop of a 64-bit register. As such, we have to clear 766// the top 32-bits before using it. To do this clearing, we use a SLLri X,0. 767def POPCrr : F3_1<2, 0b101110, 768 (outs IntRegs:$dst), (ins IntRegs:$src), 769 "popc $src, $dst", []>, Requires<[HasV9]>; 770def : Pat<(ctpop i32:$src), 771 (POPCrr (SLLri $src, 0))>; 772 773//===----------------------------------------------------------------------===// 774// Non-Instruction Patterns 775//===----------------------------------------------------------------------===// 776 777// Small immediates. 778def : Pat<(i32 simm13:$val), 779 (ORri (i32 G0), imm:$val)>; 780// Arbitrary immediates. 781def : Pat<(i32 imm:$val), 782 (ORri (SETHIi (HI22 imm:$val)), (LO10 imm:$val))>; 783 784// subc 785def : Pat<(subc i32:$b, i32:$c), 786 (SUBCCrr $b, $c)>; 787def : Pat<(subc i32:$b, simm13:$val), 788 (SUBCCri $b, imm:$val)>; 789 790// Global addresses, constant pool entries 791def : Pat<(SPhi tglobaladdr:$in), (SETHIi tglobaladdr:$in)>; 792def : Pat<(SPlo tglobaladdr:$in), (ORri (i32 G0), tglobaladdr:$in)>; 793def : Pat<(SPhi tconstpool:$in), (SETHIi tconstpool:$in)>; 794def : Pat<(SPlo tconstpool:$in), (ORri (i32 G0), tconstpool:$in)>; 795 796// Add reg, lo. This is used when taking the addr of a global/constpool entry. 797def : Pat<(add i32:$r, (SPlo tglobaladdr:$in)), 798 (ADDri $r, tglobaladdr:$in)>; 799def : Pat<(add i32:$r, (SPlo tconstpool:$in)), 800 (ADDri $r, tconstpool:$in)>; 801 802// Calls: 803def : Pat<(call tglobaladdr:$dst), 804 (CALL tglobaladdr:$dst)>; 805def : Pat<(call texternalsym:$dst), 806 (CALL texternalsym:$dst)>; 807 808// Map integer extload's to zextloads. 809def : Pat<(i32 (extloadi1 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>; 810def : Pat<(i32 (extloadi1 ADDRri:$src)), (LDUBri ADDRri:$src)>; 811def : Pat<(i32 (extloadi8 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>; 812def : Pat<(i32 (extloadi8 ADDRri:$src)), (LDUBri ADDRri:$src)>; 813def : Pat<(i32 (extloadi16 ADDRrr:$src)), (LDUHrr ADDRrr:$src)>; 814def : Pat<(i32 (extloadi16 ADDRri:$src)), (LDUHri ADDRri:$src)>; 815 816// zextload bool -> zextload byte 817def : Pat<(i32 (zextloadi1 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>; 818def : Pat<(i32 (zextloadi1 ADDRri:$src)), (LDUBri ADDRri:$src)>; 819 820include "SparcInstr64Bit.td" 821