SparcInstrInfo.td revision c69107ca11282a905c252d1b62091951087f13dc
1//===- SparcInstrInfo.td - Target Description for Sparc Target ------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the Sparc instructions in TableGen format. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// Instruction format superclass 16//===----------------------------------------------------------------------===// 17 18include "SparcInstrFormats.td" 19 20//===----------------------------------------------------------------------===// 21// Feature predicates. 22//===----------------------------------------------------------------------===// 23 24// HasV9 - This predicate is true when the target processor supports V9 25// instructions. Note that the machine may be running in 32-bit mode. 26def HasV9 : Predicate<"Subtarget.isV9()">; 27 28// HasNoV9 - This predicate is true when the target doesn't have V9 29// instructions. Use of this is just a hack for the isel not having proper 30// costs for V8 instructions that are more expensive than their V9 ones. 31def HasNoV9 : Predicate<"!Subtarget.isV9()">; 32 33// HasVIS - This is true when the target processor has VIS extensions. 34def HasVIS : Predicate<"Subtarget.isVIS()">; 35 36// UseDeprecatedInsts - This predicate is true when the target processor is a 37// V8, or when it is V9 but the V8 deprecated instructions are efficient enough 38// to use when appropriate. In either of these cases, the instruction selector 39// will pick deprecated instructions. 40def UseDeprecatedInsts : Predicate<"Subtarget.useDeprecatedV8Instructions()">; 41 42//===----------------------------------------------------------------------===// 43// Instruction Pattern Stuff 44//===----------------------------------------------------------------------===// 45 46def simm11 : PatLeaf<(imm), [{ 47 // simm11 predicate - True if the imm fits in a 11-bit sign extended field. 48 return (((int)N->getValue() << (32-11)) >> (32-11)) == (int)N->getValue(); 49}]>; 50 51def simm13 : PatLeaf<(imm), [{ 52 // simm13 predicate - True if the imm fits in a 13-bit sign extended field. 53 return (((int)N->getValue() << (32-13)) >> (32-13)) == (int)N->getValue(); 54}]>; 55 56def LO10 : SDNodeXForm<imm, [{ 57 return CurDAG->getTargetConstant((unsigned)N->getValue() & 1023, MVT::i32); 58}]>; 59 60def HI22 : SDNodeXForm<imm, [{ 61 // Transformation function: shift the immediate value down into the low bits. 62 return CurDAG->getTargetConstant((unsigned)N->getValue() >> 10, MVT::i32); 63}]>; 64 65def SETHIimm : PatLeaf<(imm), [{ 66 return (((unsigned)N->getValue() >> 10) << 10) == (unsigned)N->getValue(); 67}], HI22>; 68 69// Addressing modes. 70def ADDRrr : ComplexPattern<i32, 2, "SelectADDRrr", [], []>; 71def ADDRri : ComplexPattern<i32, 2, "SelectADDRri", [frameindex], []>; 72 73// Address operands 74def MEMrr : Operand<i32> { 75 let PrintMethod = "printMemOperand"; 76 let MIOperandInfo = (ops IntRegs, IntRegs); 77} 78def MEMri : Operand<i32> { 79 let PrintMethod = "printMemOperand"; 80 let MIOperandInfo = (ops IntRegs, i32imm); 81} 82 83// Branch targets have OtherVT type. 84def brtarget : Operand<OtherVT>; 85def calltarget : Operand<i32>; 86 87// Operand for printing out a condition code. 88let PrintMethod = "printCCOperand" in 89 def CCOp : Operand<i32>; 90 91def SDTSPcmpfcc : 92SDTypeProfile<0, 2, [SDTCisFP<0>, SDTCisSameAs<0, 1>]>; 93def SDTSPbrcc : 94SDTypeProfile<0, 2, [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>; 95def SDTSPselectcc : 96SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>]>; 97def SDTSPFTOI : 98SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisFP<1>]>; 99def SDTSPITOF : 100SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f32>]>; 101 102def SPcmpicc : SDNode<"SPISD::CMPICC", SDTIntBinOp, [SDNPOutFlag]>; 103def SPcmpfcc : SDNode<"SPISD::CMPFCC", SDTSPcmpfcc, [SDNPOutFlag]>; 104def SPbricc : SDNode<"SPISD::BRICC", SDTSPbrcc, [SDNPHasChain, SDNPInFlag]>; 105def SPbrfcc : SDNode<"SPISD::BRFCC", SDTSPbrcc, [SDNPHasChain, SDNPInFlag]>; 106 107def SPhi : SDNode<"SPISD::Hi", SDTIntUnaryOp>; 108def SPlo : SDNode<"SPISD::Lo", SDTIntUnaryOp>; 109 110def SPftoi : SDNode<"SPISD::FTOI", SDTSPFTOI>; 111def SPitof : SDNode<"SPISD::ITOF", SDTSPITOF>; 112 113def SPselecticc : SDNode<"SPISD::SELECT_ICC", SDTSPselectcc, [SDNPInFlag]>; 114def SPselectfcc : SDNode<"SPISD::SELECT_FCC", SDTSPselectcc, [SDNPInFlag]>; 115 116// These are target-independent nodes, but have target-specific formats. 117def SDT_SPCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>; 118def SDT_SPCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, 119 SDTCisVT<1, i32> ]>; 120 121def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_SPCallSeqStart, 122 [SDNPHasChain, SDNPOutFlag]>; 123def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_SPCallSeqEnd, 124 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; 125 126def SDT_SPCall : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>; 127def call : SDNode<"SPISD::CALL", SDT_SPCall, 128 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; 129 130def SDT_SPRetFlag : SDTypeProfile<0, 0, []>; 131def retflag : SDNode<"SPISD::RET_FLAG", SDT_SPRetFlag, 132 [SDNPHasChain, SDNPOptInFlag]>; 133 134//===----------------------------------------------------------------------===// 135// SPARC Flag Conditions 136//===----------------------------------------------------------------------===// 137 138// Note that these values must be kept in sync with the CCOp::CondCode enum 139// values. 140class ICC_VAL<int N> : PatLeaf<(i32 N)>; 141def ICC_NE : ICC_VAL< 9>; // Not Equal 142def ICC_E : ICC_VAL< 1>; // Equal 143def ICC_G : ICC_VAL<10>; // Greater 144def ICC_LE : ICC_VAL< 2>; // Less or Equal 145def ICC_GE : ICC_VAL<11>; // Greater or Equal 146def ICC_L : ICC_VAL< 3>; // Less 147def ICC_GU : ICC_VAL<12>; // Greater Unsigned 148def ICC_LEU : ICC_VAL< 4>; // Less or Equal Unsigned 149def ICC_CC : ICC_VAL<13>; // Carry Clear/Great or Equal Unsigned 150def ICC_CS : ICC_VAL< 5>; // Carry Set/Less Unsigned 151def ICC_POS : ICC_VAL<14>; // Positive 152def ICC_NEG : ICC_VAL< 6>; // Negative 153def ICC_VC : ICC_VAL<15>; // Overflow Clear 154def ICC_VS : ICC_VAL< 7>; // Overflow Set 155 156class FCC_VAL<int N> : PatLeaf<(i32 N)>; 157def FCC_U : FCC_VAL<23>; // Unordered 158def FCC_G : FCC_VAL<22>; // Greater 159def FCC_UG : FCC_VAL<21>; // Unordered or Greater 160def FCC_L : FCC_VAL<20>; // Less 161def FCC_UL : FCC_VAL<19>; // Unordered or Less 162def FCC_LG : FCC_VAL<18>; // Less or Greater 163def FCC_NE : FCC_VAL<17>; // Not Equal 164def FCC_E : FCC_VAL<25>; // Equal 165def FCC_UE : FCC_VAL<24>; // Unordered or Equal 166def FCC_GE : FCC_VAL<25>; // Greater or Equal 167def FCC_UGE : FCC_VAL<26>; // Unordered or Greater or Equal 168def FCC_LE : FCC_VAL<27>; // Less or Equal 169def FCC_ULE : FCC_VAL<28>; // Unordered or Less or Equal 170def FCC_O : FCC_VAL<29>; // Ordered 171 172//===----------------------------------------------------------------------===// 173// Instruction Class Templates 174//===----------------------------------------------------------------------===// 175 176/// F3_12 multiclass - Define a normal F3_1/F3_2 pattern in one shot. 177multiclass F3_12<string OpcStr, bits<6> Op3Val, SDNode OpNode> { 178 def rr : F3_1<2, Op3Val, 179 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c), 180 !strconcat(OpcStr, " $b, $c, $dst"), 181 [(set IntRegs:$dst, (OpNode IntRegs:$b, IntRegs:$c))]>; 182 def ri : F3_2<2, Op3Val, 183 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c), 184 !strconcat(OpcStr, " $b, $c, $dst"), 185 [(set IntRegs:$dst, (OpNode IntRegs:$b, simm13:$c))]>; 186} 187 188/// F3_12np multiclass - Define a normal F3_1/F3_2 pattern in one shot, with no 189/// pattern. 190multiclass F3_12np<string OpcStr, bits<6> Op3Val> { 191 def rr : F3_1<2, Op3Val, 192 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c), 193 !strconcat(OpcStr, " $b, $c, $dst"), []>; 194 def ri : F3_2<2, Op3Val, 195 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c), 196 !strconcat(OpcStr, " $b, $c, $dst"), []>; 197} 198 199//===----------------------------------------------------------------------===// 200// Instructions 201//===----------------------------------------------------------------------===// 202 203// Pseudo instructions. 204class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern> 205 : InstSP<outs, ins, asmstr, pattern>; 206 207let Defs = [O6], Uses = [O6] in { 208def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt), 209 "!ADJCALLSTACKDOWN $amt", 210 [(callseq_start imm:$amt)]>; 211def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2), 212 "!ADJCALLSTACKUP $amt1", 213 [(callseq_end imm:$amt1, imm:$amt2)]>; 214} 215def IMPLICIT_DEF_Int : Pseudo<(outs IntRegs:$dst), (ins), 216 "!IMPLICIT_DEF $dst", 217 [(set IntRegs:$dst, (undef))]>; 218def IMPLICIT_DEF_FP : Pseudo<(outs FPRegs:$dst), (ins), "!IMPLICIT_DEF $dst", 219 [(set FPRegs:$dst, (undef))]>; 220def IMPLICIT_DEF_DFP : Pseudo<(outs DFPRegs:$dst), (ins), "!IMPLICIT_DEF $dst", 221 [(set DFPRegs:$dst, (undef))]>; 222 223// FpMOVD/FpNEGD/FpABSD - These are lowered to single-precision ops by the 224// fpmover pass. 225let Predicates = [HasNoV9] in { // Only emit these in V8 mode. 226 def FpMOVD : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$src), 227 "!FpMOVD $src, $dst", []>; 228 def FpNEGD : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$src), 229 "!FpNEGD $src, $dst", 230 [(set DFPRegs:$dst, (fneg DFPRegs:$src))]>; 231 def FpABSD : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$src), 232 "!FpABSD $src, $dst", 233 [(set DFPRegs:$dst, (fabs DFPRegs:$src))]>; 234} 235 236// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded by the 237// scheduler into a branch sequence. This has to handle all permutations of 238// selection between i32/f32/f64 on ICC and FCC. 239let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler. 240 def SELECT_CC_Int_ICC 241 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond), 242 "; SELECT_CC_Int_ICC PSEUDO!", 243 [(set IntRegs:$dst, (SPselecticc IntRegs:$T, IntRegs:$F, 244 imm:$Cond))]>; 245 def SELECT_CC_Int_FCC 246 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond), 247 "; SELECT_CC_Int_FCC PSEUDO!", 248 [(set IntRegs:$dst, (SPselectfcc IntRegs:$T, IntRegs:$F, 249 imm:$Cond))]>; 250 def SELECT_CC_FP_ICC 251 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, i32imm:$Cond), 252 "; SELECT_CC_FP_ICC PSEUDO!", 253 [(set FPRegs:$dst, (SPselecticc FPRegs:$T, FPRegs:$F, 254 imm:$Cond))]>; 255 def SELECT_CC_FP_FCC 256 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, i32imm:$Cond), 257 "; SELECT_CC_FP_FCC PSEUDO!", 258 [(set FPRegs:$dst, (SPselectfcc FPRegs:$T, FPRegs:$F, 259 imm:$Cond))]>; 260 def SELECT_CC_DFP_ICC 261 : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, i32imm:$Cond), 262 "; SELECT_CC_DFP_ICC PSEUDO!", 263 [(set DFPRegs:$dst, (SPselecticc DFPRegs:$T, DFPRegs:$F, 264 imm:$Cond))]>; 265 def SELECT_CC_DFP_FCC 266 : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, i32imm:$Cond), 267 "; SELECT_CC_DFP_FCC PSEUDO!", 268 [(set DFPRegs:$dst, (SPselectfcc DFPRegs:$T, DFPRegs:$F, 269 imm:$Cond))]>; 270} 271 272 273// Section A.3 - Synthetic Instructions, p. 85 274// special cases of JMPL: 275let isReturn = 1, isTerminator = 1, hasDelaySlot = 1 in { 276 let rd = O7.Num, rs1 = G0.Num, simm13 = 8 in 277 def RETL: F3_2<2, 0b111000, (outs), (ins), "retl", [(retflag)]>; 278} 279 280// Section B.1 - Load Integer Instructions, p. 90 281def LDSBrr : F3_1<3, 0b001001, 282 (outs IntRegs:$dst), (ins MEMrr:$addr), 283 "ldsb [$addr], $dst", 284 [(set IntRegs:$dst, (sextloadi8 ADDRrr:$addr))]>; 285def LDSBri : F3_2<3, 0b001001, 286 (outs IntRegs:$dst), (ins MEMri:$addr), 287 "ldsb [$addr], $dst", 288 [(set IntRegs:$dst, (sextloadi8 ADDRri:$addr))]>; 289def LDSHrr : F3_1<3, 0b001010, 290 (outs IntRegs:$dst), (ins MEMrr:$addr), 291 "ldsh [$addr], $dst", 292 [(set IntRegs:$dst, (sextloadi16 ADDRrr:$addr))]>; 293def LDSHri : F3_2<3, 0b001010, 294 (outs IntRegs:$dst), (ins MEMri:$addr), 295 "ldsh [$addr], $dst", 296 [(set IntRegs:$dst, (sextloadi16 ADDRri:$addr))]>; 297def LDUBrr : F3_1<3, 0b000001, 298 (outs IntRegs:$dst), (ins MEMrr:$addr), 299 "ldub [$addr], $dst", 300 [(set IntRegs:$dst, (zextloadi8 ADDRrr:$addr))]>; 301def LDUBri : F3_2<3, 0b000001, 302 (outs IntRegs:$dst), (ins MEMri:$addr), 303 "ldub [$addr], $dst", 304 [(set IntRegs:$dst, (zextloadi8 ADDRri:$addr))]>; 305def LDUHrr : F3_1<3, 0b000010, 306 (outs IntRegs:$dst), (ins MEMrr:$addr), 307 "lduh [$addr], $dst", 308 [(set IntRegs:$dst, (zextloadi16 ADDRrr:$addr))]>; 309def LDUHri : F3_2<3, 0b000010, 310 (outs IntRegs:$dst), (ins MEMri:$addr), 311 "lduh [$addr], $dst", 312 [(set IntRegs:$dst, (zextloadi16 ADDRri:$addr))]>; 313def LDrr : F3_1<3, 0b000000, 314 (outs IntRegs:$dst), (ins MEMrr:$addr), 315 "ld [$addr], $dst", 316 [(set IntRegs:$dst, (load ADDRrr:$addr))]>; 317def LDri : F3_2<3, 0b000000, 318 (outs IntRegs:$dst), (ins MEMri:$addr), 319 "ld [$addr], $dst", 320 [(set IntRegs:$dst, (load ADDRri:$addr))]>; 321 322// Section B.2 - Load Floating-point Instructions, p. 92 323def LDFrr : F3_1<3, 0b100000, 324 (outs FPRegs:$dst), (ins MEMrr:$addr), 325 "ld [$addr], $dst", 326 [(set FPRegs:$dst, (load ADDRrr:$addr))]>; 327def LDFri : F3_2<3, 0b100000, 328 (outs FPRegs:$dst), (ins MEMri:$addr), 329 "ld [$addr], $dst", 330 [(set FPRegs:$dst, (load ADDRri:$addr))]>; 331def LDDFrr : F3_1<3, 0b100011, 332 (outs DFPRegs:$dst), (ins MEMrr:$addr), 333 "ldd [$addr], $dst", 334 [(set DFPRegs:$dst, (load ADDRrr:$addr))]>; 335def LDDFri : F3_2<3, 0b100011, 336 (outs DFPRegs:$dst), (ins MEMri:$addr), 337 "ldd [$addr], $dst", 338 [(set DFPRegs:$dst, (load ADDRri:$addr))]>; 339 340// Section B.4 - Store Integer Instructions, p. 95 341def STBrr : F3_1<3, 0b000101, 342 (outs), (ins MEMrr:$addr, IntRegs:$src), 343 "stb $src, [$addr]", 344 [(truncstorei8 IntRegs:$src, ADDRrr:$addr)]>; 345def STBri : F3_2<3, 0b000101, 346 (outs), (ins MEMri:$addr, IntRegs:$src), 347 "stb $src, [$addr]", 348 [(truncstorei8 IntRegs:$src, ADDRri:$addr)]>; 349def STHrr : F3_1<3, 0b000110, 350 (outs), (ins MEMrr:$addr, IntRegs:$src), 351 "sth $src, [$addr]", 352 [(truncstorei16 IntRegs:$src, ADDRrr:$addr)]>; 353def STHri : F3_2<3, 0b000110, 354 (outs), (ins MEMri:$addr, IntRegs:$src), 355 "sth $src, [$addr]", 356 [(truncstorei16 IntRegs:$src, ADDRri:$addr)]>; 357def STrr : F3_1<3, 0b000100, 358 (outs), (ins MEMrr:$addr, IntRegs:$src), 359 "st $src, [$addr]", 360 [(store IntRegs:$src, ADDRrr:$addr)]>; 361def STri : F3_2<3, 0b000100, 362 (outs), (ins MEMri:$addr, IntRegs:$src), 363 "st $src, [$addr]", 364 [(store IntRegs:$src, ADDRri:$addr)]>; 365 366// Section B.5 - Store Floating-point Instructions, p. 97 367def STFrr : F3_1<3, 0b100100, 368 (outs), (ins MEMrr:$addr, FPRegs:$src), 369 "st $src, [$addr]", 370 [(store FPRegs:$src, ADDRrr:$addr)]>; 371def STFri : F3_2<3, 0b100100, 372 (outs), (ins MEMri:$addr, FPRegs:$src), 373 "st $src, [$addr]", 374 [(store FPRegs:$src, ADDRri:$addr)]>; 375def STDFrr : F3_1<3, 0b100111, 376 (outs), (ins MEMrr:$addr, DFPRegs:$src), 377 "std $src, [$addr]", 378 [(store DFPRegs:$src, ADDRrr:$addr)]>; 379def STDFri : F3_2<3, 0b100111, 380 (outs), (ins MEMri:$addr, DFPRegs:$src), 381 "std $src, [$addr]", 382 [(store DFPRegs:$src, ADDRri:$addr)]>; 383 384// Section B.9 - SETHI Instruction, p. 104 385def SETHIi: F2_1<0b100, 386 (outs IntRegs:$dst), (ins i32imm:$src), 387 "sethi $src, $dst", 388 [(set IntRegs:$dst, SETHIimm:$src)]>; 389 390// Section B.10 - NOP Instruction, p. 105 391// (It's a special case of SETHI) 392let rd = 0, imm22 = 0 in 393 def NOP : F2_1<0b100, (outs), (ins), "nop", []>; 394 395// Section B.11 - Logical Instructions, p. 106 396defm AND : F3_12<"and", 0b000001, and>; 397 398def ANDNrr : F3_1<2, 0b000101, 399 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c), 400 "andn $b, $c, $dst", 401 [(set IntRegs:$dst, (and IntRegs:$b, (not IntRegs:$c)))]>; 402def ANDNri : F3_2<2, 0b000101, 403 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c), 404 "andn $b, $c, $dst", []>; 405 406defm OR : F3_12<"or", 0b000010, or>; 407 408def ORNrr : F3_1<2, 0b000110, 409 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c), 410 "orn $b, $c, $dst", 411 [(set IntRegs:$dst, (or IntRegs:$b, (not IntRegs:$c)))]>; 412def ORNri : F3_2<2, 0b000110, 413 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c), 414 "orn $b, $c, $dst", []>; 415defm XOR : F3_12<"xor", 0b000011, xor>; 416 417def XNORrr : F3_1<2, 0b000111, 418 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c), 419 "xnor $b, $c, $dst", 420 [(set IntRegs:$dst, (not (xor IntRegs:$b, IntRegs:$c)))]>; 421def XNORri : F3_2<2, 0b000111, 422 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c), 423 "xnor $b, $c, $dst", []>; 424 425// Section B.12 - Shift Instructions, p. 107 426defm SLL : F3_12<"sll", 0b100101, shl>; 427defm SRL : F3_12<"srl", 0b100110, srl>; 428defm SRA : F3_12<"sra", 0b100111, sra>; 429 430// Section B.13 - Add Instructions, p. 108 431defm ADD : F3_12<"add", 0b000000, add>; 432 433// "LEA" forms of add (patterns to make tblgen happy) 434def LEA_ADDri : F3_2<2, 0b000000, 435 (outs IntRegs:$dst), (ins MEMri:$addr), 436 "add ${addr:arith}, $dst", 437 [(set IntRegs:$dst, ADDRri:$addr)]>; 438 439defm ADDCC : F3_12<"addcc", 0b010000, addc>; 440defm ADDX : F3_12<"addx", 0b001000, adde>; 441 442// Section B.15 - Subtract Instructions, p. 110 443defm SUB : F3_12 <"sub" , 0b000100, sub>; 444defm SUBX : F3_12 <"subx" , 0b001100, sube>; 445defm SUBCC : F3_12 <"subcc", 0b010100, SPcmpicc>; 446 447def SUBXCCrr: F3_1<2, 0b011100, 448 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c), 449 "subxcc $b, $c, $dst", []>; 450 451// Section B.18 - Multiply Instructions, p. 113 452defm UMUL : F3_12np<"umul", 0b001010>; 453defm SMUL : F3_12 <"smul", 0b001011, mul>; 454 455 456// Section B.19 - Divide Instructions, p. 115 457defm UDIV : F3_12np<"udiv", 0b001110>; 458defm SDIV : F3_12np<"sdiv", 0b001111>; 459 460// Section B.20 - SAVE and RESTORE, p. 117 461defm SAVE : F3_12np<"save" , 0b111100>; 462defm RESTORE : F3_12np<"restore", 0b111101>; 463 464// Section B.21 - Branch on Integer Condition Codes Instructions, p. 119 465 466// conditional branch class: 467class BranchSP<bits<4> cc, dag ins, string asmstr, list<dag> pattern> 468 : F2_2<cc, 0b010, (outs), ins, asmstr, pattern> { 469 let isBranch = 1; 470 let isTerminator = 1; 471 let hasDelaySlot = 1; 472} 473 474let isBarrier = 1 in 475 def BA : BranchSP<0b1000, (ins brtarget:$dst), 476 "ba $dst", 477 [(br bb:$dst)]>; 478 479// FIXME: the encoding for the JIT should look at the condition field. 480def BCOND : BranchSP<0, (ins brtarget:$dst, CCOp:$cc), 481 "b$cc $dst", 482 [(SPbricc bb:$dst, imm:$cc)]>; 483 484 485// Section B.22 - Branch on Floating-point Condition Codes Instructions, p. 121 486 487// floating-point conditional branch class: 488class FPBranchSP<bits<4> cc, dag ins, string asmstr, list<dag> pattern> 489 : F2_2<cc, 0b110, (outs), ins, asmstr, pattern> { 490 let isBranch = 1; 491 let isTerminator = 1; 492 let hasDelaySlot = 1; 493} 494 495// FIXME: the encoding for the JIT should look at the condition field. 496def FBCOND : FPBranchSP<0, (ins brtarget:$dst, CCOp:$cc), 497 "fb$cc $dst", 498 [(SPbrfcc bb:$dst, imm:$cc)]>; 499 500 501// Section B.24 - Call and Link Instruction, p. 125 502// This is the only Format 1 instruction 503let Uses = [O0, O1, O2, O3, O4, O5], 504 hasDelaySlot = 1, isCall = 1, 505 Defs = [O0, O1, O2, O3, O4, O5, O7, G1, G2, G3, G4, G5, G6, G7, 506 D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15] in { 507 def CALL : InstSP<(outs), (ins calltarget:$dst), 508 "call $dst", []> { 509 bits<30> disp; 510 let op = 1; 511 let Inst{29-0} = disp; 512 } 513 514 // indirect calls 515 def JMPLrr : F3_1<2, 0b111000, 516 (outs), (ins MEMrr:$ptr), 517 "call $ptr", 518 [(call ADDRrr:$ptr)]>; 519 def JMPLri : F3_2<2, 0b111000, 520 (outs), (ins MEMri:$ptr), 521 "call $ptr", 522 [(call ADDRri:$ptr)]>; 523} 524 525// Section B.28 - Read State Register Instructions 526def RDY : F3_1<2, 0b101000, 527 (outs IntRegs:$dst), (ins), 528 "rd %y, $dst", []>; 529 530// Section B.29 - Write State Register Instructions 531def WRYrr : F3_1<2, 0b110000, 532 (outs), (ins IntRegs:$b, IntRegs:$c), 533 "wr $b, $c, %y", []>; 534def WRYri : F3_2<2, 0b110000, 535 (outs), (ins IntRegs:$b, i32imm:$c), 536 "wr $b, $c, %y", []>; 537 538// Convert Integer to Floating-point Instructions, p. 141 539def FITOS : F3_3<2, 0b110100, 0b011000100, 540 (outs FPRegs:$dst), (ins FPRegs:$src), 541 "fitos $src, $dst", 542 [(set FPRegs:$dst, (SPitof FPRegs:$src))]>; 543def FITOD : F3_3<2, 0b110100, 0b011001000, 544 (outs DFPRegs:$dst), (ins FPRegs:$src), 545 "fitod $src, $dst", 546 [(set DFPRegs:$dst, (SPitof FPRegs:$src))]>; 547 548// Convert Floating-point to Integer Instructions, p. 142 549def FSTOI : F3_3<2, 0b110100, 0b011010001, 550 (outs FPRegs:$dst), (ins FPRegs:$src), 551 "fstoi $src, $dst", 552 [(set FPRegs:$dst, (SPftoi FPRegs:$src))]>; 553def FDTOI : F3_3<2, 0b110100, 0b011010010, 554 (outs FPRegs:$dst), (ins DFPRegs:$src), 555 "fdtoi $src, $dst", 556 [(set FPRegs:$dst, (SPftoi DFPRegs:$src))]>; 557 558// Convert between Floating-point Formats Instructions, p. 143 559def FSTOD : F3_3<2, 0b110100, 0b011001001, 560 (outs DFPRegs:$dst), (ins FPRegs:$src), 561 "fstod $src, $dst", 562 [(set DFPRegs:$dst, (fextend FPRegs:$src))]>; 563def FDTOS : F3_3<2, 0b110100, 0b011000110, 564 (outs FPRegs:$dst), (ins DFPRegs:$src), 565 "fdtos $src, $dst", 566 [(set FPRegs:$dst, (fround DFPRegs:$src))]>; 567 568// Floating-point Move Instructions, p. 144 569def FMOVS : F3_3<2, 0b110100, 0b000000001, 570 (outs FPRegs:$dst), (ins FPRegs:$src), 571 "fmovs $src, $dst", []>; 572def FNEGS : F3_3<2, 0b110100, 0b000000101, 573 (outs FPRegs:$dst), (ins FPRegs:$src), 574 "fnegs $src, $dst", 575 [(set FPRegs:$dst, (fneg FPRegs:$src))]>; 576def FABSS : F3_3<2, 0b110100, 0b000001001, 577 (outs FPRegs:$dst), (ins FPRegs:$src), 578 "fabss $src, $dst", 579 [(set FPRegs:$dst, (fabs FPRegs:$src))]>; 580 581 582// Floating-point Square Root Instructions, p.145 583def FSQRTS : F3_3<2, 0b110100, 0b000101001, 584 (outs FPRegs:$dst), (ins FPRegs:$src), 585 "fsqrts $src, $dst", 586 [(set FPRegs:$dst, (fsqrt FPRegs:$src))]>; 587def FSQRTD : F3_3<2, 0b110100, 0b000101010, 588 (outs DFPRegs:$dst), (ins DFPRegs:$src), 589 "fsqrtd $src, $dst", 590 [(set DFPRegs:$dst, (fsqrt DFPRegs:$src))]>; 591 592 593 594// Floating-point Add and Subtract Instructions, p. 146 595def FADDS : F3_3<2, 0b110100, 0b001000001, 596 (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2), 597 "fadds $src1, $src2, $dst", 598 [(set FPRegs:$dst, (fadd FPRegs:$src1, FPRegs:$src2))]>; 599def FADDD : F3_3<2, 0b110100, 0b001000010, 600 (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2), 601 "faddd $src1, $src2, $dst", 602 [(set DFPRegs:$dst, (fadd DFPRegs:$src1, DFPRegs:$src2))]>; 603def FSUBS : F3_3<2, 0b110100, 0b001000101, 604 (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2), 605 "fsubs $src1, $src2, $dst", 606 [(set FPRegs:$dst, (fsub FPRegs:$src1, FPRegs:$src2))]>; 607def FSUBD : F3_3<2, 0b110100, 0b001000110, 608 (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2), 609 "fsubd $src1, $src2, $dst", 610 [(set DFPRegs:$dst, (fsub DFPRegs:$src1, DFPRegs:$src2))]>; 611 612// Floating-point Multiply and Divide Instructions, p. 147 613def FMULS : F3_3<2, 0b110100, 0b001001001, 614 (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2), 615 "fmuls $src1, $src2, $dst", 616 [(set FPRegs:$dst, (fmul FPRegs:$src1, FPRegs:$src2))]>; 617def FMULD : F3_3<2, 0b110100, 0b001001010, 618 (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2), 619 "fmuld $src1, $src2, $dst", 620 [(set DFPRegs:$dst, (fmul DFPRegs:$src1, DFPRegs:$src2))]>; 621def FSMULD : F3_3<2, 0b110100, 0b001101001, 622 (outs DFPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2), 623 "fsmuld $src1, $src2, $dst", 624 [(set DFPRegs:$dst, (fmul (fextend FPRegs:$src1), 625 (fextend FPRegs:$src2)))]>; 626def FDIVS : F3_3<2, 0b110100, 0b001001101, 627 (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2), 628 "fdivs $src1, $src2, $dst", 629 [(set FPRegs:$dst, (fdiv FPRegs:$src1, FPRegs:$src2))]>; 630def FDIVD : F3_3<2, 0b110100, 0b001001110, 631 (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2), 632 "fdivd $src1, $src2, $dst", 633 [(set DFPRegs:$dst, (fdiv DFPRegs:$src1, DFPRegs:$src2))]>; 634 635// Floating-point Compare Instructions, p. 148 636// Note: the 2nd template arg is different for these guys. 637// Note 2: the result of a FCMP is not available until the 2nd cycle 638// after the instr is retired, but there is no interlock. This behavior 639// is modelled with a forced noop after the instruction. 640def FCMPS : F3_3<2, 0b110101, 0b001010001, 641 (outs), (ins FPRegs:$src1, FPRegs:$src2), 642 "fcmps $src1, $src2\n\tnop", 643 [(SPcmpfcc FPRegs:$src1, FPRegs:$src2)]>; 644def FCMPD : F3_3<2, 0b110101, 0b001010010, 645 (outs), (ins DFPRegs:$src1, DFPRegs:$src2), 646 "fcmpd $src1, $src2\n\tnop", 647 [(SPcmpfcc DFPRegs:$src1, DFPRegs:$src2)]>; 648 649 650//===----------------------------------------------------------------------===// 651// V9 Instructions 652//===----------------------------------------------------------------------===// 653 654// V9 Conditional Moves. 655let Predicates = [HasV9], isTwoAddress = 1 in { 656 // Move Integer Register on Condition (MOVcc) p. 194 of the V9 manual. 657 // FIXME: Add instruction encodings for the JIT some day. 658 def MOVICCrr 659 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, CCOp:$cc), 660 "mov$cc %icc, $F, $dst", 661 [(set IntRegs:$dst, 662 (SPselecticc IntRegs:$F, IntRegs:$T, imm:$cc))]>; 663 def MOVICCri 664 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, i32imm:$F, CCOp:$cc), 665 "mov$cc %icc, $F, $dst", 666 [(set IntRegs:$dst, 667 (SPselecticc simm11:$F, IntRegs:$T, imm:$cc))]>; 668 669 def MOVFCCrr 670 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, CCOp:$cc), 671 "mov$cc %fcc0, $F, $dst", 672 [(set IntRegs:$dst, 673 (SPselectfcc IntRegs:$F, IntRegs:$T, imm:$cc))]>; 674 def MOVFCCri 675 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, i32imm:$F, CCOp:$cc), 676 "mov$cc %fcc0, $F, $dst", 677 [(set IntRegs:$dst, 678 (SPselectfcc simm11:$F, IntRegs:$T, imm:$cc))]>; 679 680 def FMOVS_ICC 681 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, CCOp:$cc), 682 "fmovs$cc %icc, $F, $dst", 683 [(set FPRegs:$dst, 684 (SPselecticc FPRegs:$F, FPRegs:$T, imm:$cc))]>; 685 def FMOVD_ICC 686 : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, CCOp:$cc), 687 "fmovd$cc %icc, $F, $dst", 688 [(set DFPRegs:$dst, 689 (SPselecticc DFPRegs:$F, DFPRegs:$T, imm:$cc))]>; 690 def FMOVS_FCC 691 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, CCOp:$cc), 692 "fmovs$cc %fcc0, $F, $dst", 693 [(set FPRegs:$dst, 694 (SPselectfcc FPRegs:$F, FPRegs:$T, imm:$cc))]>; 695 def FMOVD_FCC 696 : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, CCOp:$cc), 697 "fmovd$cc %fcc0, $F, $dst", 698 [(set DFPRegs:$dst, 699 (SPselectfcc DFPRegs:$F, DFPRegs:$T, imm:$cc))]>; 700 701} 702 703// Floating-Point Move Instructions, p. 164 of the V9 manual. 704let Predicates = [HasV9] in { 705 def FMOVD : F3_3<2, 0b110100, 0b000000010, 706 (outs DFPRegs:$dst), (ins DFPRegs:$src), 707 "fmovd $src, $dst", []>; 708 def FNEGD : F3_3<2, 0b110100, 0b000000110, 709 (outs DFPRegs:$dst), (ins DFPRegs:$src), 710 "fnegd $src, $dst", 711 [(set DFPRegs:$dst, (fneg DFPRegs:$src))]>; 712 def FABSD : F3_3<2, 0b110100, 0b000001010, 713 (outs DFPRegs:$dst), (ins DFPRegs:$src), 714 "fabsd $src, $dst", 715 [(set DFPRegs:$dst, (fabs DFPRegs:$src))]>; 716} 717 718// POPCrr - This does a ctpop of a 64-bit register. As such, we have to clear 719// the top 32-bits before using it. To do this clearing, we use a SLLri X,0. 720def POPCrr : F3_1<2, 0b101110, 721 (outs IntRegs:$dst), (ins IntRegs:$src), 722 "popc $src, $dst", []>, Requires<[HasV9]>; 723def : Pat<(ctpop IntRegs:$src), 724 (POPCrr (SLLri IntRegs:$src, 0))>; 725 726//===----------------------------------------------------------------------===// 727// Non-Instruction Patterns 728//===----------------------------------------------------------------------===// 729 730// Small immediates. 731def : Pat<(i32 simm13:$val), 732 (ORri G0, imm:$val)>; 733// Arbitrary immediates. 734def : Pat<(i32 imm:$val), 735 (ORri (SETHIi (HI22 imm:$val)), (LO10 imm:$val))>; 736 737// subc 738def : Pat<(subc IntRegs:$b, IntRegs:$c), 739 (SUBCCrr IntRegs:$b, IntRegs:$c)>; 740def : Pat<(subc IntRegs:$b, simm13:$val), 741 (SUBCCri IntRegs:$b, imm:$val)>; 742 743// Global addresses, constant pool entries 744def : Pat<(SPhi tglobaladdr:$in), (SETHIi tglobaladdr:$in)>; 745def : Pat<(SPlo tglobaladdr:$in), (ORri G0, tglobaladdr:$in)>; 746def : Pat<(SPhi tconstpool:$in), (SETHIi tconstpool:$in)>; 747def : Pat<(SPlo tconstpool:$in), (ORri G0, tconstpool:$in)>; 748 749// Add reg, lo. This is used when taking the addr of a global/constpool entry. 750def : Pat<(add IntRegs:$r, (SPlo tglobaladdr:$in)), 751 (ADDri IntRegs:$r, tglobaladdr:$in)>; 752def : Pat<(add IntRegs:$r, (SPlo tconstpool:$in)), 753 (ADDri IntRegs:$r, tconstpool:$in)>; 754 755// Calls: 756def : Pat<(call tglobaladdr:$dst), 757 (CALL tglobaladdr:$dst)>; 758def : Pat<(call texternalsym:$dst), 759 (CALL texternalsym:$dst)>; 760 761def : Pat<(ret), (RETL)>; 762 763// Map integer extload's to zextloads. 764def : Pat<(i32 (extloadi1 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>; 765def : Pat<(i32 (extloadi1 ADDRri:$src)), (LDUBri ADDRri:$src)>; 766def : Pat<(i32 (extloadi8 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>; 767def : Pat<(i32 (extloadi8 ADDRri:$src)), (LDUBri ADDRri:$src)>; 768def : Pat<(i32 (extloadi16 ADDRrr:$src)), (LDUHrr ADDRrr:$src)>; 769def : Pat<(i32 (extloadi16 ADDRri:$src)), (LDUHri ADDRri:$src)>; 770 771// zextload bool -> zextload byte 772def : Pat<(i32 (zextloadi1 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>; 773def : Pat<(i32 (zextloadi1 ADDRri:$src)), (LDUBri ADDRri:$src)>; 774 775// truncstore bool -> truncstore byte. 776def : Pat<(truncstorei1 IntRegs:$src, ADDRrr:$addr), 777 (STBrr ADDRrr:$addr, IntRegs:$src)>; 778def : Pat<(truncstorei1 IntRegs:$src, ADDRri:$addr), 779 (STBri ADDRri:$addr, IntRegs:$src)>; 780