SparcInstrInfo.td revision cedc6f4b30c1fd5f7ad1df0b65b870e6f107e8ff
15821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)//===- SparcV8Instrs.td - Target Description for SparcV8 Target -----------===// 25821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// 35821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// The LLVM Compiler Infrastructure 45821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// 55821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// This file was developed by the LLVM research group and is distributed under 65821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// the University of Illinois Open Source License. See LICENSE.TXT for details. 75821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// 85821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)//===----------------------------------------------------------------------===// 95821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// 105821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// This file describes the SparcV8 instructions in TableGen format. 115821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// 125821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)//===----------------------------------------------------------------------===// 13868fa2fe829687343ffae624259930155e16dbd8Torne (Richard Coles) 145821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)//===----------------------------------------------------------------------===// 155821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// Instruction format superclass 16cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)//===----------------------------------------------------------------------===// 175821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 185821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)include "SparcV8InstrFormats.td" 195821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 201320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tucci//===----------------------------------------------------------------------===// 211320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tucci// Instruction Pattern Stuff 225821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)//===----------------------------------------------------------------------===// 235821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 242a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)def simm13 : PatLeaf<(imm), [{ 255821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) // simm13 predicate - True if the imm fits in a 13-bit sign extended field. 265821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) return (((int)N->getValue() << (32-13)) >> (32-13)) == (int)N->getValue(); 275821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)}]>; 285821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 295821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)def LO10 : SDNodeXForm<imm, [{ 30e5d81f57cb97b3b6b7fccc9c5610d21eb81db09dBen Murdoch return CurDAG->getTargetConstant((unsigned)N->getValue() & 1023, MVT::i32); 31e5d81f57cb97b3b6b7fccc9c5610d21eb81db09dBen Murdoch}]>; 32e5d81f57cb97b3b6b7fccc9c5610d21eb81db09dBen Murdoch 33e5d81f57cb97b3b6b7fccc9c5610d21eb81db09dBen Murdochdef HI22 : SDNodeXForm<imm, [{ 34e5d81f57cb97b3b6b7fccc9c5610d21eb81db09dBen Murdoch // Transformation function: shift the immediate value down into the low bits. 355821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) return CurDAG->getTargetConstant((unsigned)N->getValue() >> 10, MVT::i32); 365821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)}]>; 375821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 385821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)def SETHIimm : PatLeaf<(imm), [{ 395821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) return (((unsigned)N->getValue() >> 10) << 10) == (unsigned)N->getValue(); 402a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)}], HI22>; 412a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) 422a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)// Addressing modes. 432a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)def ADDRrr : ComplexPattern<i32, 2, "SelectADDRrr", []>; 445821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)def ADDRri : ComplexPattern<i32, 2, "SelectADDRri", []>; 45c5cede9ae108bb15f6b7a8aea21c7e1fefa2834cBen Murdoch 465821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// Address operands 475821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)def MEMrr : Operand<i32> { 485821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) let PrintMethod = "printMemOperand"; 495821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) let NumMIOperands = 2; 505821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) let MIOperandInfo = (ops IntRegs, IntRegs); 515821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)} 525821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)def MEMri : Operand<i32> { 535821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) let PrintMethod = "printMemOperand"; 545821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) let NumMIOperands = 2; 555821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) let MIOperandInfo = (ops IntRegs, i32imm); 565821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)} 57e5d81f57cb97b3b6b7fccc9c5610d21eb81db09dBen Murdoch 58e5d81f57cb97b3b6b7fccc9c5610d21eb81db09dBen Murdoch// Branch targets have OtherVT type. 592a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)def brtarget : Operand<OtherVT>; 602a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)def calltarget : Operand<i32>; 612a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) 625821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)def SDTV8cmpfcc : 635821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)SDTypeProfile<1, 2, [SDTCisVT<0, FlagVT>, SDTCisFP<1>, SDTCisSameAs<1, 2>]>; 645821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)def SDTV8brcc : 655821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)SDTypeProfile<0, 3, [SDTCisVT<0, OtherVT>, SDTCisVT<1, OtherVT>, 665821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) SDTCisVT<2, FlagVT>]>; 675821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)def SDTV8selectcc : 685821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, 695821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) SDTCisVT<3, i32>, SDTCisVT<4, FlagVT>]>; 705821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)def SDTV8FTOI : 715821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisFP<1>]>; 725821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)def SDTV8ITOF : 735821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f32>]>; 745821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 751320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tuccidef V8cmpicc : SDNode<"V8ISD::CMPICC", SDTIntBinOp, [SDNPOutFlag]>; 765821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)def V8cmpfcc : SDNode<"V8ISD::CMPFCC", SDTV8cmpfcc, [SDNPOutFlag]>; 775821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)def V8bricc : SDNode<"V8ISD::BRICC", SDTV8brcc, [SDNPHasChain]>; 785821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)def V8brfcc : SDNode<"V8ISD::BRFCC", SDTV8brcc, [SDNPHasChain]>; 795821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 805821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)def V8hi : SDNode<"V8ISD::Hi", SDTIntUnaryOp>; 815821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)def V8lo : SDNode<"V8ISD::Lo", SDTIntUnaryOp>; 82eb525c5499e34cc9c4b825d6d9e75bb07cc06aceBen Murdoch 835821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)def V8ftoi : SDNode<"V8ISD::FTOI", SDTV8FTOI>; 845821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)def V8itof : SDNode<"V8ISD::ITOF", SDTV8ITOF>; 855821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 865d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles)def V8selecticc : SDNode<"V8ISD::SELECT_ICC", SDTV8selectcc>; 875821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)def V8selectfcc : SDNode<"V8ISD::SELECT_FCC", SDTV8selectcc>; 88e5d81f57cb97b3b6b7fccc9c5610d21eb81db09dBen Murdoch 89e5d81f57cb97b3b6b7fccc9c5610d21eb81db09dBen Murdoch// These are target-independent nodes, but have target-specific formats. 90e5d81f57cb97b3b6b7fccc9c5610d21eb81db09dBen Murdochdef SDT_V8CallSeq : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>; 91e5d81f57cb97b3b6b7fccc9c5610d21eb81db09dBen Murdochdef callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_V8CallSeq, [SDNPHasChain]>; 92e5d81f57cb97b3b6b7fccc9c5610d21eb81db09dBen Murdochdef callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_V8CallSeq, [SDNPHasChain]>; 935821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 945821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)def SDT_V8Call : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>; 955821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)def call : SDNode<"ISD::CALL", SDT_V8Call, 965821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; 975821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 98d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles)def SDT_V8RetFlag : SDTypeProfile<0, 0, []>; 995821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)def retflag : SDNode<"V8ISD::RET_FLAG", SDT_V8RetFlag, 1005821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) [SDNPHasChain, SDNPOptInFlag]>; 1015821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 1025821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)//===----------------------------------------------------------------------===// 1035821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// Instructions 104d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles)//===----------------------------------------------------------------------===// 1055821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 1065821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// Pseudo instructions. 1075821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)class Pseudo<dag ops, string asmstr, list<dag> pattern> 1085821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) : InstV8<ops, asmstr, pattern>; 1095821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 1105821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)def ADJCALLSTACKDOWN : Pseudo<(ops i32imm:$amt), 1115821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) "!ADJCALLSTACKDOWN $amt", 1125821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) [(callseq_start imm:$amt)]>; 113a3f7b4e666c476898878fa745f637129375cd889Ben Murdochdef ADJCALLSTACKUP : Pseudo<(ops i32imm:$amt), 1145821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) "!ADJCALLSTACKUP $amt", 1155821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) [(callseq_end imm:$amt)]>; 1165821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)def IMPLICIT_DEF_Int : Pseudo<(ops IntRegs:$dst), 117e5d81f57cb97b3b6b7fccc9c5610d21eb81db09dBen Murdoch "!IMPLICIT_DEF $dst", 118e5d81f57cb97b3b6b7fccc9c5610d21eb81db09dBen Murdoch [(set IntRegs:$dst, (undef))]>; 119e5d81f57cb97b3b6b7fccc9c5610d21eb81db09dBen Murdochdef IMPLICIT_DEF_FP : Pseudo<(ops FPRegs:$dst), "!IMPLICIT_DEF $dst", 120e5d81f57cb97b3b6b7fccc9c5610d21eb81db09dBen Murdoch [(set FPRegs:$dst, (undef))]>; 121e5d81f57cb97b3b6b7fccc9c5610d21eb81db09dBen Murdochdef IMPLICIT_DEF_DFP : Pseudo<(ops DFPRegs:$dst), "!IMPLICIT_DEF $dst", 122e5d81f57cb97b3b6b7fccc9c5610d21eb81db09dBen Murdoch [(set DFPRegs:$dst, (undef))]>; 1235821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 1245821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// FpMOVD/FpNEGD/FpABSD - These are lowered to single-precision ops by the 1255d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles)// fpmover pass. 126d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles)def FpMOVD : Pseudo<(ops DFPRegs:$dst, DFPRegs:$src), 127d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) "!FpMOVD $src, $dst", []>; // pseudo 64-bit double move 128d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles)def FpNEGD : Pseudo<(ops DFPRegs:$dst, DFPRegs:$src), 129d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) "!FpNEGD $src, $dst", 130d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) [(set DFPRegs:$dst, (fneg DFPRegs:$src))]>; 131d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles)def FpABSD : Pseudo<(ops DFPRegs:$dst, DFPRegs:$src), 132d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) "!FpABSD $src, $dst", 133d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) [(set DFPRegs:$dst, (fabs DFPRegs:$src))]>; 1345821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 1355821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded by the 136e5d81f57cb97b3b6b7fccc9c5610d21eb81db09dBen Murdoch// scheduler into a branch sequence. This has to handle all permutations of 137e5d81f57cb97b3b6b7fccc9c5610d21eb81db09dBen Murdoch// selection between i32/f32/f64 on ICC and FCC. 138e5d81f57cb97b3b6b7fccc9c5610d21eb81db09dBen Murdochlet usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler. 139e5d81f57cb97b3b6b7fccc9c5610d21eb81db09dBen Murdoch def SELECT_CC_Int_ICC 140e5d81f57cb97b3b6b7fccc9c5610d21eb81db09dBen Murdoch : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F, i32imm:$Cond), 141e5d81f57cb97b3b6b7fccc9c5610d21eb81db09dBen Murdoch "; SELECT_CC_Int_ICC PSEUDO!", 142e5d81f57cb97b3b6b7fccc9c5610d21eb81db09dBen Murdoch [(set IntRegs:$dst, (V8selecticc IntRegs:$T, IntRegs:$F, 143e5d81f57cb97b3b6b7fccc9c5610d21eb81db09dBen Murdoch imm:$Cond, ICC))]>; 144e5d81f57cb97b3b6b7fccc9c5610d21eb81db09dBen Murdoch def SELECT_CC_Int_FCC 145e5d81f57cb97b3b6b7fccc9c5610d21eb81db09dBen Murdoch : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F, i32imm:$Cond), 146eb525c5499e34cc9c4b825d6d9e75bb07cc06aceBen Murdoch "; SELECT_CC_Int_FCC PSEUDO!", 1475821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) [(set IntRegs:$dst, (V8selectfcc IntRegs:$T, IntRegs:$F, 148d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) imm:$Cond, FCC))]>; 1495821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) def SELECT_CC_FP_ICC 1505821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) : Pseudo<(ops FPRegs:$dst, FPRegs:$T, FPRegs:$F, i32imm:$Cond), 1515821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) "; SELECT_CC_FP_ICC PSEUDO!", 1525821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) [(set FPRegs:$dst, (V8selecticc FPRegs:$T, FPRegs:$F, 153effb81e5f8246d0db0270817048dc992db66e9fbBen Murdoch imm:$Cond, ICC))]>; 154cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) def SELECT_CC_FP_FCC 1555d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) : Pseudo<(ops FPRegs:$dst, FPRegs:$T, FPRegs:$F, i32imm:$Cond), 156e5d81f57cb97b3b6b7fccc9c5610d21eb81db09dBen Murdoch "; SELECT_CC_FP_FCC PSEUDO!", 157e5d81f57cb97b3b6b7fccc9c5610d21eb81db09dBen Murdoch [(set FPRegs:$dst, (V8selectfcc FPRegs:$T, FPRegs:$F, 158e5d81f57cb97b3b6b7fccc9c5610d21eb81db09dBen Murdoch imm:$Cond, FCC))]>; 159e5d81f57cb97b3b6b7fccc9c5610d21eb81db09dBen Murdoch def SELECT_CC_DFP_ICC 160e5d81f57cb97b3b6b7fccc9c5610d21eb81db09dBen Murdoch : Pseudo<(ops DFPRegs:$dst, DFPRegs:$T, DFPRegs:$F, i32imm:$Cond), 161e5d81f57cb97b3b6b7fccc9c5610d21eb81db09dBen Murdoch "; SELECT_CC_DFP_ICC PSEUDO!", 1625821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) [(set DFPRegs:$dst, (V8selecticc DFPRegs:$T, DFPRegs:$F, 1635821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) imm:$Cond, ICC))]>; 164eb525c5499e34cc9c4b825d6d9e75bb07cc06aceBen Murdoch def SELECT_CC_DFP_FCC 165eb525c5499e34cc9c4b825d6d9e75bb07cc06aceBen Murdoch : Pseudo<(ops DFPRegs:$dst, DFPRegs:$T, DFPRegs:$F, i32imm:$Cond), 1665821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) "; SELECT_CC_DFP_FCC PSEUDO!", 167eb525c5499e34cc9c4b825d6d9e75bb07cc06aceBen Murdoch [(set DFPRegs:$dst, (V8selectfcc DFPRegs:$T, DFPRegs:$F, 1685821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) imm:$Cond, FCC))]>; 1695d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles)} 170eb525c5499e34cc9c4b825d6d9e75bb07cc06aceBen Murdoch 171eb525c5499e34cc9c4b825d6d9e75bb07cc06aceBen Murdoch// Section A.3 - Synthetic Instructions, p. 85 172c5cede9ae108bb15f6b7a8aea21c7e1fefa2834cBen Murdoch// special cases of JMPL: 1735821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)let isReturn = 1, isTerminator = 1, hasDelaySlot = 1, noResults = 1 in { 1745821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) let rd = O7.Num, rs1 = G0.Num, simm13 = 8 in 1755821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) def RETL: F3_2<2, 0b111000, (ops), "retl", [(retflag)]>; 1765821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)} 1775821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 178e5d81f57cb97b3b6b7fccc9c5610d21eb81db09dBen Murdoch// Section B.1 - Load Integer Instructions, p. 90 1795821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)def LDSBrr : F3_1<3, 0b001001, 1805821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) (ops IntRegs:$dst, MEMrr:$addr), 1815821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) "ldsb [$addr], $dst", 1825821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) [(set IntRegs:$dst, (sextload ADDRrr:$addr, i8))]>; 183e5d81f57cb97b3b6b7fccc9c5610d21eb81db09dBen Murdochdef LDSBri : F3_2<3, 0b001001, 184e5d81f57cb97b3b6b7fccc9c5610d21eb81db09dBen Murdoch (ops IntRegs:$dst, MEMri:$addr), 1855821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) "ldsb [$addr], $dst", 1865821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) [(set IntRegs:$dst, (sextload ADDRri:$addr, i8))]>; 1875821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)def LDSHrr : F3_1<3, 0b001010, 1885821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) (ops IntRegs:$dst, MEMrr:$addr), 1895821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) "ldsh [$addr], $dst", 1905821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) [(set IntRegs:$dst, (sextload ADDRrr:$addr, i16))]>; 1915821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)def LDSHri : F3_2<3, 0b001010, 1925821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) (ops IntRegs:$dst, MEMri:$addr), 1935821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) "ldsh [$addr], $dst", 1945821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) [(set IntRegs:$dst, (sextload ADDRri:$addr, i16))]>; 1955821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)def LDUBrr : F3_1<3, 0b000001, 1965821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) (ops IntRegs:$dst, MEMrr:$addr), 1975821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) "ldub [$addr], $dst", 1985821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) [(set IntRegs:$dst, (zextload ADDRrr:$addr, i8))]>; 1995821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)def LDUBri : F3_2<3, 0b000001, 2002a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) (ops IntRegs:$dst, MEMri:$addr), 2015821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) "ldub [$addr], $dst", 2025821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) [(set IntRegs:$dst, (zextload ADDRri:$addr, i8))]>; 2035821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)def LDUHrr : F3_1<3, 0b000010, 2045821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) (ops IntRegs:$dst, MEMrr:$addr), 2055821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) "lduh [$addr], $dst", 2065821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) [(set IntRegs:$dst, (zextload ADDRrr:$addr, i16))]>; 2075821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)def LDUHri : F3_2<3, 0b000010, 2085821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) (ops IntRegs:$dst, MEMri:$addr), 209 "lduh [$addr], $dst", 210 [(set IntRegs:$dst, (zextload ADDRri:$addr, i16))]>; 211def LDrr : F3_1<3, 0b000000, 212 (ops IntRegs:$dst, MEMrr:$addr), 213 "ld [$addr], $dst", 214 [(set IntRegs:$dst, (load ADDRrr:$addr))]>; 215def LDri : F3_2<3, 0b000000, 216 (ops IntRegs:$dst, MEMri:$addr), 217 "ld [$addr], $dst", 218 [(set IntRegs:$dst, (load ADDRri:$addr))]>; 219 220// Section B.2 - Load Floating-point Instructions, p. 92 221def LDFrr : F3_1<3, 0b100000, 222 (ops FPRegs:$dst, MEMrr:$addr), 223 "ld [$addr], $dst", 224 [(set FPRegs:$dst, (load ADDRrr:$addr))]>; 225def LDFri : F3_2<3, 0b100000, 226 (ops FPRegs:$dst, MEMri:$addr), 227 "ld [$addr], $dst", 228 [(set FPRegs:$dst, (load ADDRri:$addr))]>; 229def LDDFrr : F3_1<3, 0b100011, 230 (ops DFPRegs:$dst, MEMrr:$addr), 231 "ldd [$addr], $dst", 232 [(set DFPRegs:$dst, (load ADDRrr:$addr))]>; 233def LDDFri : F3_2<3, 0b100011, 234 (ops DFPRegs:$dst, MEMri:$addr), 235 "ldd [$addr], $dst", 236 [(set DFPRegs:$dst, (load ADDRri:$addr))]>; 237 238// Section B.4 - Store Integer Instructions, p. 95 239def STBrr : F3_1<3, 0b000101, 240 (ops MEMrr:$addr, IntRegs:$src), 241 "stb $src, [$addr]", 242 [(truncstore IntRegs:$src, ADDRrr:$addr, i8)]>; 243def STBri : F3_2<3, 0b000101, 244 (ops MEMri:$addr, IntRegs:$src), 245 "stb $src, [$addr]", 246 [(truncstore IntRegs:$src, ADDRri:$addr, i8)]>; 247def STHrr : F3_1<3, 0b000110, 248 (ops MEMrr:$addr, IntRegs:$src), 249 "sth $src, [$addr]", 250 [(truncstore IntRegs:$src, ADDRrr:$addr, i16)]>; 251def STHri : F3_2<3, 0b000110, 252 (ops MEMri:$addr, IntRegs:$src), 253 "sth $src, [$addr]", 254 [(truncstore IntRegs:$src, ADDRri:$addr, i16)]>; 255def STrr : F3_1<3, 0b000100, 256 (ops MEMrr:$addr, IntRegs:$src), 257 "st $src, [$addr]", 258 [(store IntRegs:$src, ADDRrr:$addr)]>; 259def STri : F3_2<3, 0b000100, 260 (ops MEMri:$addr, IntRegs:$src), 261 "st $src, [$addr]", 262 [(store IntRegs:$src, ADDRri:$addr)]>; 263 264// Section B.5 - Store Floating-point Instructions, p. 97 265def STFrr : F3_1<3, 0b100100, 266 (ops MEMrr:$addr, FPRegs:$src), 267 "st $src, [$addr]", 268 [(store FPRegs:$src, ADDRrr:$addr)]>; 269def STFri : F3_2<3, 0b100100, 270 (ops MEMri:$addr, FPRegs:$src), 271 "st $src, [$addr]", 272 [(store FPRegs:$src, ADDRri:$addr)]>; 273def STDFrr : F3_1<3, 0b100111, 274 (ops MEMrr:$addr, DFPRegs:$src), 275 "std $src, [$addr]", 276 [(store DFPRegs:$src, ADDRrr:$addr)]>; 277def STDFri : F3_2<3, 0b100111, 278 (ops MEMri:$addr, DFPRegs:$src), 279 "std $src, [$addr]", 280 [(store DFPRegs:$src, ADDRri:$addr)]>; 281 282// Section B.9 - SETHI Instruction, p. 104 283def SETHIi: F2_1<0b100, 284 (ops IntRegs:$dst, i32imm:$src), 285 "sethi $src, $dst", 286 [(set IntRegs:$dst, SETHIimm:$src)]>; 287 288// Section B.10 - NOP Instruction, p. 105 289// (It's a special case of SETHI) 290let rd = 0, imm22 = 0 in 291 def NOP : F2_1<0b100, (ops), "nop", []>; 292 293// Section B.11 - Logical Instructions, p. 106 294def ANDrr : F3_1<2, 0b000001, 295 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 296 "and $b, $c, $dst", 297 [(set IntRegs:$dst, (and IntRegs:$b, IntRegs:$c))]>; 298def ANDri : F3_2<2, 0b000001, 299 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 300 "and $b, $c, $dst", 301 [(set IntRegs:$dst, (and IntRegs:$b, simm13:$c))]>; 302def ANDNrr : F3_1<2, 0b000101, 303 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 304 "andn $b, $c, $dst", 305 [(set IntRegs:$dst, (and IntRegs:$b, (not IntRegs:$c)))]>; 306def ANDNri : F3_2<2, 0b000101, 307 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 308 "andn $b, $c, $dst", []>; 309def ORrr : F3_1<2, 0b000010, 310 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 311 "or $b, $c, $dst", 312 [(set IntRegs:$dst, (or IntRegs:$b, IntRegs:$c))]>; 313def ORri : F3_2<2, 0b000010, 314 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 315 "or $b, $c, $dst", 316 [(set IntRegs:$dst, (or IntRegs:$b, simm13:$c))]>; 317def ORNrr : F3_1<2, 0b000110, 318 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 319 "orn $b, $c, $dst", 320 [(set IntRegs:$dst, (or IntRegs:$b, (not IntRegs:$c)))]>; 321def ORNri : F3_2<2, 0b000110, 322 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 323 "orn $b, $c, $dst", []>; 324def XORrr : F3_1<2, 0b000011, 325 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 326 "xor $b, $c, $dst", 327 [(set IntRegs:$dst, (xor IntRegs:$b, IntRegs:$c))]>; 328def XORri : F3_2<2, 0b000011, 329 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 330 "xor $b, $c, $dst", 331 [(set IntRegs:$dst, (xor IntRegs:$b, simm13:$c))]>; 332def XNORrr : F3_1<2, 0b000111, 333 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 334 "xnor $b, $c, $dst", 335 [(set IntRegs:$dst, (not (xor IntRegs:$b, IntRegs:$c)))]>; 336def XNORri : F3_2<2, 0b000111, 337 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 338 "xnor $b, $c, $dst", []>; 339 340// Section B.12 - Shift Instructions, p. 107 341def SLLrr : F3_1<2, 0b100101, 342 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 343 "sll $b, $c, $dst", 344 [(set IntRegs:$dst, (shl IntRegs:$b, IntRegs:$c))]>; 345def SLLri : F3_2<2, 0b100101, 346 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 347 "sll $b, $c, $dst", 348 [(set IntRegs:$dst, (shl IntRegs:$b, simm13:$c))]>; 349def SRLrr : F3_1<2, 0b100110, 350 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 351 "srl $b, $c, $dst", 352 [(set IntRegs:$dst, (srl IntRegs:$b, IntRegs:$c))]>; 353def SRLri : F3_2<2, 0b100110, 354 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 355 "srl $b, $c, $dst", 356 [(set IntRegs:$dst, (srl IntRegs:$b, simm13:$c))]>; 357def SRArr : F3_1<2, 0b100111, 358 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 359 "sra $b, $c, $dst", 360 [(set IntRegs:$dst, (sra IntRegs:$b, IntRegs:$c))]>; 361def SRAri : F3_2<2, 0b100111, 362 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 363 "sra $b, $c, $dst", 364 [(set IntRegs:$dst, (sra IntRegs:$b, simm13:$c))]>; 365 366// Section B.13 - Add Instructions, p. 108 367def ADDrr : F3_1<2, 0b000000, 368 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 369 "add $b, $c, $dst", 370 [(set IntRegs:$dst, (add IntRegs:$b, IntRegs:$c))]>; 371def ADDri : F3_2<2, 0b000000, 372 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 373 "add $b, $c, $dst", 374 [(set IntRegs:$dst, (add IntRegs:$b, simm13:$c))]>; 375def ADDCCrr : F3_1<2, 0b010000, 376 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 377 "addcc $b, $c, $dst", []>; 378def ADDCCri : F3_2<2, 0b010000, 379 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 380 "addcc $b, $c, $dst", []>; 381def ADDXrr : F3_1<2, 0b001000, 382 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 383 "addx $b, $c, $dst", []>; 384def ADDXri : F3_2<2, 0b001000, 385 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 386 "addx $b, $c, $dst", []>; 387 388// Section B.15 - Subtract Instructions, p. 110 389def SUBrr : F3_1<2, 0b000100, 390 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 391 "sub $b, $c, $dst", 392 [(set IntRegs:$dst, (sub IntRegs:$b, IntRegs:$c))]>; 393def SUBri : F3_2<2, 0b000100, 394 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 395 "sub $b, $c, $dst", 396 [(set IntRegs:$dst, (sub IntRegs:$b, simm13:$c))]>; 397def SUBXrr : F3_1<2, 0b001100, 398 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 399 "subx $b, $c, $dst", []>; 400def SUBXri : F3_2<2, 0b001100, 401 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 402 "subx $b, $c, $dst", []>; 403def SUBCCrr : F3_1<2, 0b010100, 404 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 405 "subcc $b, $c, $dst", 406 [(set IntRegs:$dst, (V8cmpicc IntRegs:$b, IntRegs:$c))]>; 407def SUBCCri : F3_2<2, 0b010100, 408 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 409 "subcc $b, $c, $dst", 410 [(set IntRegs:$dst, (V8cmpicc IntRegs:$b, simm13:$c))]>; 411def SUBXCCrr: F3_1<2, 0b011100, 412 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 413 "subxcc $b, $c, $dst", []>; 414 415// Section B.18 - Multiply Instructions, p. 113 416def UMULrr : F3_1<2, 0b001010, 417 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 418 "umul $b, $c, $dst", []>; 419def UMULri : F3_2<2, 0b001010, 420 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 421 "umul $b, $c, $dst", []>; 422def SMULrr : F3_1<2, 0b001011, 423 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 424 "smul $b, $c, $dst", 425 [(set IntRegs:$dst, (mul IntRegs:$b, IntRegs:$c))]>; 426def SMULri : F3_2<2, 0b001011, 427 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 428 "smul $b, $c, $dst", 429 [(set IntRegs:$dst, (mul IntRegs:$b, simm13:$c))]>; 430 431// Section B.19 - Divide Instructions, p. 115 432def UDIVrr : F3_1<2, 0b001110, 433 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 434 "udiv $b, $c, $dst", []>; 435def UDIVri : F3_2<2, 0b001110, 436 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 437 "udiv $b, $c, $dst", []>; 438def SDIVrr : F3_1<2, 0b001111, 439 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 440 "sdiv $b, $c, $dst", []>; 441def SDIVri : F3_2<2, 0b001111, 442 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 443 "sdiv $b, $c, $dst", []>; 444 445// Section B.20 - SAVE and RESTORE, p. 117 446def SAVErr : F3_1<2, 0b111100, 447 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 448 "save $b, $c, $dst", []>; 449def SAVEri : F3_2<2, 0b111100, 450 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 451 "save $b, $c, $dst", []>; 452def RESTORErr : F3_1<2, 0b111101, 453 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 454 "restore $b, $c, $dst", []>; 455def RESTOREri : F3_2<2, 0b111101, 456 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 457 "restore $b, $c, $dst", []>; 458 459// Section B.21 - Branch on Integer Condition Codes Instructions, p. 119 460 461// conditional branch class: 462class BranchV8<bits<4> cc, dag ops, string asmstr, list<dag> pattern> 463 : F2_2<cc, 0b010, ops, asmstr, pattern> { 464 let isBranch = 1; 465 let isTerminator = 1; 466 let hasDelaySlot = 1; 467 let noResults = 1; 468} 469 470let isBarrier = 1 in 471 def BA : BranchV8<0b1000, (ops brtarget:$dst), 472 "ba $dst", 473 [(br bb:$dst)]>; 474def BNE : BranchV8<0b1001, (ops brtarget:$dst), 475 "bne $dst", 476 [(V8bricc bb:$dst, SETNE, ICC)]>; 477def BE : BranchV8<0b0001, (ops brtarget:$dst), 478 "be $dst", 479 [(V8bricc bb:$dst, SETEQ, ICC)]>; 480def BG : BranchV8<0b1010, (ops brtarget:$dst), 481 "bg $dst", 482 [(V8bricc bb:$dst, SETGT, ICC)]>; 483def BLE : BranchV8<0b0010, (ops brtarget:$dst), 484 "ble $dst", 485 [(V8bricc bb:$dst, SETLE, ICC)]>; 486def BGE : BranchV8<0b1011, (ops brtarget:$dst), 487 "bge $dst", 488 [(V8bricc bb:$dst, SETGE, ICC)]>; 489def BL : BranchV8<0b0011, (ops brtarget:$dst), 490 "bl $dst", 491 [(V8bricc bb:$dst, SETLT, ICC)]>; 492def BGU : BranchV8<0b1100, (ops brtarget:$dst), 493 "bgu $dst", 494 [(V8bricc bb:$dst, SETUGT, ICC)]>; 495def BLEU : BranchV8<0b0100, (ops brtarget:$dst), 496 "bleu $dst", 497 [(V8bricc bb:$dst, SETULE, ICC)]>; 498def BCC : BranchV8<0b1101, (ops brtarget:$dst), 499 "bcc $dst", 500 [(V8bricc bb:$dst, SETUGE, ICC)]>; 501def BCS : BranchV8<0b0101, (ops brtarget:$dst), 502 "bcs $dst", 503 [(V8bricc bb:$dst, SETULT, ICC)]>; 504 505// Section B.22 - Branch on Floating-point Condition Codes Instructions, p. 121 506 507// floating-point conditional branch class: 508class FPBranchV8<bits<4> cc, dag ops, string asmstr, list<dag> pattern> 509 : F2_2<cc, 0b110, ops, asmstr, pattern> { 510 let isBranch = 1; 511 let isTerminator = 1; 512 let hasDelaySlot = 1; 513 let noResults = 1; 514} 515 516def FBU : FPBranchV8<0b0111, (ops brtarget:$dst), 517 "fbu $dst", 518 [(V8brfcc bb:$dst, SETUO, FCC)]>; 519def FBG : FPBranchV8<0b0110, (ops brtarget:$dst), 520 "fbg $dst", 521 [(V8brfcc bb:$dst, SETGT, FCC)]>; 522def FBUG : FPBranchV8<0b0101, (ops brtarget:$dst), 523 "fbug $dst", 524 [(V8brfcc bb:$dst, SETUGT, FCC)]>; 525def FBL : FPBranchV8<0b0100, (ops brtarget:$dst), 526 "fbl $dst", 527 [(V8brfcc bb:$dst, SETLT, FCC)]>; 528def FBUL : FPBranchV8<0b0011, (ops brtarget:$dst), 529 "fbul $dst", 530 [(V8brfcc bb:$dst, SETULT, FCC)]>; 531def FBLG : FPBranchV8<0b0010, (ops brtarget:$dst), 532 "fblg $dst", 533 [(V8brfcc bb:$dst, SETONE, FCC)]>; 534def FBNE : FPBranchV8<0b0001, (ops brtarget:$dst), 535 "fbne $dst", 536 [(V8brfcc bb:$dst, SETNE, FCC)]>; 537def FBE : FPBranchV8<0b1001, (ops brtarget:$dst), 538 "fbe $dst", 539 [(V8brfcc bb:$dst, SETEQ, FCC)]>; 540def FBUE : FPBranchV8<0b1010, (ops brtarget:$dst), 541 "fbue $dst", 542 [(V8brfcc bb:$dst, SETUEQ, FCC)]>; 543def FBGE : FPBranchV8<0b1011, (ops brtarget:$dst), 544 "fbge $dst", 545 [(V8brfcc bb:$dst, SETGE, FCC)]>; 546def FBUGE: FPBranchV8<0b1100, (ops brtarget:$dst), 547 "fbuge $dst", 548 [(V8brfcc bb:$dst, SETUGE, FCC)]>; 549def FBLE : FPBranchV8<0b1101, (ops brtarget:$dst), 550 "fble $dst", 551 [(V8brfcc bb:$dst, SETLE, FCC)]>; 552def FBULE: FPBranchV8<0b1110, (ops brtarget:$dst), 553 "fbule $dst", 554 [(V8brfcc bb:$dst, SETULE, FCC)]>; 555def FBO : FPBranchV8<0b1111, (ops brtarget:$dst), 556 "fbo $dst", 557 [(V8brfcc bb:$dst, SETO, FCC)]>; 558 559 560 561// Section B.24 - Call and Link Instruction, p. 125 562// This is the only Format 1 instruction 563let Uses = [O0, O1, O2, O3, O4, O5], 564 hasDelaySlot = 1, isCall = 1, noResults = 1, 565 Defs = [O0, O1, O2, O3, O4, O5, O7, G1, G2, G3, G4, G5, G6, G7, 566 D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15] in { 567 def CALL : InstV8<(ops calltarget:$dst), 568 "call $dst", []> { 569 bits<30> disp; 570 let op = 1; 571 let Inst{29-0} = disp; 572 } 573 574 // indirect calls 575 def JMPLrr : F3_1<2, 0b111000, 576 (ops MEMrr:$ptr), 577 "call $ptr", 578 [(call ADDRrr:$ptr)]>; 579 def JMPLri : F3_2<2, 0b111000, 580 (ops MEMri:$ptr), 581 "call $ptr", 582 [(call ADDRri:$ptr)]>; 583} 584 585// Section B.28 - Read State Register Instructions 586def RDY : F3_1<2, 0b101000, 587 (ops IntRegs:$dst), 588 "rd %y, $dst", []>; 589 590// Section B.29 - Write State Register Instructions 591def WRYrr : F3_1<2, 0b110000, 592 (ops IntRegs:$b, IntRegs:$c), 593 "wr $b, $c, %y", []>; 594def WRYri : F3_2<2, 0b110000, 595 (ops IntRegs:$b, i32imm:$c), 596 "wr $b, $c, %y", []>; 597 598// Convert Integer to Floating-point Instructions, p. 141 599def FITOS : F3_3<2, 0b110100, 0b011000100, 600 (ops FPRegs:$dst, FPRegs:$src), 601 "fitos $src, $dst", 602 [(set FPRegs:$dst, (V8itof FPRegs:$src))]>; 603def FITOD : F3_3<2, 0b110100, 0b011001000, 604 (ops DFPRegs:$dst, FPRegs:$src), 605 "fitod $src, $dst", 606 [(set DFPRegs:$dst, (V8itof FPRegs:$src))]>; 607 608// Convert Floating-point to Integer Instructions, p. 142 609def FSTOI : F3_3<2, 0b110100, 0b011010001, 610 (ops FPRegs:$dst, FPRegs:$src), 611 "fstoi $src, $dst", 612 [(set FPRegs:$dst, (V8ftoi FPRegs:$src))]>; 613def FDTOI : F3_3<2, 0b110100, 0b011010010, 614 (ops FPRegs:$dst, DFPRegs:$src), 615 "fdtoi $src, $dst", 616 [(set FPRegs:$dst, (V8ftoi DFPRegs:$src))]>; 617 618// Convert between Floating-point Formats Instructions, p. 143 619def FSTOD : F3_3<2, 0b110100, 0b011001001, 620 (ops DFPRegs:$dst, FPRegs:$src), 621 "fstod $src, $dst", 622 [(set DFPRegs:$dst, (fextend FPRegs:$src))]>; 623def FDTOS : F3_3<2, 0b110100, 0b011000110, 624 (ops FPRegs:$dst, DFPRegs:$src), 625 "fdtos $src, $dst", 626 [(set FPRegs:$dst, (fround DFPRegs:$src))]>; 627 628// Floating-point Move Instructions, p. 144 629def FMOVS : F3_3<2, 0b110100, 0b000000001, 630 (ops FPRegs:$dst, FPRegs:$src), 631 "fmovs $src, $dst", []>; 632def FNEGS : F3_3<2, 0b110100, 0b000000101, 633 (ops FPRegs:$dst, FPRegs:$src), 634 "fnegs $src, $dst", 635 [(set FPRegs:$dst, (fneg FPRegs:$src))]>; 636def FABSS : F3_3<2, 0b110100, 0b000001001, 637 (ops FPRegs:$dst, FPRegs:$src), 638 "fabss $src, $dst", 639 [(set FPRegs:$dst, (fabs FPRegs:$src))]>; 640 641 642// Floating-point Square Root Instructions, p.145 643def FSQRTS : F3_3<2, 0b110100, 0b000101001, 644 (ops FPRegs:$dst, FPRegs:$src), 645 "fsqrts $src, $dst", 646 [(set FPRegs:$dst, (fsqrt FPRegs:$src))]>; 647def FSQRTD : F3_3<2, 0b110100, 0b000101010, 648 (ops DFPRegs:$dst, DFPRegs:$src), 649 "fsqrtd $src, $dst", 650 [(set DFPRegs:$dst, (fsqrt DFPRegs:$src))]>; 651 652 653 654// Floating-point Add and Subtract Instructions, p. 146 655def FADDS : F3_3<2, 0b110100, 0b001000001, 656 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2), 657 "fadds $src1, $src2, $dst", 658 [(set FPRegs:$dst, (fadd FPRegs:$src1, FPRegs:$src2))]>; 659def FADDD : F3_3<2, 0b110100, 0b001000010, 660 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2), 661 "faddd $src1, $src2, $dst", 662 [(set DFPRegs:$dst, (fadd DFPRegs:$src1, DFPRegs:$src2))]>; 663def FSUBS : F3_3<2, 0b110100, 0b001000101, 664 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2), 665 "fsubs $src1, $src2, $dst", 666 [(set FPRegs:$dst, (fsub FPRegs:$src1, FPRegs:$src2))]>; 667def FSUBD : F3_3<2, 0b110100, 0b001000110, 668 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2), 669 "fsubd $src1, $src2, $dst", 670 [(set DFPRegs:$dst, (fsub DFPRegs:$src1, DFPRegs:$src2))]>; 671 672// Floating-point Multiply and Divide Instructions, p. 147 673def FMULS : F3_3<2, 0b110100, 0b001001001, 674 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2), 675 "fmuls $src1, $src2, $dst", 676 [(set FPRegs:$dst, (fmul FPRegs:$src1, FPRegs:$src2))]>; 677def FMULD : F3_3<2, 0b110100, 0b001001010, 678 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2), 679 "fmuld $src1, $src2, $dst", 680 [(set DFPRegs:$dst, (fmul DFPRegs:$src1, DFPRegs:$src2))]>; 681def FSMULD : F3_3<2, 0b110100, 0b001101001, 682 (ops DFPRegs:$dst, FPRegs:$src1, FPRegs:$src2), 683 "fsmuld $src1, $src2, $dst", 684 [(set DFPRegs:$dst, (fmul (fextend FPRegs:$src1), 685 (fextend FPRegs:$src2)))]>; 686def FDIVS : F3_3<2, 0b110100, 0b001001101, 687 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2), 688 "fdivs $src1, $src2, $dst", 689 [(set FPRegs:$dst, (fdiv FPRegs:$src1, FPRegs:$src2))]>; 690def FDIVD : F3_3<2, 0b110100, 0b001001110, 691 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2), 692 "fdivd $src1, $src2, $dst", 693 [(set DFPRegs:$dst, (fdiv DFPRegs:$src1, DFPRegs:$src2))]>; 694 695// Floating-point Compare Instructions, p. 148 696// Note: the 2nd template arg is different for these guys. 697// Note 2: the result of a FCMP is not available until the 2nd cycle 698// after the instr is retired, but there is no interlock. This behavior 699// is modelled with a forced noop after the instruction. 700def FCMPS : F3_3<2, 0b110101, 0b001010001, 701 (ops FPRegs:$src1, FPRegs:$src2), 702 "fcmps $src1, $src2\n\tnop", 703 [(set FCC, (V8cmpfcc FPRegs:$src1, FPRegs:$src2))]>; 704def FCMPD : F3_3<2, 0b110101, 0b001010010, 705 (ops DFPRegs:$src1, DFPRegs:$src2), 706 "fcmpd $src1, $src2\n\tnop", 707 [(set FCC, (V8cmpfcc DFPRegs:$src1, DFPRegs:$src2))]>; 708 709//===----------------------------------------------------------------------===// 710// Non-Instruction Patterns 711//===----------------------------------------------------------------------===// 712 713// Small immediates. 714def : Pat<(i32 simm13:$val), 715 (ORri G0, imm:$val)>; 716// Arbitrary immediates. 717def : Pat<(i32 imm:$val), 718 (ORri (SETHIi (HI22 imm:$val)), (LO10 imm:$val))>; 719 720// Global addresses, constant pool entries 721def : Pat<(V8hi tglobaladdr:$in), (SETHIi tglobaladdr:$in)>; 722def : Pat<(V8lo tglobaladdr:$in), (ORri G0, tglobaladdr:$in)>; 723def : Pat<(V8hi tconstpool:$in), (SETHIi tconstpool:$in)>; 724def : Pat<(V8lo tconstpool:$in), (ORri G0, tconstpool:$in)>; 725 726// Add reg, lo. This is used when taking the addr of a global/constpool entry. 727def : Pat<(add IntRegs:$r, (V8lo tglobaladdr:$in)), 728 (ADDri IntRegs:$r, tglobaladdr:$in)>; 729def : Pat<(add IntRegs:$r, (V8lo tconstpool:$in)), 730 (ADDri IntRegs:$r, tconstpool:$in)>; 731 732 733// Calls: 734def : Pat<(call tglobaladdr:$dst), 735 (CALL tglobaladdr:$dst)>; 736def : Pat<(call externalsym:$dst), 737 (CALL externalsym:$dst)>; 738 739def : Pat<(ret), (RETL)>; 740 741// Map integer extload's to zextloads. 742def : Pat<(i32 (extload ADDRrr:$src, i1)), (LDUBrr ADDRrr:$src)>; 743def : Pat<(i32 (extload ADDRri:$src, i1)), (LDUBri ADDRri:$src)>; 744def : Pat<(i32 (extload ADDRrr:$src, i8)), (LDUBrr ADDRrr:$src)>; 745def : Pat<(i32 (extload ADDRri:$src, i8)), (LDUBri ADDRri:$src)>; 746def : Pat<(i32 (extload ADDRrr:$src, i16)), (LDUHrr ADDRrr:$src)>; 747def : Pat<(i32 (extload ADDRri:$src, i16)), (LDUHri ADDRri:$src)>; 748 749// zextload bool -> zextload byte 750def : Pat<(i32 (zextload ADDRrr:$src, i1)), (LDUBrr ADDRrr:$src)>; 751def : Pat<(i32 (zextload ADDRri:$src, i1)), (LDUBri ADDRri:$src)>; 752 753// truncstore bool -> truncstore byte. 754def : Pat<(truncstore IntRegs:$src, ADDRrr:$addr, i1), 755 (STBrr ADDRrr:$addr, IntRegs:$src)>; 756def : Pat<(truncstore IntRegs:$src, ADDRri:$addr, i1), 757 (STBri ADDRri:$addr, IntRegs:$src)>; 758