SparcInstrInfo.td revision d7bf501cc732f8ddcc30a6bd68d2fdbfe0f2145f
1//===- SparcV8Instrs.td - Target Description for SparcV8 Target -----------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the SparcV8 instructions in TableGen format. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// Instruction format superclass 16//===----------------------------------------------------------------------===// 17 18class InstV8 : Instruction { // SparcV8 instruction baseline 19 field bits<32> Inst; 20 21 let Namespace = "V8"; 22 23 bits<2> op; 24 let Inst{31-30} = op; // Top two bits are the 'op' field 25 26 // Bit attributes specific to SparcV8 instructions 27 bit isPasi = 0; // Does this instruction affect an alternate addr space? 28 bit isPrivileged = 0; // Is this a privileged instruction? 29} 30 31include "SparcV8InstrFormats.td" 32 33//===----------------------------------------------------------------------===// 34// Instructions 35//===----------------------------------------------------------------------===// 36 37// Pseudo instructions. 38class PseudoInstV8<string nm> : InstV8 { 39 let Name = nm; 40} 41def PHI : PseudoInstV8<"PHI">; 42def ADJCALLSTACKDOWN : PseudoInstV8<"ADJCALLSTACKDOWN">; 43def ADJCALLSTACKUP : PseudoInstV8<"ADJCALLSTACKUP">; 44def IMPLICIT_USE : PseudoInstV8<"IMPLICIT_USE">; 45def IMPLICIT_DEF : PseudoInstV8<"IMPLICIT_DEF">; 46def FpMOVD : PseudoInstV8<"FpMOVD">; // pseudo 64-bit double move 47 48// Section A.3 - Synthetic Instructions, p. 85 49// special cases of JMPL: 50let isReturn = 1, isTerminator = 1, hasDelaySlot = 1, simm13 = 8 in 51 def RET : F3_2<2, 0b111000, "ret">; 52let isReturn = 1, isTerminator = 1, hasDelaySlot = 1, simm13 = 8 in 53 def RETL: F3_2<2, 0b111000, "retl">; 54// CMP is a special case of SUBCC where destination is ignored, by setting it to 55// %g0 (hardwired zero). 56// FIXME: should keep track of the fact that it defs the integer condition codes 57let rd = 0 in 58 def CMPri: F3_2<2, 0b010100, "cmp">; 59 60// Section B.1 - Load Integer Instructions, p. 90 61def LDSB: F3_2<3, 0b001001, "ldsb">; 62def LDSH: F3_2<3, 0b001010, "ldsh">; 63def LDUB: F3_2<3, 0b000001, "ldub">; 64def LDUH: F3_2<3, 0b000010, "lduh">; 65def LD : F3_2<3, 0b000000, "ld">; 66def LDD : F3_2<3, 0b000011, "ldd">; 67 68// Section B.2 - Load Floating-point Instructions, p. 92 69def LDFrr : F3_1<3, 0b100000, "ld">; 70def LDFri : F3_2<3, 0b100000, "ld">; 71def LDDFrr : F3_1<3, 0b100011, "ldd">; 72def LDDFri : F3_2<3, 0b100011, "ldd">; 73def LDFSRrr: F3_1<3, 0b100001, "ld">; 74def LDFSRri: F3_2<3, 0b100001, "ld">; 75 76// Section B.4 - Store Integer Instructions, p. 95 77def STB : F3_2<3, 0b000101, "stb">; 78def STH : F3_2<3, 0b000110, "sth">; 79def ST : F3_2<3, 0b000100, "st">; 80def STD : F3_2<3, 0b000111, "std">; 81 82// Section B.5 - Store Floating-point Instructions, p. 97 83def STFrr : F3_1<3, 0b100100, "st">; 84def STFri : F3_2<3, 0b100100, "st">; 85def STDFrr : F3_1<3, 0b100111, "std">; 86def STDFri : F3_2<3, 0b100111, "std">; 87def STFSRrr : F3_1<3, 0b100101, "st">; 88def STFSRri : F3_2<3, 0b100101, "st">; 89def STDFQrr : F3_1<3, 0b100110, "std">; 90def STDFQri : F3_2<3, 0b100110, "std">; 91 92// Section B.9 - SETHI Instruction, p. 104 93def SETHIi: F2_1<0b100, "sethi">; 94 95// Section B.10 - NOP Instruction, p. 105 96// (It's a special case of SETHI) 97let rd = 0, imm = 0 in 98 def NOP : F2_1<0b100, "nop">; 99 100// Section B.11 - Logical Instructions, p. 106 101def ANDrr : F3_1<2, 0b000001, "and">; 102def ANDri : F3_2<2, 0b000001, "and">; 103def ORrr : F3_1<2, 0b000010, "or">; 104def ORri : F3_2<2, 0b000010, "or">; 105def XORrr : F3_1<2, 0b000011, "xor">; 106def XORri : F3_2<2, 0b000011, "xor">; 107 108// Section B.12 - Shift Instructions, p. 107 109def SLLrr : F3_1<2, 0b100101, "sll">; 110def SLLri : F3_2<2, 0b100101, "sll">; 111def SRLrr : F3_1<2, 0b100110, "srl">; 112def SRLri : F3_2<2, 0b100110, "srl">; 113def SRArr : F3_1<2, 0b100111, "sra">; 114def SRAri : F3_2<2, 0b100111, "sra">; 115 116// Section B.13 - Add Instructions, p. 108 117def ADDrr : F3_1<2, 0b000000, "add">; 118def ADDri : F3_2<2, 0b000000, "add">; 119 120// Section B.15 - Subtract Instructions, p. 110 121def SUBrr : F3_1<2, 0b000100, "sub">; 122def SUBCCrr : F3_1<2, 0b010100, "subcc">; 123def SUBCCri : F3_2<2, 0b010100, "subcc">; 124 125// Section B.18 - Multiply Instructions, p. 113 126def UMULrr : F3_1<2, 0b001010, "umul">; 127def SMULrr : F3_1<2, 0b001011, "smul">; 128 129// Section B.19 - Divide Instructions, p. 115 130def UDIVrr : F3_1<2, 0b001110, "udiv">; 131def UDIVri : F3_2<2, 0b001110, "udiv">; 132def SDIVrr : F3_1<2, 0b001111, "sdiv">; 133def SDIVri : F3_2<2, 0b001111, "sdiv">; 134def UDIVCCrr : F3_1<2, 0b011110, "udivcc">; 135def UDIVCCri : F3_2<2, 0b011110, "udivcc">; 136def SDIVCCrr : F3_1<2, 0b011111, "sdivcc">; 137def SDIVCCri : F3_2<2, 0b011111, "sdivcc">; 138 139// Section B.20 - SAVE and RESTORE, p. 117 140def SAVErr : F3_1<2, 0b111100, "save">; // save r, r, r 141def SAVEri : F3_2<2, 0b111100, "save">; // save r, i, r 142def RESTORErr : F3_1<2, 0b111101, "restore">; // restore r, r, r 143def RESTOREri : F3_2<2, 0b111101, "restore">; // restore r, i, r 144 145// Section B.21 - Branch on Integer Condition Codes Instructions, p. 119 146 147// conditional branch class: 148class BranchV8<bits<4> cc, string nm> : F2_2<cc, 0b010, nm> { 149 let isBranch = 1; 150 let isTerminator = 1; 151 let hasDelaySlot = 1; 152} 153 154let isBarrier = 1 in 155 def BA : BranchV8<0b1000, "ba">; 156def BN : BranchV8<0b0000, "bn">; 157def BNE : BranchV8<0b1001, "bne">; 158def BE : BranchV8<0b0001, "be">; 159def BG : BranchV8<0b1010, "bg">; 160def BLE : BranchV8<0b0010, "ble">; 161def BGE : BranchV8<0b1011, "bge">; 162def BL : BranchV8<0b0011, "bl">; 163def BGU : BranchV8<0b1100, "bgu">; 164def BLEU : BranchV8<0b0100, "bleu">; 165def BCC : BranchV8<0b1101, "bcc">; 166def BCS : BranchV8<0b0101, "bcs">; 167 168// Section B.22 - Branch on Floating-point Condition Codes Instructions, p. 121 169 170// floating-point conditional branch class: 171class FPBranchV8<bits<4> cc, string nm> : F2_2<cc, 0b110, nm> { 172 let isBranch = 1; 173 let isTerminator = 1; 174 let hasDelaySlot = 1; 175} 176 177def FBA : FPBranchV8<0b1000, "fba">; 178def FBN : FPBranchV8<0b0000, "fbn">; 179def FBU : FPBranchV8<0b0111, "fbu">; 180def FBG : FPBranchV8<0b0110, "fbg">; 181def FBUG : FPBranchV8<0b0101, "fbug">; 182def FBL : FPBranchV8<0b0100, "fbl">; 183def FBUL : FPBranchV8<0b0011, "fbul">; 184def FBLG : FPBranchV8<0b0010, "fblg">; 185def FBNE : FPBranchV8<0b0001, "fbne">; 186def FBE : FPBranchV8<0b1001, "fbe">; 187def FBUE : FPBranchV8<0b1010, "fbue">; 188def FBGE : FPBranchV8<0b1011, "fbge">; 189def FBUGE: FPBranchV8<0b1100, "fbuge">; 190def FBLE : FPBranchV8<0b1101, "fble">; 191def FBULE: FPBranchV8<0b1110, "fbule">; 192def FBO : FPBranchV8<0b1111, "fbo">; 193 194// Section B.24 - Call and Link Instruction, p. 125 195// This is the only Format 1 instruction 196let Defs = [O0, O1, O2, O3, O4, O5], hasDelaySlot = 1, isCall = 1 in { 197 // pc-relative call: 198 def CALL : InstV8 { 199 bits<30> disp; 200 let op = 1; 201 let Inst{29-0} = disp; 202 let Name = "call"; 203 } 204 // indirect call: 205 def JMPLrr : F3_1<2, 0b111000, "jmpl">; // jmpl [rs1+rs2], rd 206} 207 208// Section B.29 - Write State Register Instructions 209def WRrr : F3_1<2, 0b110000, "wr">; // wr rs1, rs2, rd 210def WRri : F3_2<2, 0b110000, "wr">; // wr rs1, imm, rd 211 212// Convert Integer to Floating-point Instructions, p. 141 213def FITOS : F3_3<2, 0b110100, 0b011000100, "fitos">; 214def FITOD : F3_3<2, 0b110100, 0b011001000, "fitod">; 215 216// Convert between Floating-point Formats Instructions, p. 143 217def FSTOD : F3_3<2, 0b110100, 0b011001001, "fstod">; 218def FDTOS : F3_3<2, 0b110100, 0b011000110, "fdtos">; 219 220// Floating-point Move Instructions, p. 144 221def FMOVS : F3_3<2, 0b110100, 0b000000001, "fmovs">; 222def FNEGS : F3_3<2, 0b110100, 0b000000101, "fnegs">; 223def FABSS : F3_3<2, 0b110100, 0b000001001, "fabss">; 224 225// Floating-point Add and Subtract Instructions, p. 146 226def FADDS : F3_3<2, 0b110100, 0b001000001, "fadds">; 227def FADDD : F3_3<2, 0b110100, 0b001000010, "faddd">; 228def FSUBS : F3_3<2, 0b110100, 0b001000101, "fsubs">; 229def FSUBD : F3_3<2, 0b110100, 0b001000110, "fsubd">; 230 231// Floating-point Multiply and Divide Instructions, p. 147 232def FMULS : F3_3<2, 0b110100, 0b001001001, "fmuls">; 233def FMULD : F3_3<2, 0b110100, 0b001001010, "fmuld">; 234def FSMULD : F3_3<2, 0b110100, 0b001101001, "fsmuld">; 235def FDIVS : F3_3<2, 0b110100, 0b001001101, "fdivs">; 236def FDIVD : F3_3<2, 0b110100, 0b001001110, "fdivd">; 237 238// Floating-point Compare Instructions, p. 148 239// Note: the 2nd template arg is different for these guys. 240// Note 2: the result of a FCMP is not available until the 2nd cycle 241// after the instr is retired, but there is no interlock. This behavior 242// is modelled as a delay slot. 243let hasDelaySlot = 1 in { 244 def FCMPS : F3_3<2, 0b110101, 0b001010001, "fcmps">; 245 def FCMPD : F3_3<2, 0b110101, 0b001010010, "fcmpd">; 246 def FCMPES : F3_3<2, 0b110101, 0b001010101, "fcmpes">; 247 def FCMPED : F3_3<2, 0b110101, 0b001010110, "fcmped">; 248} 249 250