SparcInstrInfo.td revision e33a3ff942d33edfb619867c84b1d4589d3a582d
1//===- SparcV8Instrs.td - Target Description for SparcV8 Target -----------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the SparcV8 instructions in TableGen format. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// Instruction format superclass 16//===----------------------------------------------------------------------===// 17 18class InstV8 : Instruction { // SparcV8 instruction baseline 19 field bits<32> Inst; 20 21 let Namespace = "V8"; 22 23 bits<2> op; 24 let Inst{31-30} = op; // Top two bits are the 'op' field 25 26 // Bit attributes specific to SparcV8 instructions 27 bit isPasi = 0; // Does this instruction affect an alternate addr space? 28 bit isPrivileged = 0; // Is this a privileged instruction? 29} 30 31include "SparcV8InstrFormats.td" 32 33//===----------------------------------------------------------------------===// 34// Instruction Pattern Stuff 35//===----------------------------------------------------------------------===// 36 37def simm13 : PatLeaf<(imm), [{ 38 // simm13 predicate - True if the imm fits in a 13-bit sign extended field. 39 return (((int)N->getValue() << (32-13)) >> (32-13)) == (int)N->getValue(); 40}]>; 41 42//===----------------------------------------------------------------------===// 43// Instructions 44//===----------------------------------------------------------------------===// 45 46// Pseudo instructions. 47class PseudoInstV8<string asmstr, dag ops> : InstV8 { 48 let AsmString = asmstr; 49 dag OperandList = ops; 50} 51def PHI : PseudoInstV8<"PHI", (ops variable_ops)>; 52def ADJCALLSTACKDOWN : PseudoInstV8<"!ADJCALLSTACKDOWN $amt", 53 (ops i32imm:$amt)>; 54def ADJCALLSTACKUP : PseudoInstV8<"!ADJCALLSTACKUP $amt", 55 (ops i32imm:$amt)>; 56//def IMPLICIT_USE : PseudoInstV8<"!IMPLICIT_USE",(ops variable_ops)>; 57def IMPLICIT_DEF : PseudoInstV8<"!IMPLICIT_DEF $dst", 58 (ops IntRegs:$dst)>; 59def FpMOVD : PseudoInstV8<"!FpMOVD", (ops)>; // pseudo 64-bit double move 60 61// Section A.3 - Synthetic Instructions, p. 85 62// special cases of JMPL: 63let isReturn = 1, isTerminator = 1, hasDelaySlot = 1 in { 64 let rd = I7.Num, rs1 = G0.Num, simm13 = 8 in 65 def RET : F3_2<2, 0b111000, 66 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 67 "ret $b, $c, $dst", []>; 68 let rd = O7.Num, rs1 = G0.Num, simm13 = 8 in 69 def RETL: F3_2<2, 0b111000, (ops), 70 "retl", [(ret)]>; 71} 72// CMP is a special case of SUBCC where destination is ignored, by setting it to 73// %g0 (hardwired zero). 74// FIXME: should keep track of the fact that it defs the integer condition codes 75let rd = 0 in 76 def CMPri: F3_2<2, 0b010100, 77 (ops IntRegs:$b, i32imm:$c), 78 "cmp $b, $c", []>; 79 80// Section B.1 - Load Integer Instructions, p. 90 81def LDSB: F3_2<3, 0b001001, 82 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 83 "ldsb [$b+$c], $dst", []>; 84def LDSH: F3_2<3, 0b001010, 85 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 86 "ldsh [$b+$c], $dst", []>; 87def LDUB: F3_2<3, 0b000001, 88 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 89 "ldub [$b+$c], $dst", []>; 90def LDUH: F3_2<3, 0b000010, 91 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 92 "lduh [$b+$c], $dst", []>; 93def LD : F3_2<3, 0b000000, 94 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 95 "ld [$b+$c], $dst", []>; 96def LDD : F3_2<3, 0b000011, 97 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 98 "ldd [$b+$c], $dst", []>; 99 100// Section B.2 - Load Floating-point Instructions, p. 92 101def LDFrr : F3_1<3, 0b100000, 102 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 103 "ld [$b+$c], $dst", []>; 104def LDFri : F3_2<3, 0b100000, 105 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 106 "ld [$b+$c], $dst", []>; 107def LDDFrr : F3_1<3, 0b100011, 108 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 109 "ldd [$b+$c], $dst", []>; 110def LDDFri : F3_2<3, 0b100011, 111 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 112 "ldd [$b+$c], $dst", []>; 113def LDFSRrr: F3_1<3, 0b100001, 114 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 115 "ld [$b+$c], $dst", []>; 116def LDFSRri: F3_2<3, 0b100001, 117 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 118 "ld [$b+$c], $dst", []>; 119 120// Section B.4 - Store Integer Instructions, p. 95 121def STB : F3_2<3, 0b000101, 122 (ops IntRegs:$base, IntRegs:$offset, i32imm:$src), 123 "stb $src, [$base+$offset]", []>; 124def STH : F3_2<3, 0b000110, 125 (ops IntRegs:$base, IntRegs:$offset, i32imm:$src), 126 "sth $src, [$base+$offset]", []>; 127def ST : F3_2<3, 0b000100, 128 (ops IntRegs:$base, IntRegs:$offset, i32imm:$src), 129 "st $src, [$base+$offset]", []>; 130def STD : F3_2<3, 0b000111, 131 (ops IntRegs:$base, IntRegs:$offset, i32imm:$src), 132 "std $src, [$base+$offset]", []>; 133 134// Section B.5 - Store Floating-point Instructions, p. 97 135def STFrr : F3_1<3, 0b100100, 136 (ops IntRegs:$base, IntRegs:$offset, IntRegs:$src), 137 "st $src, [$base+$offset]", []>; 138def STFri : F3_2<3, 0b100100, 139 (ops IntRegs:$base, IntRegs:$offset, i32imm:$src), 140 "st $src, [$base+$offset]", []>; 141def STDFrr : F3_1<3, 0b100111, 142 (ops IntRegs:$base, IntRegs:$offset, IntRegs:$src), 143 "std $src, [$base+$offset]", []>; 144def STDFri : F3_2<3, 0b100111, 145 (ops IntRegs:$base, IntRegs:$offset, i32imm:$src), 146 "std $src, [$base+$offset]", []>; 147def STFSRrr : F3_1<3, 0b100101, 148 (ops IntRegs:$base, IntRegs:$offset, IntRegs:$src), 149 "st $src, [$base+$offset]", []>; 150def STFSRri : F3_2<3, 0b100101, 151 (ops IntRegs:$base, IntRegs:$offset, i32imm:$src), 152 "st $src, [$base+$offset]", []>; 153def STDFQrr : F3_1<3, 0b100110, 154 (ops IntRegs:$base, IntRegs:$offset, IntRegs:$src), 155 "std $src, [$base+$offset]", []>; 156def STDFQri : F3_2<3, 0b100110, 157 (ops IntRegs:$base, IntRegs:$offset, i32imm:$src), 158 "std $src, [$base+$offset]", []>; 159 160// Section B.9 - SETHI Instruction, p. 104 161def SETHIi: F2_1<0b100, 162 (ops IntRegs:$dst, i32imm:$src), 163 "sethi $src, $dst">; 164 165// Section B.10 - NOP Instruction, p. 105 166// (It's a special case of SETHI) 167let rd = 0, imm22 = 0 in 168 def NOP : F2_1<0b100, (ops), "nop">; 169 170// Section B.11 - Logical Instructions, p. 106 171def ANDrr : F3_1<2, 0b000001, 172 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 173 "and $b, $c, $dst", []>; 174def ANDri : F3_2<2, 0b000001, 175 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 176 "and $b, $c, $dst", 177 [(set IntRegs:$dst, (and IntRegs:$b, simm13:$c))]>; 178def ANDCCrr : F3_1<2, 0b010001, 179 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 180 "andcc $b, $c, $dst", []>; 181def ANDCCri : F3_2<2, 0b010001, 182 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 183 "andcc $b, $c, $dst", []>; 184def ANDNrr : F3_1<2, 0b000101, 185 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 186 "andn $b, $c, $dst", []>; 187def ANDNri : F3_2<2, 0b000101, 188 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 189 "andn $b, $c, $dst", []>; 190def ANDNCCrr: F3_1<2, 0b010101, 191 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 192 "andncc $b, $c, $dst", []>; 193def ANDNCCri: F3_2<2, 0b010101, 194 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 195 "andncc $b, $c, $dst", []>; 196def ORrr : F3_1<2, 0b000010, 197 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 198 "or $b, $c, $dst", []>; 199def ORri : F3_2<2, 0b000010, 200 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 201 "or $b, $c, $dst", 202 [(set IntRegs:$dst, (or IntRegs:$b, simm13:$c))]>; 203def ORCCrr : F3_1<2, 0b010010, 204 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 205 "orcc $b, $c, $dst", []>; 206def ORCCri : F3_2<2, 0b010010, 207 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 208 "orcc $b, $c, $dst", []>; 209def ORNrr : F3_1<2, 0b000110, 210 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 211 "orn $b, $c, $dst", []>; 212def ORNri : F3_2<2, 0b000110, 213 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 214 "orn $b, $c, $dst", []>; 215def ORNCCrr : F3_1<2, 0b010110, 216 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 217 "orncc $b, $c, $dst", []>; 218def ORNCCri : F3_2<2, 0b010110, 219 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 220 "orncc $b, $c, $dst", []>; 221def XORrr : F3_1<2, 0b000011, 222 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 223 "xor $b, $c, $dst", []>; 224def XORri : F3_2<2, 0b000011, 225 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 226 "xor $b, $c, $dst", 227 [(set IntRegs:$dst, (xor IntRegs:$b, simm13:$c))]>; 228def XORCCrr : F3_1<2, 0b010011, 229 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 230 "xorcc $b, $c, $dst", []>; 231def XORCCri : F3_2<2, 0b010011, 232 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 233 "xorcc $b, $c, $dst", []>; 234def XNORrr : F3_1<2, 0b000111, 235 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 236 "xnor $b, $c, $dst", []>; 237def XNORri : F3_2<2, 0b000111, 238 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 239 "xnor $b, $c, $dst", []>; 240def XNORCCrr: F3_1<2, 0b010111, 241 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 242 "xnorcc $b, $c, $dst", []>; 243def XNORCCri: F3_2<2, 0b010111, 244 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 245 "xnorcc $b, $c, $dst", []>; 246 247// Section B.12 - Shift Instructions, p. 107 248def SLLrr : F3_1<2, 0b100101, 249 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 250 "sll $b, $c, $dst", []>; 251def SLLri : F3_2<2, 0b100101, 252 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 253 "sll $b, $c, $dst", []>; 254def SRLrr : F3_1<2, 0b100110, 255 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 256 "srl $b, $c, $dst", []>; 257def SRLri : F3_2<2, 0b100110, 258 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 259 "srl $b, $c, $dst", []>; 260def SRArr : F3_1<2, 0b100111, 261 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 262 "sra $b, $c, $dst", []>; 263def SRAri : F3_2<2, 0b100111, 264 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 265 "sla $b, $c, $dst", []>; 266 267// Section B.13 - Add Instructions, p. 108 268def ADDrr : F3_1<2, 0b000000, 269 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 270 "add $b, $c, $dst", []>; 271def ADDri : F3_2<2, 0b000000, 272 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 273 "add $b, $c, $dst", 274 [(set IntRegs:$dst, (add IntRegs:$b, simm13:$c))]>; 275def ADDCCrr : F3_1<2, 0b010000, 276 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 277 "addcc $b, $c, $dst", []>; 278def ADDCCri : F3_2<2, 0b010000, 279 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 280 "addcc $b, $c, $dst", []>; 281def ADDXrr : F3_1<2, 0b001000, 282 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 283 "addx $b, $c, $dst", []>; 284def ADDXri : F3_2<2, 0b001000, 285 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 286 "addx $b, $c, $dst", []>; 287def ADDXCCrr: F3_1<2, 0b011000, 288 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 289 "addxcc $b, $c, $dst", []>; 290def ADDXCCri: F3_2<2, 0b011000, 291 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 292 "addxcc $b, $c, $dst", []>; 293 294// Section B.15 - Subtract Instructions, p. 110 295def SUBrr : F3_1<2, 0b000100, 296 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 297 "sub $b, $c, $dst", []>; 298def SUBri : F3_2<2, 0b000100, 299 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 300 "sub $b, $c, $dst", 301 [(set IntRegs:$dst, (sub IntRegs:$b, simm13:$c))]>; 302def SUBCCrr : F3_1<2, 0b010100, 303 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 304 "subcc $b, $c, $dst", []>; 305def SUBCCri : F3_2<2, 0b010100, 306 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 307 "subcc $b, $c, $dst", []>; 308def SUBXrr : F3_1<2, 0b001100, 309 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 310 "subx $b, $c, $dst", []>; 311def SUBXri : F3_2<2, 0b001100, 312 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 313 "subx $b, $c, $dst", []>; 314def SUBXCCrr: F3_1<2, 0b011100, 315 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 316 "subxcc $b, $c, $dst", []>; 317def SUBXCCri: F3_2<2, 0b011100, 318 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 319 "subxcc $b, $c, $dst", []>; 320 321// Section B.18 - Multiply Instructions, p. 113 322def UMULrr : F3_1<2, 0b001010, 323 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 324 "umul $b, $c, $dst", []>; 325def UMULri : F3_2<2, 0b001010, 326 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 327 "umul $b, $c, $dst", []>; 328def SMULrr : F3_1<2, 0b001011, 329 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 330 "smul $b, $c, $dst", []>; 331def SMULri : F3_2<2, 0b001011, 332 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 333 "smul $b, $c, $dst", []>; 334def UMULCCrr: F3_1<2, 0b011010, 335 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 336 "umulcc $b, $c, $dst", []>; 337def UMULCCri: F3_2<2, 0b011010, 338 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 339 "umulcc $b, $c, $dst", []>; 340def SMULCCrr: F3_1<2, 0b011011, 341 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 342 "smulcc $b, $c, $dst", []>; 343def SMULCCri: F3_2<2, 0b011011, 344 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 345 "smulcc $b, $c, $dst", []>; 346 347// Section B.19 - Divide Instructions, p. 115 348def UDIVrr : F3_1<2, 0b001110, 349 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 350 "udiv $b, $c, $dst", []>; 351def UDIVri : F3_2<2, 0b001110, 352 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 353 "udiv $b, $c, $dst", []>; 354def SDIVrr : F3_1<2, 0b001111, 355 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 356 "sdiv $b, $c, $dst", []>; 357def SDIVri : F3_2<2, 0b001111, 358 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 359 "sdiv $b, $c, $dst", []>; 360def UDIVCCrr : F3_1<2, 0b011110, 361 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 362 "udivcc $b, $c, $dst", []>; 363def UDIVCCri : F3_2<2, 0b011110, 364 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 365 "udivcc $b, $c, $dst", []>; 366def SDIVCCrr : F3_1<2, 0b011111, 367 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 368 "sdivcc $b, $c, $dst", []>; 369def SDIVCCri : F3_2<2, 0b011111, 370 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 371 "sdivcc $b, $c, $dst", []>; 372 373// Section B.20 - SAVE and RESTORE, p. 117 374def SAVErr : F3_1<2, 0b111100, 375 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 376 "save $b, $c, $dst", []>; 377def SAVEri : F3_2<2, 0b111100, 378 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 379 "save $b, $c, $dst", []>; 380def RESTORErr : F3_1<2, 0b111101, 381 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 382 "restore $b, $c, $dst", []>; 383def RESTOREri : F3_2<2, 0b111101, 384 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 385 "restore $b, $c, $dst", []>; 386 387// Section B.21 - Branch on Integer Condition Codes Instructions, p. 119 388 389// conditional branch class: 390class BranchV8<bits<4> cc, dag ops, string asmstr> 391 : F2_2<cc, 0b010, ops, asmstr> { 392 let isBranch = 1; 393 let isTerminator = 1; 394 let hasDelaySlot = 1; 395} 396 397let isBarrier = 1 in 398 def BA : BranchV8<0b1000, (ops IntRegs:$dst), "ba $dst">; 399def BN : BranchV8<0b0000, (ops IntRegs:$dst), "bn $dst">; 400def BNE : BranchV8<0b1001, (ops IntRegs:$dst), "bne $dst">; 401def BE : BranchV8<0b0001, (ops IntRegs:$dst), "be $dst">; 402def BG : BranchV8<0b1010, (ops IntRegs:$dst), "bg $dst">; 403def BLE : BranchV8<0b0010, (ops IntRegs:$dst), "ble $dst">; 404def BGE : BranchV8<0b1011, (ops IntRegs:$dst), "bge $dst">; 405def BL : BranchV8<0b0011, (ops IntRegs:$dst), "bl $dst">; 406def BGU : BranchV8<0b1100, (ops IntRegs:$dst), "bgu $dst">; 407def BLEU : BranchV8<0b0100, (ops IntRegs:$dst), "bleu $dst">; 408def BCC : BranchV8<0b1101, (ops IntRegs:$dst), "bcc $dst">; 409def BCS : BranchV8<0b0101, (ops IntRegs:$dst), "bcs $dst">; 410 411// Section B.22 - Branch on Floating-point Condition Codes Instructions, p. 121 412 413// floating-point conditional branch class: 414class FPBranchV8<bits<4> cc, dag ops, string asmstr> 415 : F2_2<cc, 0b110, ops, asmstr> { 416 let isBranch = 1; 417 let isTerminator = 1; 418 let hasDelaySlot = 1; 419} 420 421def FBA : FPBranchV8<0b1000, (ops IntRegs:$dst), "fba $dst">; 422def FBN : FPBranchV8<0b0000, (ops IntRegs:$dst), "fbn $dst">; 423def FBU : FPBranchV8<0b0111, (ops IntRegs:$dst), "fbu $dst">; 424def FBG : FPBranchV8<0b0110, (ops IntRegs:$dst), "fbg $dst">; 425def FBUG : FPBranchV8<0b0101, (ops IntRegs:$dst), "fbug $dst">; 426def FBL : FPBranchV8<0b0100, (ops IntRegs:$dst), "fbl $dst">; 427def FBUL : FPBranchV8<0b0011, (ops IntRegs:$dst), "fbul $dst">; 428def FBLG : FPBranchV8<0b0010, (ops IntRegs:$dst), "fblg $dst">; 429def FBNE : FPBranchV8<0b0001, (ops IntRegs:$dst), "fbne $dst">; 430def FBE : FPBranchV8<0b1001, (ops IntRegs:$dst), "fbe $dst">; 431def FBUE : FPBranchV8<0b1010, (ops IntRegs:$dst), "fbue $dst">; 432def FBGE : FPBranchV8<0b1011, (ops IntRegs:$dst), "fbge $dst">; 433def FBUGE: FPBranchV8<0b1100, (ops IntRegs:$dst), "fbuge $dst">; 434def FBLE : FPBranchV8<0b1101, (ops IntRegs:$dst), "fble $dst">; 435def FBULE: FPBranchV8<0b1110, (ops IntRegs:$dst), "fbule $dst">; 436def FBO : FPBranchV8<0b1111, (ops IntRegs:$dst), "fbo $dst">; 437 438 439 440// Section B.24 - Call and Link Instruction, p. 125 441// This is the only Format 1 instruction 442let Uses = [O0, O1, O2, O3, O4, O5], hasDelaySlot = 1, isCall = 1 in { 443 // pc-relative call: 444 let Defs = [O0, O1, O2, O3, O4, O5, O7, G1, G2, G3, G4, G5, G6, G7, 445 D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15] in 446 def CALL : InstV8 { 447 let OperandList = (ops IntRegs:$dst); 448 bits<30> disp; 449 let op = 1; 450 let Inst{29-0} = disp; 451 let AsmString = "call $dst"; 452 } 453 454 // indirect call (O7 is an EXPLICIT def in indirect calls, so it cannot also 455 // be an implicit def): 456 let Defs = [O0, O1, O2, O3, O4, O5, G1, G2, G3, G4, G5, G6, G7, 457 D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15] in 458 def JMPLrr : F3_1<2, 0b111000, 459 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 460 "jmpl $b+$c, $dst", []>; 461} 462 463// Section B.29 - Write State Register Instructions 464def WRrr : F3_1<2, 0b110000, 465 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 466 "wr $b, $c, $dst", []>; 467def WRri : F3_2<2, 0b110000, 468 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 469 "wr $b, $c, $dst", []>; 470 471// Convert Integer to Floating-point Instructions, p. 141 472def FITOS : F3_3<2, 0b110100, 0b011000100, 473 (ops FPRegs:$dst, FPRegs:$src), 474 "fitos $src, $dst">; 475def FITOD : F3_3<2, 0b110100, 0b011001000, 476 (ops DFPRegs:$dst, DFPRegs:$src), 477 "fitod $src, $dst">; 478 479// Convert Floating-point to Integer Instructions, p. 142 480def FSTOI : F3_3<2, 0b110100, 0b011010001, 481 (ops FPRegs:$dst, FPRegs:$src), 482 "fstoi $src, $dst">; 483def FDTOI : F3_3<2, 0b110100, 0b011010010, 484 (ops DFPRegs:$dst, DFPRegs:$src), 485 "fdtoi $src, $dst">; 486 487// Convert between Floating-point Formats Instructions, p. 143 488def FSTOD : F3_3<2, 0b110100, 0b011001001, 489 (ops DFPRegs:$dst, FPRegs:$src), 490 "fstod $src, $dst">; 491def FDTOS : F3_3<2, 0b110100, 0b011000110, 492 (ops FPRegs:$dst, DFPRegs:$src), 493 "fdtos $src, $dst">; 494 495// Floating-point Move Instructions, p. 144 496def FMOVS : F3_3<2, 0b110100, 0b000000001, 497 (ops FPRegs:$dst, FPRegs:$src), 498 "fmovs $src, $dst">; 499def FNEGS : F3_3<2, 0b110100, 0b000000101, 500 (ops FPRegs:$dst, FPRegs:$src), 501 "fnegs $src, $dst">; 502def FABSS : F3_3<2, 0b110100, 0b000001001, 503 (ops FPRegs:$dst, FPRegs:$src), 504 "fabss $src, $dst">; 505 506// Floating-point Add and Subtract Instructions, p. 146 507def FADDS : F3_3<2, 0b110100, 0b001000001, 508 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2), 509 "fadds $src1, $src2, $dst">; 510def FADDD : F3_3<2, 0b110100, 0b001000010, 511 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2), 512 "faddd $src1, $src2, $dst">; 513def FSUBS : F3_3<2, 0b110100, 0b001000101, 514 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2), 515 "fsubs $src1, $src2, $dst">; 516def FSUBD : F3_3<2, 0b110100, 0b001000110, 517 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2), 518 "fsubd $src1, $src2, $dst">; 519 520// Floating-point Multiply and Divide Instructions, p. 147 521def FMULS : F3_3<2, 0b110100, 0b001001001, 522 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2), 523 "fmuls $src1, $src2, $dst">; 524def FMULD : F3_3<2, 0b110100, 0b001001010, 525 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2), 526 "fmuld $src1, $src2, $dst">; 527def FSMULD : F3_3<2, 0b110100, 0b001101001, 528 (ops DFPRegs:$dst, FPRegs:$src1, FPRegs:$src2), 529 "fsmuld $src1, $src2, $dst">; 530def FDIVS : F3_3<2, 0b110100, 0b001001101, 531 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2), 532 "fdivs $src1, $src2, $dst">; 533def FDIVD : F3_3<2, 0b110100, 0b001001110, 534 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2), 535 "fdivd $src1, $src2, $dst">; 536 537// Floating-point Compare Instructions, p. 148 538// Note: the 2nd template arg is different for these guys. 539// Note 2: the result of a FCMP is not available until the 2nd cycle 540// after the instr is retired, but there is no interlock. This behavior 541// is modelled with a forced noop after the instruction. 542def FCMPS : F3_3<2, 0b110101, 0b001010001, 543 (ops FPRegs:$src1, FPRegs:$src2), 544 "fcmps $src1, $src2\n\tnop">; 545def FCMPD : F3_3<2, 0b110101, 0b001010010, 546 (ops DFPRegs:$src1, DFPRegs:$src2), 547 "fcmpd $src1, $src2\n\tnop">; 548def FCMPES : F3_3<2, 0b110101, 0b001010101, 549 (ops FPRegs:$src1, FPRegs:$src2), 550 "fcmpes $src1, $src2\n\tnop">; 551def FCMPED : F3_3<2, 0b110101, 0b001010110, 552 (ops DFPRegs:$src1, DFPRegs:$src2), 553 "fcmped $src1, $src2\n\tnop">; 554