SparcInstrInfo.td revision e50ed30282bb5b4a9ed952580523f2dda16215ac
1//===- SparcInstrInfo.td - Target Description for Sparc Target ------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the Sparc instructions in TableGen format. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// Instruction format superclass 16//===----------------------------------------------------------------------===// 17 18include "SparcInstrFormats.td" 19 20//===----------------------------------------------------------------------===// 21// Feature predicates. 22//===----------------------------------------------------------------------===// 23 24// HasV9 - This predicate is true when the target processor supports V9 25// instructions. Note that the machine may be running in 32-bit mode. 26def HasV9 : Predicate<"Subtarget.isV9()">; 27 28// HasNoV9 - This predicate is true when the target doesn't have V9 29// instructions. Use of this is just a hack for the isel not having proper 30// costs for V8 instructions that are more expensive than their V9 ones. 31def HasNoV9 : Predicate<"!Subtarget.isV9()">; 32 33// HasVIS - This is true when the target processor has VIS extensions. 34def HasVIS : Predicate<"Subtarget.isVIS()">; 35 36// UseDeprecatedInsts - This predicate is true when the target processor is a 37// V8, or when it is V9 but the V8 deprecated instructions are efficient enough 38// to use when appropriate. In either of these cases, the instruction selector 39// will pick deprecated instructions. 40def UseDeprecatedInsts : Predicate<"Subtarget.useDeprecatedV8Instructions()">; 41 42//===----------------------------------------------------------------------===// 43// Instruction Pattern Stuff 44//===----------------------------------------------------------------------===// 45 46def simm11 : PatLeaf<(imm), [{ 47 // simm11 predicate - True if the imm fits in a 11-bit sign extended field. 48 return (((int)N->getZExtValue() << (32-11)) >> (32-11)) == 49 (int)N->getZExtValue(); 50}]>; 51 52def simm13 : PatLeaf<(imm), [{ 53 // simm13 predicate - True if the imm fits in a 13-bit sign extended field. 54 return (((int)N->getZExtValue() << (32-13)) >> (32-13)) == 55 (int)N->getZExtValue(); 56}]>; 57 58def LO10 : SDNodeXForm<imm, [{ 59 return CurDAG->getTargetConstant((unsigned)N->getZExtValue() & 1023, 60 EVT::i32); 61}]>; 62 63def HI22 : SDNodeXForm<imm, [{ 64 // Transformation function: shift the immediate value down into the low bits. 65 return CurDAG->getTargetConstant((unsigned)N->getZExtValue() >> 10, EVT::i32); 66}]>; 67 68def SETHIimm : PatLeaf<(imm), [{ 69 return (((unsigned)N->getZExtValue() >> 10) << 10) == 70 (unsigned)N->getZExtValue(); 71}], HI22>; 72 73// Addressing modes. 74def ADDRrr : ComplexPattern<i32, 2, "SelectADDRrr", [], []>; 75def ADDRri : ComplexPattern<i32, 2, "SelectADDRri", [frameindex], []>; 76 77// Address operands 78def MEMrr : Operand<i32> { 79 let PrintMethod = "printMemOperand"; 80 let MIOperandInfo = (ops IntRegs, IntRegs); 81} 82def MEMri : Operand<i32> { 83 let PrintMethod = "printMemOperand"; 84 let MIOperandInfo = (ops IntRegs, i32imm); 85} 86 87// Branch targets have OtherVT type. 88def brtarget : Operand<OtherVT>; 89def calltarget : Operand<i32>; 90 91// Operand for printing out a condition code. 92let PrintMethod = "printCCOperand" in 93 def CCOp : Operand<i32>; 94 95def SDTSPcmpfcc : 96SDTypeProfile<0, 2, [SDTCisFP<0>, SDTCisSameAs<0, 1>]>; 97def SDTSPbrcc : 98SDTypeProfile<0, 2, [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>; 99def SDTSPselectcc : 100SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>]>; 101def SDTSPFTOI : 102SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisFP<1>]>; 103def SDTSPITOF : 104SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f32>]>; 105 106def SPcmpicc : SDNode<"SPISD::CMPICC", SDTIntBinOp, [SDNPOutFlag]>; 107def SPcmpfcc : SDNode<"SPISD::CMPFCC", SDTSPcmpfcc, [SDNPOutFlag]>; 108def SPbricc : SDNode<"SPISD::BRICC", SDTSPbrcc, [SDNPHasChain, SDNPInFlag]>; 109def SPbrfcc : SDNode<"SPISD::BRFCC", SDTSPbrcc, [SDNPHasChain, SDNPInFlag]>; 110 111def SPhi : SDNode<"SPISD::Hi", SDTIntUnaryOp>; 112def SPlo : SDNode<"SPISD::Lo", SDTIntUnaryOp>; 113 114def SPftoi : SDNode<"SPISD::FTOI", SDTSPFTOI>; 115def SPitof : SDNode<"SPISD::ITOF", SDTSPITOF>; 116 117def SPselecticc : SDNode<"SPISD::SELECT_ICC", SDTSPselectcc, [SDNPInFlag]>; 118def SPselectfcc : SDNode<"SPISD::SELECT_FCC", SDTSPselectcc, [SDNPInFlag]>; 119 120// These are target-independent nodes, but have target-specific formats. 121def SDT_SPCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>; 122def SDT_SPCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, 123 SDTCisVT<1, i32> ]>; 124 125def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_SPCallSeqStart, 126 [SDNPHasChain, SDNPOutFlag]>; 127def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_SPCallSeqEnd, 128 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; 129 130def SDT_SPCall : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>; 131def call : SDNode<"SPISD::CALL", SDT_SPCall, 132 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; 133 134def retflag : SDNode<"SPISD::RET_FLAG", SDTNone, 135 [SDNPHasChain, SDNPOptInFlag]>; 136 137//===----------------------------------------------------------------------===// 138// SPARC Flag Conditions 139//===----------------------------------------------------------------------===// 140 141// Note that these values must be kept in sync with the CCOp::CondCode enum 142// values. 143class ICC_VAL<int N> : PatLeaf<(i32 N)>; 144def ICC_NE : ICC_VAL< 9>; // Not Equal 145def ICC_E : ICC_VAL< 1>; // Equal 146def ICC_G : ICC_VAL<10>; // Greater 147def ICC_LE : ICC_VAL< 2>; // Less or Equal 148def ICC_GE : ICC_VAL<11>; // Greater or Equal 149def ICC_L : ICC_VAL< 3>; // Less 150def ICC_GU : ICC_VAL<12>; // Greater Unsigned 151def ICC_LEU : ICC_VAL< 4>; // Less or Equal Unsigned 152def ICC_CC : ICC_VAL<13>; // Carry Clear/Great or Equal Unsigned 153def ICC_CS : ICC_VAL< 5>; // Carry Set/Less Unsigned 154def ICC_POS : ICC_VAL<14>; // Positive 155def ICC_NEG : ICC_VAL< 6>; // Negative 156def ICC_VC : ICC_VAL<15>; // Overflow Clear 157def ICC_VS : ICC_VAL< 7>; // Overflow Set 158 159class FCC_VAL<int N> : PatLeaf<(i32 N)>; 160def FCC_U : FCC_VAL<23>; // Unordered 161def FCC_G : FCC_VAL<22>; // Greater 162def FCC_UG : FCC_VAL<21>; // Unordered or Greater 163def FCC_L : FCC_VAL<20>; // Less 164def FCC_UL : FCC_VAL<19>; // Unordered or Less 165def FCC_LG : FCC_VAL<18>; // Less or Greater 166def FCC_NE : FCC_VAL<17>; // Not Equal 167def FCC_E : FCC_VAL<25>; // Equal 168def FCC_UE : FCC_VAL<24>; // Unordered or Equal 169def FCC_GE : FCC_VAL<25>; // Greater or Equal 170def FCC_UGE : FCC_VAL<26>; // Unordered or Greater or Equal 171def FCC_LE : FCC_VAL<27>; // Less or Equal 172def FCC_ULE : FCC_VAL<28>; // Unordered or Less or Equal 173def FCC_O : FCC_VAL<29>; // Ordered 174 175//===----------------------------------------------------------------------===// 176// Instruction Class Templates 177//===----------------------------------------------------------------------===// 178 179/// F3_12 multiclass - Define a normal F3_1/F3_2 pattern in one shot. 180multiclass F3_12<string OpcStr, bits<6> Op3Val, SDNode OpNode> { 181 def rr : F3_1<2, Op3Val, 182 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c), 183 !strconcat(OpcStr, " $b, $c, $dst"), 184 [(set IntRegs:$dst, (OpNode IntRegs:$b, IntRegs:$c))]>; 185 def ri : F3_2<2, Op3Val, 186 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c), 187 !strconcat(OpcStr, " $b, $c, $dst"), 188 [(set IntRegs:$dst, (OpNode IntRegs:$b, simm13:$c))]>; 189} 190 191/// F3_12np multiclass - Define a normal F3_1/F3_2 pattern in one shot, with no 192/// pattern. 193multiclass F3_12np<string OpcStr, bits<6> Op3Val> { 194 def rr : F3_1<2, Op3Val, 195 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c), 196 !strconcat(OpcStr, " $b, $c, $dst"), []>; 197 def ri : F3_2<2, Op3Val, 198 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c), 199 !strconcat(OpcStr, " $b, $c, $dst"), []>; 200} 201 202//===----------------------------------------------------------------------===// 203// Instructions 204//===----------------------------------------------------------------------===// 205 206// Pseudo instructions. 207class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern> 208 : InstSP<outs, ins, asmstr, pattern>; 209 210let Defs = [O6], Uses = [O6] in { 211def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt), 212 "!ADJCALLSTACKDOWN $amt", 213 [(callseq_start timm:$amt)]>; 214def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2), 215 "!ADJCALLSTACKUP $amt1", 216 [(callseq_end timm:$amt1, timm:$amt2)]>; 217} 218 219// FpMOVD/FpNEGD/FpABSD - These are lowered to single-precision ops by the 220// fpmover pass. 221let Predicates = [HasNoV9] in { // Only emit these in V8 mode. 222 def FpMOVD : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$src), 223 "!FpMOVD $src, $dst", []>; 224 def FpNEGD : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$src), 225 "!FpNEGD $src, $dst", 226 [(set DFPRegs:$dst, (fneg DFPRegs:$src))]>; 227 def FpABSD : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$src), 228 "!FpABSD $src, $dst", 229 [(set DFPRegs:$dst, (fabs DFPRegs:$src))]>; 230} 231 232// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded by the 233// scheduler into a branch sequence. This has to handle all permutations of 234// selection between i32/f32/f64 on ICC and FCC. 235let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler. 236 def SELECT_CC_Int_ICC 237 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond), 238 "; SELECT_CC_Int_ICC PSEUDO!", 239 [(set IntRegs:$dst, (SPselecticc IntRegs:$T, IntRegs:$F, 240 imm:$Cond))]>; 241 def SELECT_CC_Int_FCC 242 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond), 243 "; SELECT_CC_Int_FCC PSEUDO!", 244 [(set IntRegs:$dst, (SPselectfcc IntRegs:$T, IntRegs:$F, 245 imm:$Cond))]>; 246 def SELECT_CC_FP_ICC 247 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, i32imm:$Cond), 248 "; SELECT_CC_FP_ICC PSEUDO!", 249 [(set FPRegs:$dst, (SPselecticc FPRegs:$T, FPRegs:$F, 250 imm:$Cond))]>; 251 def SELECT_CC_FP_FCC 252 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, i32imm:$Cond), 253 "; SELECT_CC_FP_FCC PSEUDO!", 254 [(set FPRegs:$dst, (SPselectfcc FPRegs:$T, FPRegs:$F, 255 imm:$Cond))]>; 256 def SELECT_CC_DFP_ICC 257 : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, i32imm:$Cond), 258 "; SELECT_CC_DFP_ICC PSEUDO!", 259 [(set DFPRegs:$dst, (SPselecticc DFPRegs:$T, DFPRegs:$F, 260 imm:$Cond))]>; 261 def SELECT_CC_DFP_FCC 262 : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, i32imm:$Cond), 263 "; SELECT_CC_DFP_FCC PSEUDO!", 264 [(set DFPRegs:$dst, (SPselectfcc DFPRegs:$T, DFPRegs:$F, 265 imm:$Cond))]>; 266} 267 268 269// Section A.3 - Synthetic Instructions, p. 85 270// special cases of JMPL: 271let isReturn = 1, isTerminator = 1, hasDelaySlot = 1 in { 272 let rd = O7.Num, rs1 = G0.Num, simm13 = 8 in 273 def RETL: F3_2<2, 0b111000, (outs), (ins), "retl", [(retflag)]>; 274} 275 276// Section B.1 - Load Integer Instructions, p. 90 277def LDSBrr : F3_1<3, 0b001001, 278 (outs IntRegs:$dst), (ins MEMrr:$addr), 279 "ldsb [$addr], $dst", 280 [(set IntRegs:$dst, (sextloadi8 ADDRrr:$addr))]>; 281def LDSBri : F3_2<3, 0b001001, 282 (outs IntRegs:$dst), (ins MEMri:$addr), 283 "ldsb [$addr], $dst", 284 [(set IntRegs:$dst, (sextloadi8 ADDRri:$addr))]>; 285def LDSHrr : F3_1<3, 0b001010, 286 (outs IntRegs:$dst), (ins MEMrr:$addr), 287 "ldsh [$addr], $dst", 288 [(set IntRegs:$dst, (sextloadi16 ADDRrr:$addr))]>; 289def LDSHri : F3_2<3, 0b001010, 290 (outs IntRegs:$dst), (ins MEMri:$addr), 291 "ldsh [$addr], $dst", 292 [(set IntRegs:$dst, (sextloadi16 ADDRri:$addr))]>; 293def LDUBrr : F3_1<3, 0b000001, 294 (outs IntRegs:$dst), (ins MEMrr:$addr), 295 "ldub [$addr], $dst", 296 [(set IntRegs:$dst, (zextloadi8 ADDRrr:$addr))]>; 297def LDUBri : F3_2<3, 0b000001, 298 (outs IntRegs:$dst), (ins MEMri:$addr), 299 "ldub [$addr], $dst", 300 [(set IntRegs:$dst, (zextloadi8 ADDRri:$addr))]>; 301def LDUHrr : F3_1<3, 0b000010, 302 (outs IntRegs:$dst), (ins MEMrr:$addr), 303 "lduh [$addr], $dst", 304 [(set IntRegs:$dst, (zextloadi16 ADDRrr:$addr))]>; 305def LDUHri : F3_2<3, 0b000010, 306 (outs IntRegs:$dst), (ins MEMri:$addr), 307 "lduh [$addr], $dst", 308 [(set IntRegs:$dst, (zextloadi16 ADDRri:$addr))]>; 309def LDrr : F3_1<3, 0b000000, 310 (outs IntRegs:$dst), (ins MEMrr:$addr), 311 "ld [$addr], $dst", 312 [(set IntRegs:$dst, (load ADDRrr:$addr))]>; 313def LDri : F3_2<3, 0b000000, 314 (outs IntRegs:$dst), (ins MEMri:$addr), 315 "ld [$addr], $dst", 316 [(set IntRegs:$dst, (load ADDRri:$addr))]>; 317 318// Section B.2 - Load Floating-point Instructions, p. 92 319def LDFrr : F3_1<3, 0b100000, 320 (outs FPRegs:$dst), (ins MEMrr:$addr), 321 "ld [$addr], $dst", 322 [(set FPRegs:$dst, (load ADDRrr:$addr))]>; 323def LDFri : F3_2<3, 0b100000, 324 (outs FPRegs:$dst), (ins MEMri:$addr), 325 "ld [$addr], $dst", 326 [(set FPRegs:$dst, (load ADDRri:$addr))]>; 327def LDDFrr : F3_1<3, 0b100011, 328 (outs DFPRegs:$dst), (ins MEMrr:$addr), 329 "ldd [$addr], $dst", 330 [(set DFPRegs:$dst, (load ADDRrr:$addr))]>; 331def LDDFri : F3_2<3, 0b100011, 332 (outs DFPRegs:$dst), (ins MEMri:$addr), 333 "ldd [$addr], $dst", 334 [(set DFPRegs:$dst, (load ADDRri:$addr))]>; 335 336// Section B.4 - Store Integer Instructions, p. 95 337def STBrr : F3_1<3, 0b000101, 338 (outs), (ins MEMrr:$addr, IntRegs:$src), 339 "stb $src, [$addr]", 340 [(truncstorei8 IntRegs:$src, ADDRrr:$addr)]>; 341def STBri : F3_2<3, 0b000101, 342 (outs), (ins MEMri:$addr, IntRegs:$src), 343 "stb $src, [$addr]", 344 [(truncstorei8 IntRegs:$src, ADDRri:$addr)]>; 345def STHrr : F3_1<3, 0b000110, 346 (outs), (ins MEMrr:$addr, IntRegs:$src), 347 "sth $src, [$addr]", 348 [(truncstorei16 IntRegs:$src, ADDRrr:$addr)]>; 349def STHri : F3_2<3, 0b000110, 350 (outs), (ins MEMri:$addr, IntRegs:$src), 351 "sth $src, [$addr]", 352 [(truncstorei16 IntRegs:$src, ADDRri:$addr)]>; 353def STrr : F3_1<3, 0b000100, 354 (outs), (ins MEMrr:$addr, IntRegs:$src), 355 "st $src, [$addr]", 356 [(store IntRegs:$src, ADDRrr:$addr)]>; 357def STri : F3_2<3, 0b000100, 358 (outs), (ins MEMri:$addr, IntRegs:$src), 359 "st $src, [$addr]", 360 [(store IntRegs:$src, ADDRri:$addr)]>; 361 362// Section B.5 - Store Floating-point Instructions, p. 97 363def STFrr : F3_1<3, 0b100100, 364 (outs), (ins MEMrr:$addr, FPRegs:$src), 365 "st $src, [$addr]", 366 [(store FPRegs:$src, ADDRrr:$addr)]>; 367def STFri : F3_2<3, 0b100100, 368 (outs), (ins MEMri:$addr, FPRegs:$src), 369 "st $src, [$addr]", 370 [(store FPRegs:$src, ADDRri:$addr)]>; 371def STDFrr : F3_1<3, 0b100111, 372 (outs), (ins MEMrr:$addr, DFPRegs:$src), 373 "std $src, [$addr]", 374 [(store DFPRegs:$src, ADDRrr:$addr)]>; 375def STDFri : F3_2<3, 0b100111, 376 (outs), (ins MEMri:$addr, DFPRegs:$src), 377 "std $src, [$addr]", 378 [(store DFPRegs:$src, ADDRri:$addr)]>; 379 380// Section B.9 - SETHI Instruction, p. 104 381def SETHIi: F2_1<0b100, 382 (outs IntRegs:$dst), (ins i32imm:$src), 383 "sethi $src, $dst", 384 [(set IntRegs:$dst, SETHIimm:$src)]>; 385 386// Section B.10 - NOP Instruction, p. 105 387// (It's a special case of SETHI) 388let rd = 0, imm22 = 0 in 389 def NOP : F2_1<0b100, (outs), (ins), "nop", []>; 390 391// Section B.11 - Logical Instructions, p. 106 392defm AND : F3_12<"and", 0b000001, and>; 393 394def ANDNrr : F3_1<2, 0b000101, 395 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c), 396 "andn $b, $c, $dst", 397 [(set IntRegs:$dst, (and IntRegs:$b, (not IntRegs:$c)))]>; 398def ANDNri : F3_2<2, 0b000101, 399 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c), 400 "andn $b, $c, $dst", []>; 401 402defm OR : F3_12<"or", 0b000010, or>; 403 404def ORNrr : F3_1<2, 0b000110, 405 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c), 406 "orn $b, $c, $dst", 407 [(set IntRegs:$dst, (or IntRegs:$b, (not IntRegs:$c)))]>; 408def ORNri : F3_2<2, 0b000110, 409 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c), 410 "orn $b, $c, $dst", []>; 411defm XOR : F3_12<"xor", 0b000011, xor>; 412 413def XNORrr : F3_1<2, 0b000111, 414 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c), 415 "xnor $b, $c, $dst", 416 [(set IntRegs:$dst, (not (xor IntRegs:$b, IntRegs:$c)))]>; 417def XNORri : F3_2<2, 0b000111, 418 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c), 419 "xnor $b, $c, $dst", []>; 420 421// Section B.12 - Shift Instructions, p. 107 422defm SLL : F3_12<"sll", 0b100101, shl>; 423defm SRL : F3_12<"srl", 0b100110, srl>; 424defm SRA : F3_12<"sra", 0b100111, sra>; 425 426// Section B.13 - Add Instructions, p. 108 427defm ADD : F3_12<"add", 0b000000, add>; 428 429// "LEA" forms of add (patterns to make tblgen happy) 430def LEA_ADDri : F3_2<2, 0b000000, 431 (outs IntRegs:$dst), (ins MEMri:$addr), 432 "add ${addr:arith}, $dst", 433 [(set IntRegs:$dst, ADDRri:$addr)]>; 434 435defm ADDCC : F3_12<"addcc", 0b010000, addc>; 436defm ADDX : F3_12<"addx", 0b001000, adde>; 437 438// Section B.15 - Subtract Instructions, p. 110 439defm SUB : F3_12 <"sub" , 0b000100, sub>; 440defm SUBX : F3_12 <"subx" , 0b001100, sube>; 441defm SUBCC : F3_12 <"subcc", 0b010100, SPcmpicc>; 442 443def SUBXCCrr: F3_1<2, 0b011100, 444 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c), 445 "subxcc $b, $c, $dst", []>; 446 447// Section B.18 - Multiply Instructions, p. 113 448defm UMUL : F3_12np<"umul", 0b001010>; 449defm SMUL : F3_12 <"smul", 0b001011, mul>; 450 451 452// Section B.19 - Divide Instructions, p. 115 453defm UDIV : F3_12np<"udiv", 0b001110>; 454defm SDIV : F3_12np<"sdiv", 0b001111>; 455 456// Section B.20 - SAVE and RESTORE, p. 117 457defm SAVE : F3_12np<"save" , 0b111100>; 458defm RESTORE : F3_12np<"restore", 0b111101>; 459 460// Section B.21 - Branch on Integer Condition Codes Instructions, p. 119 461 462// conditional branch class: 463class BranchSP<bits<4> cc, dag ins, string asmstr, list<dag> pattern> 464 : F2_2<cc, 0b010, (outs), ins, asmstr, pattern> { 465 let isBranch = 1; 466 let isTerminator = 1; 467 let hasDelaySlot = 1; 468} 469 470let isBarrier = 1 in 471 def BA : BranchSP<0b1000, (ins brtarget:$dst), 472 "ba $dst", 473 [(br bb:$dst)]>; 474 475// FIXME: the encoding for the JIT should look at the condition field. 476def BCOND : BranchSP<0, (ins brtarget:$dst, CCOp:$cc), 477 "b$cc $dst", 478 [(SPbricc bb:$dst, imm:$cc)]>; 479 480 481// Section B.22 - Branch on Floating-point Condition Codes Instructions, p. 121 482 483// floating-point conditional branch class: 484class FPBranchSP<bits<4> cc, dag ins, string asmstr, list<dag> pattern> 485 : F2_2<cc, 0b110, (outs), ins, asmstr, pattern> { 486 let isBranch = 1; 487 let isTerminator = 1; 488 let hasDelaySlot = 1; 489} 490 491// FIXME: the encoding for the JIT should look at the condition field. 492def FBCOND : FPBranchSP<0, (ins brtarget:$dst, CCOp:$cc), 493 "fb$cc $dst", 494 [(SPbrfcc bb:$dst, imm:$cc)]>; 495 496 497// Section B.24 - Call and Link Instruction, p. 125 498// This is the only Format 1 instruction 499let Uses = [O0, O1, O2, O3, O4, O5], 500 hasDelaySlot = 1, isCall = 1, 501 Defs = [O0, O1, O2, O3, O4, O5, O7, G1, G2, G3, G4, G5, G6, G7, 502 D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15] in { 503 def CALL : InstSP<(outs), (ins calltarget:$dst), 504 "call $dst", []> { 505 bits<30> disp; 506 let op = 1; 507 let Inst{29-0} = disp; 508 } 509 510 // indirect calls 511 def JMPLrr : F3_1<2, 0b111000, 512 (outs), (ins MEMrr:$ptr), 513 "call $ptr", 514 [(call ADDRrr:$ptr)]>; 515 def JMPLri : F3_2<2, 0b111000, 516 (outs), (ins MEMri:$ptr), 517 "call $ptr", 518 [(call ADDRri:$ptr)]>; 519} 520 521// Section B.28 - Read State Register Instructions 522def RDY : F3_1<2, 0b101000, 523 (outs IntRegs:$dst), (ins), 524 "rd %y, $dst", []>; 525 526// Section B.29 - Write State Register Instructions 527def WRYrr : F3_1<2, 0b110000, 528 (outs), (ins IntRegs:$b, IntRegs:$c), 529 "wr $b, $c, %y", []>; 530def WRYri : F3_2<2, 0b110000, 531 (outs), (ins IntRegs:$b, i32imm:$c), 532 "wr $b, $c, %y", []>; 533 534// Convert Integer to Floating-point Instructions, p. 141 535def FITOS : F3_3<2, 0b110100, 0b011000100, 536 (outs FPRegs:$dst), (ins FPRegs:$src), 537 "fitos $src, $dst", 538 [(set FPRegs:$dst, (SPitof FPRegs:$src))]>; 539def FITOD : F3_3<2, 0b110100, 0b011001000, 540 (outs DFPRegs:$dst), (ins FPRegs:$src), 541 "fitod $src, $dst", 542 [(set DFPRegs:$dst, (SPitof FPRegs:$src))]>; 543 544// Convert Floating-point to Integer Instructions, p. 142 545def FSTOI : F3_3<2, 0b110100, 0b011010001, 546 (outs FPRegs:$dst), (ins FPRegs:$src), 547 "fstoi $src, $dst", 548 [(set FPRegs:$dst, (SPftoi FPRegs:$src))]>; 549def FDTOI : F3_3<2, 0b110100, 0b011010010, 550 (outs FPRegs:$dst), (ins DFPRegs:$src), 551 "fdtoi $src, $dst", 552 [(set FPRegs:$dst, (SPftoi DFPRegs:$src))]>; 553 554// Convert between Floating-point Formats Instructions, p. 143 555def FSTOD : F3_3<2, 0b110100, 0b011001001, 556 (outs DFPRegs:$dst), (ins FPRegs:$src), 557 "fstod $src, $dst", 558 [(set DFPRegs:$dst, (fextend FPRegs:$src))]>; 559def FDTOS : F3_3<2, 0b110100, 0b011000110, 560 (outs FPRegs:$dst), (ins DFPRegs:$src), 561 "fdtos $src, $dst", 562 [(set FPRegs:$dst, (fround DFPRegs:$src))]>; 563 564// Floating-point Move Instructions, p. 144 565def FMOVS : F3_3<2, 0b110100, 0b000000001, 566 (outs FPRegs:$dst), (ins FPRegs:$src), 567 "fmovs $src, $dst", []>; 568def FNEGS : F3_3<2, 0b110100, 0b000000101, 569 (outs FPRegs:$dst), (ins FPRegs:$src), 570 "fnegs $src, $dst", 571 [(set FPRegs:$dst, (fneg FPRegs:$src))]>; 572def FABSS : F3_3<2, 0b110100, 0b000001001, 573 (outs FPRegs:$dst), (ins FPRegs:$src), 574 "fabss $src, $dst", 575 [(set FPRegs:$dst, (fabs FPRegs:$src))]>; 576 577 578// Floating-point Square Root Instructions, p.145 579def FSQRTS : F3_3<2, 0b110100, 0b000101001, 580 (outs FPRegs:$dst), (ins FPRegs:$src), 581 "fsqrts $src, $dst", 582 [(set FPRegs:$dst, (fsqrt FPRegs:$src))]>; 583def FSQRTD : F3_3<2, 0b110100, 0b000101010, 584 (outs DFPRegs:$dst), (ins DFPRegs:$src), 585 "fsqrtd $src, $dst", 586 [(set DFPRegs:$dst, (fsqrt DFPRegs:$src))]>; 587 588 589 590// Floating-point Add and Subtract Instructions, p. 146 591def FADDS : F3_3<2, 0b110100, 0b001000001, 592 (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2), 593 "fadds $src1, $src2, $dst", 594 [(set FPRegs:$dst, (fadd FPRegs:$src1, FPRegs:$src2))]>; 595def FADDD : F3_3<2, 0b110100, 0b001000010, 596 (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2), 597 "faddd $src1, $src2, $dst", 598 [(set DFPRegs:$dst, (fadd DFPRegs:$src1, DFPRegs:$src2))]>; 599def FSUBS : F3_3<2, 0b110100, 0b001000101, 600 (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2), 601 "fsubs $src1, $src2, $dst", 602 [(set FPRegs:$dst, (fsub FPRegs:$src1, FPRegs:$src2))]>; 603def FSUBD : F3_3<2, 0b110100, 0b001000110, 604 (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2), 605 "fsubd $src1, $src2, $dst", 606 [(set DFPRegs:$dst, (fsub DFPRegs:$src1, DFPRegs:$src2))]>; 607 608// Floating-point Multiply and Divide Instructions, p. 147 609def FMULS : F3_3<2, 0b110100, 0b001001001, 610 (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2), 611 "fmuls $src1, $src2, $dst", 612 [(set FPRegs:$dst, (fmul FPRegs:$src1, FPRegs:$src2))]>; 613def FMULD : F3_3<2, 0b110100, 0b001001010, 614 (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2), 615 "fmuld $src1, $src2, $dst", 616 [(set DFPRegs:$dst, (fmul DFPRegs:$src1, DFPRegs:$src2))]>; 617def FSMULD : F3_3<2, 0b110100, 0b001101001, 618 (outs DFPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2), 619 "fsmuld $src1, $src2, $dst", 620 [(set DFPRegs:$dst, (fmul (fextend FPRegs:$src1), 621 (fextend FPRegs:$src2)))]>; 622def FDIVS : F3_3<2, 0b110100, 0b001001101, 623 (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2), 624 "fdivs $src1, $src2, $dst", 625 [(set FPRegs:$dst, (fdiv FPRegs:$src1, FPRegs:$src2))]>; 626def FDIVD : F3_3<2, 0b110100, 0b001001110, 627 (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2), 628 "fdivd $src1, $src2, $dst", 629 [(set DFPRegs:$dst, (fdiv DFPRegs:$src1, DFPRegs:$src2))]>; 630 631// Floating-point Compare Instructions, p. 148 632// Note: the 2nd template arg is different for these guys. 633// Note 2: the result of a FCMP is not available until the 2nd cycle 634// after the instr is retired, but there is no interlock. This behavior 635// is modelled with a forced noop after the instruction. 636def FCMPS : F3_3<2, 0b110101, 0b001010001, 637 (outs), (ins FPRegs:$src1, FPRegs:$src2), 638 "fcmps $src1, $src2\n\tnop", 639 [(SPcmpfcc FPRegs:$src1, FPRegs:$src2)]>; 640def FCMPD : F3_3<2, 0b110101, 0b001010010, 641 (outs), (ins DFPRegs:$src1, DFPRegs:$src2), 642 "fcmpd $src1, $src2\n\tnop", 643 [(SPcmpfcc DFPRegs:$src1, DFPRegs:$src2)]>; 644 645 646//===----------------------------------------------------------------------===// 647// V9 Instructions 648//===----------------------------------------------------------------------===// 649 650// V9 Conditional Moves. 651let Predicates = [HasV9], isTwoAddress = 1 in { 652 // Move Integer Register on Condition (MOVcc) p. 194 of the V9 manual. 653 // FIXME: Add instruction encodings for the JIT some day. 654 def MOVICCrr 655 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, CCOp:$cc), 656 "mov$cc %icc, $F, $dst", 657 [(set IntRegs:$dst, 658 (SPselecticc IntRegs:$F, IntRegs:$T, imm:$cc))]>; 659 def MOVICCri 660 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, i32imm:$F, CCOp:$cc), 661 "mov$cc %icc, $F, $dst", 662 [(set IntRegs:$dst, 663 (SPselecticc simm11:$F, IntRegs:$T, imm:$cc))]>; 664 665 def MOVFCCrr 666 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, CCOp:$cc), 667 "mov$cc %fcc0, $F, $dst", 668 [(set IntRegs:$dst, 669 (SPselectfcc IntRegs:$F, IntRegs:$T, imm:$cc))]>; 670 def MOVFCCri 671 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, i32imm:$F, CCOp:$cc), 672 "mov$cc %fcc0, $F, $dst", 673 [(set IntRegs:$dst, 674 (SPselectfcc simm11:$F, IntRegs:$T, imm:$cc))]>; 675 676 def FMOVS_ICC 677 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, CCOp:$cc), 678 "fmovs$cc %icc, $F, $dst", 679 [(set FPRegs:$dst, 680 (SPselecticc FPRegs:$F, FPRegs:$T, imm:$cc))]>; 681 def FMOVD_ICC 682 : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, CCOp:$cc), 683 "fmovd$cc %icc, $F, $dst", 684 [(set DFPRegs:$dst, 685 (SPselecticc DFPRegs:$F, DFPRegs:$T, imm:$cc))]>; 686 def FMOVS_FCC 687 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, CCOp:$cc), 688 "fmovs$cc %fcc0, $F, $dst", 689 [(set FPRegs:$dst, 690 (SPselectfcc FPRegs:$F, FPRegs:$T, imm:$cc))]>; 691 def FMOVD_FCC 692 : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, CCOp:$cc), 693 "fmovd$cc %fcc0, $F, $dst", 694 [(set DFPRegs:$dst, 695 (SPselectfcc DFPRegs:$F, DFPRegs:$T, imm:$cc))]>; 696 697} 698 699// Floating-Point Move Instructions, p. 164 of the V9 manual. 700let Predicates = [HasV9] in { 701 def FMOVD : F3_3<2, 0b110100, 0b000000010, 702 (outs DFPRegs:$dst), (ins DFPRegs:$src), 703 "fmovd $src, $dst", []>; 704 def FNEGD : F3_3<2, 0b110100, 0b000000110, 705 (outs DFPRegs:$dst), (ins DFPRegs:$src), 706 "fnegd $src, $dst", 707 [(set DFPRegs:$dst, (fneg DFPRegs:$src))]>; 708 def FABSD : F3_3<2, 0b110100, 0b000001010, 709 (outs DFPRegs:$dst), (ins DFPRegs:$src), 710 "fabsd $src, $dst", 711 [(set DFPRegs:$dst, (fabs DFPRegs:$src))]>; 712} 713 714// POPCrr - This does a ctpop of a 64-bit register. As such, we have to clear 715// the top 32-bits before using it. To do this clearing, we use a SLLri X,0. 716def POPCrr : F3_1<2, 0b101110, 717 (outs IntRegs:$dst), (ins IntRegs:$src), 718 "popc $src, $dst", []>, Requires<[HasV9]>; 719def : Pat<(ctpop IntRegs:$src), 720 (POPCrr (SLLri IntRegs:$src, 0))>; 721 722//===----------------------------------------------------------------------===// 723// Non-Instruction Patterns 724//===----------------------------------------------------------------------===// 725 726// Small immediates. 727def : Pat<(i32 simm13:$val), 728 (ORri G0, imm:$val)>; 729// Arbitrary immediates. 730def : Pat<(i32 imm:$val), 731 (ORri (SETHIi (HI22 imm:$val)), (LO10 imm:$val))>; 732 733// subc 734def : Pat<(subc IntRegs:$b, IntRegs:$c), 735 (SUBCCrr IntRegs:$b, IntRegs:$c)>; 736def : Pat<(subc IntRegs:$b, simm13:$val), 737 (SUBCCri IntRegs:$b, imm:$val)>; 738 739// Global addresses, constant pool entries 740def : Pat<(SPhi tglobaladdr:$in), (SETHIi tglobaladdr:$in)>; 741def : Pat<(SPlo tglobaladdr:$in), (ORri G0, tglobaladdr:$in)>; 742def : Pat<(SPhi tconstpool:$in), (SETHIi tconstpool:$in)>; 743def : Pat<(SPlo tconstpool:$in), (ORri G0, tconstpool:$in)>; 744 745// Add reg, lo. This is used when taking the addr of a global/constpool entry. 746def : Pat<(add IntRegs:$r, (SPlo tglobaladdr:$in)), 747 (ADDri IntRegs:$r, tglobaladdr:$in)>; 748def : Pat<(add IntRegs:$r, (SPlo tconstpool:$in)), 749 (ADDri IntRegs:$r, tconstpool:$in)>; 750 751// Calls: 752def : Pat<(call tglobaladdr:$dst), 753 (CALL tglobaladdr:$dst)>; 754def : Pat<(call texternalsym:$dst), 755 (CALL texternalsym:$dst)>; 756 757// Map integer extload's to zextloads. 758def : Pat<(i32 (extloadi1 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>; 759def : Pat<(i32 (extloadi1 ADDRri:$src)), (LDUBri ADDRri:$src)>; 760def : Pat<(i32 (extloadi8 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>; 761def : Pat<(i32 (extloadi8 ADDRri:$src)), (LDUBri ADDRri:$src)>; 762def : Pat<(i32 (extloadi16 ADDRrr:$src)), (LDUHrr ADDRrr:$src)>; 763def : Pat<(i32 (extloadi16 ADDRri:$src)), (LDUHri ADDRri:$src)>; 764 765// zextload bool -> zextload byte 766def : Pat<(i32 (zextloadi1 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>; 767def : Pat<(i32 (zextloadi1 ADDRri:$src)), (LDUBri ADDRri:$src)>; 768