SparcInstrInfo.td revision ef596e1a80a9790efbc905c57b4e06ba6addb95a
1//===-- SparcInstrInfo.td - Target Description for Sparc Target -----------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the Sparc instructions in TableGen format. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// Instruction format superclass 16//===----------------------------------------------------------------------===// 17 18include "SparcInstrFormats.td" 19 20//===----------------------------------------------------------------------===// 21// Feature predicates. 22//===----------------------------------------------------------------------===// 23 24// True when generating 32-bit code. 25def Is32Bit : Predicate<"!Subtarget.is64Bit()">; 26 27// True when generating 64-bit code. This also implies HasV9. 28def Is64Bit : Predicate<"Subtarget.is64Bit()">; 29 30// HasV9 - This predicate is true when the target processor supports V9 31// instructions. Note that the machine may be running in 32-bit mode. 32def HasV9 : Predicate<"Subtarget.isV9()">; 33 34// HasNoV9 - This predicate is true when the target doesn't have V9 35// instructions. Use of this is just a hack for the isel not having proper 36// costs for V8 instructions that are more expensive than their V9 ones. 37def HasNoV9 : Predicate<"!Subtarget.isV9()">; 38 39// HasVIS - This is true when the target processor has VIS extensions. 40def HasVIS : Predicate<"Subtarget.isVIS()">; 41 42// UseDeprecatedInsts - This predicate is true when the target processor is a 43// V8, or when it is V9 but the V8 deprecated instructions are efficient enough 44// to use when appropriate. In either of these cases, the instruction selector 45// will pick deprecated instructions. 46def UseDeprecatedInsts : Predicate<"Subtarget.useDeprecatedV8Instructions()">; 47 48//===----------------------------------------------------------------------===// 49// Instruction Pattern Stuff 50//===----------------------------------------------------------------------===// 51 52def simm11 : PatLeaf<(imm), [{ return isInt<11>(N->getSExtValue()); }]>; 53 54def simm13 : PatLeaf<(imm), [{ return isInt<13>(N->getSExtValue()); }]>; 55 56def LO10 : SDNodeXForm<imm, [{ 57 return CurDAG->getTargetConstant((unsigned)N->getZExtValue() & 1023, 58 MVT::i32); 59}]>; 60 61def HI22 : SDNodeXForm<imm, [{ 62 // Transformation function: shift the immediate value down into the low bits. 63 return CurDAG->getTargetConstant((unsigned)N->getZExtValue() >> 10, MVT::i32); 64}]>; 65 66def SETHIimm : PatLeaf<(imm), [{ 67 return (((unsigned)N->getZExtValue() >> 10) << 10) == 68 (unsigned)N->getZExtValue(); 69}], HI22>; 70 71// Addressing modes. 72def ADDRrr : ComplexPattern<iPTR, 2, "SelectADDRrr", [], []>; 73def ADDRri : ComplexPattern<iPTR, 2, "SelectADDRri", [frameindex], []>; 74 75// Address operands 76def MEMrr : Operand<iPTR> { 77 let PrintMethod = "printMemOperand"; 78 let MIOperandInfo = (ops ptr_rc, ptr_rc); 79} 80def MEMri : Operand<iPTR> { 81 let PrintMethod = "printMemOperand"; 82 let MIOperandInfo = (ops ptr_rc, i32imm); 83} 84 85// Branch targets have OtherVT type. 86def brtarget : Operand<OtherVT>; 87def calltarget : Operand<i32>; 88 89// Operand for printing out a condition code. 90let PrintMethod = "printCCOperand" in 91 def CCOp : Operand<i32>; 92 93def SDTSPcmpfcc : 94SDTypeProfile<0, 2, [SDTCisFP<0>, SDTCisSameAs<0, 1>]>; 95def SDTSPbrcc : 96SDTypeProfile<0, 2, [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>; 97def SDTSPselectcc : 98SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>]>; 99def SDTSPFTOI : 100SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisFP<1>]>; 101def SDTSPITOF : 102SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f32>]>; 103 104def SPcmpicc : SDNode<"SPISD::CMPICC", SDTIntBinOp, [SDNPOutGlue]>; 105def SPcmpfcc : SDNode<"SPISD::CMPFCC", SDTSPcmpfcc, [SDNPOutGlue]>; 106def SPbricc : SDNode<"SPISD::BRICC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>; 107def SPbrxcc : SDNode<"SPISD::BRXCC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>; 108def SPbrfcc : SDNode<"SPISD::BRFCC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>; 109 110def SPhi : SDNode<"SPISD::Hi", SDTIntUnaryOp>; 111def SPlo : SDNode<"SPISD::Lo", SDTIntUnaryOp>; 112 113def SPftoi : SDNode<"SPISD::FTOI", SDTSPFTOI>; 114def SPitof : SDNode<"SPISD::ITOF", SDTSPITOF>; 115 116def SPselecticc : SDNode<"SPISD::SELECT_ICC", SDTSPselectcc, [SDNPInGlue]>; 117def SPselectxcc : SDNode<"SPISD::SELECT_XCC", SDTSPselectcc, [SDNPInGlue]>; 118def SPselectfcc : SDNode<"SPISD::SELECT_FCC", SDTSPselectcc, [SDNPInGlue]>; 119 120// These are target-independent nodes, but have target-specific formats. 121def SDT_SPCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>; 122def SDT_SPCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, 123 SDTCisVT<1, i32> ]>; 124 125def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_SPCallSeqStart, 126 [SDNPHasChain, SDNPOutGlue]>; 127def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_SPCallSeqEnd, 128 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 129 130def SDT_SPCall : SDTypeProfile<0, -1, [SDTCisVT<0, i32>]>; 131def call : SDNode<"SPISD::CALL", SDT_SPCall, 132 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 133 SDNPVariadic]>; 134 135def SDT_SPRet : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>; 136def retflag : SDNode<"SPISD::RET_FLAG", SDT_SPRet, 137 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 138 139def flushw : SDNode<"SPISD::FLUSHW", SDTNone, 140 [SDNPHasChain, SDNPSideEffect, SDNPMayStore]>; 141 142def getPCX : Operand<i32> { 143 let PrintMethod = "printGetPCX"; 144} 145 146//===----------------------------------------------------------------------===// 147// SPARC Flag Conditions 148//===----------------------------------------------------------------------===// 149 150// Note that these values must be kept in sync with the CCOp::CondCode enum 151// values. 152class ICC_VAL<int N> : PatLeaf<(i32 N)>; 153def ICC_NE : ICC_VAL< 9>; // Not Equal 154def ICC_E : ICC_VAL< 1>; // Equal 155def ICC_G : ICC_VAL<10>; // Greater 156def ICC_LE : ICC_VAL< 2>; // Less or Equal 157def ICC_GE : ICC_VAL<11>; // Greater or Equal 158def ICC_L : ICC_VAL< 3>; // Less 159def ICC_GU : ICC_VAL<12>; // Greater Unsigned 160def ICC_LEU : ICC_VAL< 4>; // Less or Equal Unsigned 161def ICC_CC : ICC_VAL<13>; // Carry Clear/Great or Equal Unsigned 162def ICC_CS : ICC_VAL< 5>; // Carry Set/Less Unsigned 163def ICC_POS : ICC_VAL<14>; // Positive 164def ICC_NEG : ICC_VAL< 6>; // Negative 165def ICC_VC : ICC_VAL<15>; // Overflow Clear 166def ICC_VS : ICC_VAL< 7>; // Overflow Set 167 168class FCC_VAL<int N> : PatLeaf<(i32 N)>; 169def FCC_U : FCC_VAL<23>; // Unordered 170def FCC_G : FCC_VAL<22>; // Greater 171def FCC_UG : FCC_VAL<21>; // Unordered or Greater 172def FCC_L : FCC_VAL<20>; // Less 173def FCC_UL : FCC_VAL<19>; // Unordered or Less 174def FCC_LG : FCC_VAL<18>; // Less or Greater 175def FCC_NE : FCC_VAL<17>; // Not Equal 176def FCC_E : FCC_VAL<25>; // Equal 177def FCC_UE : FCC_VAL<24>; // Unordered or Equal 178def FCC_GE : FCC_VAL<25>; // Greater or Equal 179def FCC_UGE : FCC_VAL<26>; // Unordered or Greater or Equal 180def FCC_LE : FCC_VAL<27>; // Less or Equal 181def FCC_ULE : FCC_VAL<28>; // Unordered or Less or Equal 182def FCC_O : FCC_VAL<29>; // Ordered 183 184//===----------------------------------------------------------------------===// 185// Instruction Class Templates 186//===----------------------------------------------------------------------===// 187 188/// F3_12 multiclass - Define a normal F3_1/F3_2 pattern in one shot. 189multiclass F3_12<string OpcStr, bits<6> Op3Val, SDNode OpNode> { 190 def rr : F3_1<2, Op3Val, 191 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c), 192 !strconcat(OpcStr, " $b, $c, $dst"), 193 [(set i32:$dst, (OpNode i32:$b, i32:$c))]>; 194 def ri : F3_2<2, Op3Val, 195 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c), 196 !strconcat(OpcStr, " $b, $c, $dst"), 197 [(set i32:$dst, (OpNode i32:$b, (i32 simm13:$c)))]>; 198} 199 200/// F3_12np multiclass - Define a normal F3_1/F3_2 pattern in one shot, with no 201/// pattern. 202multiclass F3_12np<string OpcStr, bits<6> Op3Val> { 203 def rr : F3_1<2, Op3Val, 204 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c), 205 !strconcat(OpcStr, " $b, $c, $dst"), []>; 206 def ri : F3_2<2, Op3Val, 207 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c), 208 !strconcat(OpcStr, " $b, $c, $dst"), []>; 209} 210 211//===----------------------------------------------------------------------===// 212// Instructions 213//===----------------------------------------------------------------------===// 214 215// Pseudo instructions. 216class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern> 217 : InstSP<outs, ins, asmstr, pattern>; 218 219// GETPCX for PIC 220let Defs = [O7] in { 221 def GETPCX : Pseudo<(outs getPCX:$getpcseq), (ins), "$getpcseq", [] >; 222} 223 224let Defs = [O6], Uses = [O6] in { 225def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt), 226 "!ADJCALLSTACKDOWN $amt", 227 [(callseq_start timm:$amt)]>; 228def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2), 229 "!ADJCALLSTACKUP $amt1", 230 [(callseq_end timm:$amt1, timm:$amt2)]>; 231} 232 233let hasSideEffects = 1, mayStore = 1 in { 234 let rd = 0, rs1 = 0, rs2 = 0 in 235 def FLUSHW : F3_1<0b10, 0b101011, (outs), (ins), 236 "flushw", 237 [(flushw)]>, Requires<[HasV9]>; 238 let rd = 0, rs1 = 1, simm13 = 3 in 239 def TA3 : F3_2<0b10, 0b111010, (outs), (ins), 240 "ta 3", 241 [(flushw)]>; 242} 243 244def UNIMP : F2_1<0b000, (outs), (ins i32imm:$val), 245 "unimp $val", []>; 246 247// FpMOVD/FpNEGD/FpABSD - These are lowered to single-precision ops by the 248// fpmover pass. 249let Predicates = [HasNoV9] in { // Only emit these in V8 mode. 250 def FpMOVD : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$src), 251 "!FpMOVD $src, $dst", []>; 252 def FpNEGD : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$src), 253 "!FpNEGD $src, $dst", 254 [(set f64:$dst, (fneg f64:$src))]>; 255 def FpABSD : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$src), 256 "!FpABSD $src, $dst", 257 [(set f64:$dst, (fabs f64:$src))]>; 258} 259 260// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after 261// instruction selection into a branch sequence. This has to handle all 262// permutations of selection between i32/f32/f64 on ICC and FCC. 263 // Expanded after instruction selection. 264let Uses = [ICC], usesCustomInserter = 1 in { 265 def SELECT_CC_Int_ICC 266 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond), 267 "; SELECT_CC_Int_ICC PSEUDO!", 268 [(set i32:$dst, (SPselecticc i32:$T, i32:$F, imm:$Cond))]>; 269 def SELECT_CC_FP_ICC 270 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, i32imm:$Cond), 271 "; SELECT_CC_FP_ICC PSEUDO!", 272 [(set f32:$dst, (SPselecticc f32:$T, f32:$F, imm:$Cond))]>; 273 274 def SELECT_CC_DFP_ICC 275 : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, i32imm:$Cond), 276 "; SELECT_CC_DFP_ICC PSEUDO!", 277 [(set f64:$dst, (SPselecticc f64:$T, f64:$F, imm:$Cond))]>; 278} 279 280let usesCustomInserter = 1, Uses = [FCC] in { 281 282 def SELECT_CC_Int_FCC 283 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond), 284 "; SELECT_CC_Int_FCC PSEUDO!", 285 [(set i32:$dst, (SPselectfcc i32:$T, i32:$F, imm:$Cond))]>; 286 287 def SELECT_CC_FP_FCC 288 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, i32imm:$Cond), 289 "; SELECT_CC_FP_FCC PSEUDO!", 290 [(set f32:$dst, (SPselectfcc f32:$T, f32:$F, imm:$Cond))]>; 291 def SELECT_CC_DFP_FCC 292 : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, i32imm:$Cond), 293 "; SELECT_CC_DFP_FCC PSEUDO!", 294 [(set f64:$dst, (SPselectfcc f64:$T, f64:$F, imm:$Cond))]>; 295} 296 297 298// Section A.3 - Synthetic Instructions, p. 85 299// special cases of JMPL: 300let isReturn = 1, isTerminator = 1, hasDelaySlot = 1, isBarrier = 1 in { 301 let rd = O7.Num, rs1 = G0.Num in 302 def RETL: F3_2<2, 0b111000, (outs), (ins i32imm:$val), 303 "jmp %o7+$val", [(retflag simm13:$val)]>; 304 305 let rd = I7.Num, rs1 = G0.Num in 306 def RET: F3_2<2, 0b111000, (outs), (ins i32imm:$val), 307 "jmp %i7+$val", []>; 308} 309 310// Section B.1 - Load Integer Instructions, p. 90 311def LDSBrr : F3_1<3, 0b001001, 312 (outs IntRegs:$dst), (ins MEMrr:$addr), 313 "ldsb [$addr], $dst", 314 [(set i32:$dst, (sextloadi8 ADDRrr:$addr))]>; 315def LDSBri : F3_2<3, 0b001001, 316 (outs IntRegs:$dst), (ins MEMri:$addr), 317 "ldsb [$addr], $dst", 318 [(set i32:$dst, (sextloadi8 ADDRri:$addr))]>; 319def LDSHrr : F3_1<3, 0b001010, 320 (outs IntRegs:$dst), (ins MEMrr:$addr), 321 "ldsh [$addr], $dst", 322 [(set i32:$dst, (sextloadi16 ADDRrr:$addr))]>; 323def LDSHri : F3_2<3, 0b001010, 324 (outs IntRegs:$dst), (ins MEMri:$addr), 325 "ldsh [$addr], $dst", 326 [(set i32:$dst, (sextloadi16 ADDRri:$addr))]>; 327def LDUBrr : F3_1<3, 0b000001, 328 (outs IntRegs:$dst), (ins MEMrr:$addr), 329 "ldub [$addr], $dst", 330 [(set i32:$dst, (zextloadi8 ADDRrr:$addr))]>; 331def LDUBri : F3_2<3, 0b000001, 332 (outs IntRegs:$dst), (ins MEMri:$addr), 333 "ldub [$addr], $dst", 334 [(set i32:$dst, (zextloadi8 ADDRri:$addr))]>; 335def LDUHrr : F3_1<3, 0b000010, 336 (outs IntRegs:$dst), (ins MEMrr:$addr), 337 "lduh [$addr], $dst", 338 [(set i32:$dst, (zextloadi16 ADDRrr:$addr))]>; 339def LDUHri : F3_2<3, 0b000010, 340 (outs IntRegs:$dst), (ins MEMri:$addr), 341 "lduh [$addr], $dst", 342 [(set i32:$dst, (zextloadi16 ADDRri:$addr))]>; 343def LDrr : F3_1<3, 0b000000, 344 (outs IntRegs:$dst), (ins MEMrr:$addr), 345 "ld [$addr], $dst", 346 [(set i32:$dst, (load ADDRrr:$addr))]>; 347def LDri : F3_2<3, 0b000000, 348 (outs IntRegs:$dst), (ins MEMri:$addr), 349 "ld [$addr], $dst", 350 [(set i32:$dst, (load ADDRri:$addr))]>; 351 352// Section B.2 - Load Floating-point Instructions, p. 92 353def LDFrr : F3_1<3, 0b100000, 354 (outs FPRegs:$dst), (ins MEMrr:$addr), 355 "ld [$addr], $dst", 356 [(set f32:$dst, (load ADDRrr:$addr))]>; 357def LDFri : F3_2<3, 0b100000, 358 (outs FPRegs:$dst), (ins MEMri:$addr), 359 "ld [$addr], $dst", 360 [(set f32:$dst, (load ADDRri:$addr))]>; 361def LDDFrr : F3_1<3, 0b100011, 362 (outs DFPRegs:$dst), (ins MEMrr:$addr), 363 "ldd [$addr], $dst", 364 [(set f64:$dst, (load ADDRrr:$addr))]>; 365def LDDFri : F3_2<3, 0b100011, 366 (outs DFPRegs:$dst), (ins MEMri:$addr), 367 "ldd [$addr], $dst", 368 [(set f64:$dst, (load ADDRri:$addr))]>; 369 370// Section B.4 - Store Integer Instructions, p. 95 371def STBrr : F3_1<3, 0b000101, 372 (outs), (ins MEMrr:$addr, IntRegs:$src), 373 "stb $src, [$addr]", 374 [(truncstorei8 i32:$src, ADDRrr:$addr)]>; 375def STBri : F3_2<3, 0b000101, 376 (outs), (ins MEMri:$addr, IntRegs:$src), 377 "stb $src, [$addr]", 378 [(truncstorei8 i32:$src, ADDRri:$addr)]>; 379def STHrr : F3_1<3, 0b000110, 380 (outs), (ins MEMrr:$addr, IntRegs:$src), 381 "sth $src, [$addr]", 382 [(truncstorei16 i32:$src, ADDRrr:$addr)]>; 383def STHri : F3_2<3, 0b000110, 384 (outs), (ins MEMri:$addr, IntRegs:$src), 385 "sth $src, [$addr]", 386 [(truncstorei16 i32:$src, ADDRri:$addr)]>; 387def STrr : F3_1<3, 0b000100, 388 (outs), (ins MEMrr:$addr, IntRegs:$src), 389 "st $src, [$addr]", 390 [(store i32:$src, ADDRrr:$addr)]>; 391def STri : F3_2<3, 0b000100, 392 (outs), (ins MEMri:$addr, IntRegs:$src), 393 "st $src, [$addr]", 394 [(store i32:$src, ADDRri:$addr)]>; 395 396// Section B.5 - Store Floating-point Instructions, p. 97 397def STFrr : F3_1<3, 0b100100, 398 (outs), (ins MEMrr:$addr, FPRegs:$src), 399 "st $src, [$addr]", 400 [(store f32:$src, ADDRrr:$addr)]>; 401def STFri : F3_2<3, 0b100100, 402 (outs), (ins MEMri:$addr, FPRegs:$src), 403 "st $src, [$addr]", 404 [(store f32:$src, ADDRri:$addr)]>; 405def STDFrr : F3_1<3, 0b100111, 406 (outs), (ins MEMrr:$addr, DFPRegs:$src), 407 "std $src, [$addr]", 408 [(store f64:$src, ADDRrr:$addr)]>; 409def STDFri : F3_2<3, 0b100111, 410 (outs), (ins MEMri:$addr, DFPRegs:$src), 411 "std $src, [$addr]", 412 [(store f64:$src, ADDRri:$addr)]>; 413 414// Section B.9 - SETHI Instruction, p. 104 415def SETHIi: F2_1<0b100, 416 (outs IntRegs:$dst), (ins i32imm:$src), 417 "sethi $src, $dst", 418 [(set i32:$dst, SETHIimm:$src)]>; 419 420// Section B.10 - NOP Instruction, p. 105 421// (It's a special case of SETHI) 422let rd = 0, imm22 = 0 in 423 def NOP : F2_1<0b100, (outs), (ins), "nop", []>; 424 425// Section B.11 - Logical Instructions, p. 106 426defm AND : F3_12<"and", 0b000001, and>; 427 428def ANDNrr : F3_1<2, 0b000101, 429 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c), 430 "andn $b, $c, $dst", 431 [(set i32:$dst, (and i32:$b, (not i32:$c)))]>; 432def ANDNri : F3_2<2, 0b000101, 433 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c), 434 "andn $b, $c, $dst", []>; 435 436defm OR : F3_12<"or", 0b000010, or>; 437 438def ORNrr : F3_1<2, 0b000110, 439 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c), 440 "orn $b, $c, $dst", 441 [(set i32:$dst, (or i32:$b, (not i32:$c)))]>; 442def ORNri : F3_2<2, 0b000110, 443 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c), 444 "orn $b, $c, $dst", []>; 445defm XOR : F3_12<"xor", 0b000011, xor>; 446 447def XNORrr : F3_1<2, 0b000111, 448 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c), 449 "xnor $b, $c, $dst", 450 [(set i32:$dst, (not (xor i32:$b, i32:$c)))]>; 451def XNORri : F3_2<2, 0b000111, 452 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c), 453 "xnor $b, $c, $dst", []>; 454 455// Section B.12 - Shift Instructions, p. 107 456defm SLL : F3_12<"sll", 0b100101, shl>; 457defm SRL : F3_12<"srl", 0b100110, srl>; 458defm SRA : F3_12<"sra", 0b100111, sra>; 459 460// Section B.13 - Add Instructions, p. 108 461defm ADD : F3_12<"add", 0b000000, add>; 462 463// "LEA" forms of add (patterns to make tblgen happy) 464def LEA_ADDri : F3_2<2, 0b000000, 465 (outs IntRegs:$dst), (ins MEMri:$addr), 466 "add ${addr:arith}, $dst", 467 [(set i32:$dst, ADDRri:$addr)]>; 468 469let Defs = [ICC] in 470 defm ADDCC : F3_12<"addcc", 0b010000, addc>; 471 472let Uses = [ICC] in 473 defm ADDX : F3_12<"addx", 0b001000, adde>; 474 475// Section B.15 - Subtract Instructions, p. 110 476defm SUB : F3_12 <"sub" , 0b000100, sub>; 477let Uses = [ICC] in 478 defm SUBX : F3_12 <"subx" , 0b001100, sube>; 479 480let Defs = [ICC] in 481 defm SUBCC : F3_12 <"subcc", 0b010100, SPcmpicc>; 482 483let Uses = [ICC], Defs = [ICC] in 484 def SUBXCCrr: F3_1<2, 0b011100, 485 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c), 486 "subxcc $b, $c, $dst", []>; 487 488 489// Section B.18 - Multiply Instructions, p. 113 490let Defs = [Y] in { 491 defm UMUL : F3_12np<"umul", 0b001010>; 492 defm SMUL : F3_12 <"smul", 0b001011, mul>; 493} 494 495// Section B.19 - Divide Instructions, p. 115 496let Defs = [Y] in { 497 defm UDIV : F3_12np<"udiv", 0b001110>; 498 defm SDIV : F3_12np<"sdiv", 0b001111>; 499} 500 501// Section B.20 - SAVE and RESTORE, p. 117 502defm SAVE : F3_12np<"save" , 0b111100>; 503defm RESTORE : F3_12np<"restore", 0b111101>; 504 505// Section B.21 - Branch on Integer Condition Codes Instructions, p. 119 506 507// conditional branch class: 508class BranchSP<bits<4> cc, dag ins, string asmstr, list<dag> pattern> 509 : F2_2<cc, 0b010, (outs), ins, asmstr, pattern> { 510 let isBranch = 1; 511 let isTerminator = 1; 512 let hasDelaySlot = 1; 513} 514 515let isBarrier = 1 in 516 def BA : BranchSP<0b1000, (ins brtarget:$dst), 517 "ba $dst", 518 [(br bb:$dst)]>; 519 520// FIXME: the encoding for the JIT should look at the condition field. 521let Uses = [ICC] in 522 def BCOND : BranchSP<0, (ins brtarget:$dst, CCOp:$cc), 523 "b$cc $dst", 524 [(SPbricc bb:$dst, imm:$cc)]>; 525 526 527// Section B.22 - Branch on Floating-point Condition Codes Instructions, p. 121 528 529// floating-point conditional branch class: 530class FPBranchSP<bits<4> cc, dag ins, string asmstr, list<dag> pattern> 531 : F2_2<cc, 0b110, (outs), ins, asmstr, pattern> { 532 let isBranch = 1; 533 let isTerminator = 1; 534 let hasDelaySlot = 1; 535} 536 537// FIXME: the encoding for the JIT should look at the condition field. 538let Uses = [FCC] in 539 def FBCOND : FPBranchSP<0, (ins brtarget:$dst, CCOp:$cc), 540 "fb$cc $dst", 541 [(SPbrfcc bb:$dst, imm:$cc)]>; 542 543 544// Section B.24 - Call and Link Instruction, p. 125 545// This is the only Format 1 instruction 546let Uses = [O6], 547 hasDelaySlot = 1, isCall = 1, 548 Defs = [O0, O1, O2, O3, O4, O5, O7, G1, G2, G3, G4, G5, G6, G7, 549 D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15, 550 ICC, FCC, Y] in { 551 def CALL : InstSP<(outs), (ins calltarget:$dst, variable_ops), 552 "call $dst", []> { 553 bits<30> disp; 554 let op = 1; 555 let Inst{29-0} = disp; 556 } 557 558 // indirect calls 559 def JMPLrr : F3_1<2, 0b111000, 560 (outs), (ins MEMrr:$ptr, variable_ops), 561 "call $ptr", 562 [(call ADDRrr:$ptr)]>; 563 def JMPLri : F3_2<2, 0b111000, 564 (outs), (ins MEMri:$ptr, variable_ops), 565 "call $ptr", 566 [(call ADDRri:$ptr)]>; 567} 568 569// Section B.28 - Read State Register Instructions 570let Uses = [Y] in 571 def RDY : F3_1<2, 0b101000, 572 (outs IntRegs:$dst), (ins), 573 "rd %y, $dst", []>; 574 575// Section B.29 - Write State Register Instructions 576let Defs = [Y] in { 577 def WRYrr : F3_1<2, 0b110000, 578 (outs), (ins IntRegs:$b, IntRegs:$c), 579 "wr $b, $c, %y", []>; 580 def WRYri : F3_2<2, 0b110000, 581 (outs), (ins IntRegs:$b, i32imm:$c), 582 "wr $b, $c, %y", []>; 583} 584// Convert Integer to Floating-point Instructions, p. 141 585def FITOS : F3_3<2, 0b110100, 0b011000100, 586 (outs FPRegs:$dst), (ins FPRegs:$src), 587 "fitos $src, $dst", 588 [(set FPRegs:$dst, (SPitof FPRegs:$src))]>; 589def FITOD : F3_3<2, 0b110100, 0b011001000, 590 (outs DFPRegs:$dst), (ins FPRegs:$src), 591 "fitod $src, $dst", 592 [(set DFPRegs:$dst, (SPitof FPRegs:$src))]>; 593 594// Convert Floating-point to Integer Instructions, p. 142 595def FSTOI : F3_3<2, 0b110100, 0b011010001, 596 (outs FPRegs:$dst), (ins FPRegs:$src), 597 "fstoi $src, $dst", 598 [(set FPRegs:$dst, (SPftoi FPRegs:$src))]>; 599def FDTOI : F3_3<2, 0b110100, 0b011010010, 600 (outs FPRegs:$dst), (ins DFPRegs:$src), 601 "fdtoi $src, $dst", 602 [(set FPRegs:$dst, (SPftoi DFPRegs:$src))]>; 603 604// Convert between Floating-point Formats Instructions, p. 143 605def FSTOD : F3_3<2, 0b110100, 0b011001001, 606 (outs DFPRegs:$dst), (ins FPRegs:$src), 607 "fstod $src, $dst", 608 [(set f64:$dst, (fextend f32:$src))]>; 609def FDTOS : F3_3<2, 0b110100, 0b011000110, 610 (outs FPRegs:$dst), (ins DFPRegs:$src), 611 "fdtos $src, $dst", 612 [(set f32:$dst, (fround f64:$src))]>; 613 614// Floating-point Move Instructions, p. 144 615def FMOVS : F3_3<2, 0b110100, 0b000000001, 616 (outs FPRegs:$dst), (ins FPRegs:$src), 617 "fmovs $src, $dst", []>; 618def FNEGS : F3_3<2, 0b110100, 0b000000101, 619 (outs FPRegs:$dst), (ins FPRegs:$src), 620 "fnegs $src, $dst", 621 [(set f32:$dst, (fneg f32:$src))]>; 622def FABSS : F3_3<2, 0b110100, 0b000001001, 623 (outs FPRegs:$dst), (ins FPRegs:$src), 624 "fabss $src, $dst", 625 [(set f32:$dst, (fabs f32:$src))]>; 626 627 628// Floating-point Square Root Instructions, p.145 629def FSQRTS : F3_3<2, 0b110100, 0b000101001, 630 (outs FPRegs:$dst), (ins FPRegs:$src), 631 "fsqrts $src, $dst", 632 [(set f32:$dst, (fsqrt f32:$src))]>; 633def FSQRTD : F3_3<2, 0b110100, 0b000101010, 634 (outs DFPRegs:$dst), (ins DFPRegs:$src), 635 "fsqrtd $src, $dst", 636 [(set f64:$dst, (fsqrt f64:$src))]>; 637 638 639 640// Floating-point Add and Subtract Instructions, p. 146 641def FADDS : F3_3<2, 0b110100, 0b001000001, 642 (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2), 643 "fadds $src1, $src2, $dst", 644 [(set f32:$dst, (fadd f32:$src1, f32:$src2))]>; 645def FADDD : F3_3<2, 0b110100, 0b001000010, 646 (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2), 647 "faddd $src1, $src2, $dst", 648 [(set f64:$dst, (fadd f64:$src1, f64:$src2))]>; 649def FSUBS : F3_3<2, 0b110100, 0b001000101, 650 (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2), 651 "fsubs $src1, $src2, $dst", 652 [(set f32:$dst, (fsub f32:$src1, f32:$src2))]>; 653def FSUBD : F3_3<2, 0b110100, 0b001000110, 654 (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2), 655 "fsubd $src1, $src2, $dst", 656 [(set f64:$dst, (fsub f64:$src1, f64:$src2))]>; 657 658// Floating-point Multiply and Divide Instructions, p. 147 659def FMULS : F3_3<2, 0b110100, 0b001001001, 660 (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2), 661 "fmuls $src1, $src2, $dst", 662 [(set f32:$dst, (fmul f32:$src1, f32:$src2))]>; 663def FMULD : F3_3<2, 0b110100, 0b001001010, 664 (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2), 665 "fmuld $src1, $src2, $dst", 666 [(set f64:$dst, (fmul f64:$src1, f64:$src2))]>; 667def FSMULD : F3_3<2, 0b110100, 0b001101001, 668 (outs DFPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2), 669 "fsmuld $src1, $src2, $dst", 670 [(set f64:$dst, (fmul (fextend f32:$src1), 671 (fextend f32:$src2)))]>; 672def FDIVS : F3_3<2, 0b110100, 0b001001101, 673 (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2), 674 "fdivs $src1, $src2, $dst", 675 [(set f32:$dst, (fdiv f32:$src1, f32:$src2))]>; 676def FDIVD : F3_3<2, 0b110100, 0b001001110, 677 (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2), 678 "fdivd $src1, $src2, $dst", 679 [(set f64:$dst, (fdiv f64:$src1, f64:$src2))]>; 680 681// Floating-point Compare Instructions, p. 148 682// Note: the 2nd template arg is different for these guys. 683// Note 2: the result of a FCMP is not available until the 2nd cycle 684// after the instr is retired, but there is no interlock. This behavior 685// is modelled with a forced noop after the instruction. 686let Defs = [FCC] in { 687 def FCMPS : F3_3<2, 0b110101, 0b001010001, 688 (outs), (ins FPRegs:$src1, FPRegs:$src2), 689 "fcmps $src1, $src2\n\tnop", 690 [(SPcmpfcc f32:$src1, f32:$src2)]>; 691 def FCMPD : F3_3<2, 0b110101, 0b001010010, 692 (outs), (ins DFPRegs:$src1, DFPRegs:$src2), 693 "fcmpd $src1, $src2\n\tnop", 694 [(SPcmpfcc f64:$src1, f64:$src2)]>; 695} 696 697//===----------------------------------------------------------------------===// 698// V9 Instructions 699//===----------------------------------------------------------------------===// 700 701// V9 Conditional Moves. 702let Predicates = [HasV9], Constraints = "$T = $dst" in { 703 // Move Integer Register on Condition (MOVcc) p. 194 of the V9 manual. 704 // FIXME: Add instruction encodings for the JIT some day. 705 let Uses = [ICC] in { 706 def MOVICCrr 707 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, CCOp:$cc), 708 "mov$cc %icc, $F, $dst", 709 [(set i32:$dst, (SPselecticc i32:$F, i32:$T, imm:$cc))]>; 710 def MOVICCri 711 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, i32imm:$F, CCOp:$cc), 712 "mov$cc %icc, $F, $dst", 713 [(set i32:$dst, (SPselecticc simm11:$F, i32:$T, imm:$cc))]>; 714 } 715 716 let Uses = [FCC] in { 717 def MOVFCCrr 718 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, CCOp:$cc), 719 "mov$cc %fcc0, $F, $dst", 720 [(set i32:$dst, (SPselectfcc i32:$F, i32:$T, imm:$cc))]>; 721 def MOVFCCri 722 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, i32imm:$F, CCOp:$cc), 723 "mov$cc %fcc0, $F, $dst", 724 [(set i32:$dst, (SPselectfcc simm11:$F, i32:$T, imm:$cc))]>; 725 } 726 727 let Uses = [ICC] in { 728 def FMOVS_ICC 729 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, CCOp:$cc), 730 "fmovs$cc %icc, $F, $dst", 731 [(set f32:$dst, 732 (SPselecticc f32:$F, f32:$T, imm:$cc))]>; 733 def FMOVD_ICC 734 : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, CCOp:$cc), 735 "fmovd$cc %icc, $F, $dst", 736 [(set f64:$dst, (SPselecticc f64:$F, f64:$T, imm:$cc))]>; 737 } 738 739 let Uses = [FCC] in { 740 def FMOVS_FCC 741 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, CCOp:$cc), 742 "fmovs$cc %fcc0, $F, $dst", 743 [(set f32:$dst, (SPselectfcc f32:$F, f32:$T, imm:$cc))]>; 744 def FMOVD_FCC 745 : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, CCOp:$cc), 746 "fmovd$cc %fcc0, $F, $dst", 747 [(set f64:$dst, (SPselectfcc f64:$F, f64:$T, imm:$cc))]>; 748 } 749 750} 751 752// Floating-Point Move Instructions, p. 164 of the V9 manual. 753let Predicates = [HasV9] in { 754 def FMOVD : F3_3<2, 0b110100, 0b000000010, 755 (outs DFPRegs:$dst), (ins DFPRegs:$src), 756 "fmovd $src, $dst", []>; 757 def FNEGD : F3_3<2, 0b110100, 0b000000110, 758 (outs DFPRegs:$dst), (ins DFPRegs:$src), 759 "fnegd $src, $dst", 760 [(set f64:$dst, (fneg f64:$src))]>; 761 def FABSD : F3_3<2, 0b110100, 0b000001010, 762 (outs DFPRegs:$dst), (ins DFPRegs:$src), 763 "fabsd $src, $dst", 764 [(set f64:$dst, (fabs f64:$src))]>; 765} 766 767// POPCrr - This does a ctpop of a 64-bit register. As such, we have to clear 768// the top 32-bits before using it. To do this clearing, we use a SLLri X,0. 769def POPCrr : F3_1<2, 0b101110, 770 (outs IntRegs:$dst), (ins IntRegs:$src), 771 "popc $src, $dst", []>, Requires<[HasV9]>; 772def : Pat<(ctpop i32:$src), 773 (POPCrr (SLLri $src, 0))>; 774 775//===----------------------------------------------------------------------===// 776// Non-Instruction Patterns 777//===----------------------------------------------------------------------===// 778 779// Small immediates. 780def : Pat<(i32 simm13:$val), 781 (ORri (i32 G0), imm:$val)>; 782// Arbitrary immediates. 783def : Pat<(i32 imm:$val), 784 (ORri (SETHIi (HI22 imm:$val)), (LO10 imm:$val))>; 785 786// subc 787def : Pat<(subc i32:$b, i32:$c), 788 (SUBCCrr $b, $c)>; 789def : Pat<(subc i32:$b, simm13:$val), 790 (SUBCCri $b, imm:$val)>; 791 792// Global addresses, constant pool entries 793def : Pat<(SPhi tglobaladdr:$in), (SETHIi tglobaladdr:$in)>; 794def : Pat<(SPlo tglobaladdr:$in), (ORri (i32 G0), tglobaladdr:$in)>; 795def : Pat<(SPhi tconstpool:$in), (SETHIi tconstpool:$in)>; 796def : Pat<(SPlo tconstpool:$in), (ORri (i32 G0), tconstpool:$in)>; 797 798// Add reg, lo. This is used when taking the addr of a global/constpool entry. 799def : Pat<(add iPTR:$r, (SPlo tglobaladdr:$in)), (ADDri $r, tglobaladdr:$in)>; 800def : Pat<(add iPTR:$r, (SPlo tconstpool:$in)), (ADDri $r, tconstpool:$in)>; 801 802// Calls: 803def : Pat<(call tglobaladdr:$dst), 804 (CALL tglobaladdr:$dst)>; 805def : Pat<(call texternalsym:$dst), 806 (CALL texternalsym:$dst)>; 807 808// Map integer extload's to zextloads. 809def : Pat<(i32 (extloadi1 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>; 810def : Pat<(i32 (extloadi1 ADDRri:$src)), (LDUBri ADDRri:$src)>; 811def : Pat<(i32 (extloadi8 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>; 812def : Pat<(i32 (extloadi8 ADDRri:$src)), (LDUBri ADDRri:$src)>; 813def : Pat<(i32 (extloadi16 ADDRrr:$src)), (LDUHrr ADDRrr:$src)>; 814def : Pat<(i32 (extloadi16 ADDRri:$src)), (LDUHri ADDRri:$src)>; 815 816// zextload bool -> zextload byte 817def : Pat<(i32 (zextloadi1 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>; 818def : Pat<(i32 (zextloadi1 ADDRri:$src)), (LDUBri ADDRri:$src)>; 819 820include "SparcInstr64Bit.td" 821