SparcInstrInfo.td revision f27df33b02a85a030aaa4476aee7d1e8fe5921b2
1//===- SparcInstrInfo.td - Target Description for Sparc Target ------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the Sparc instructions in TableGen format. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// Instruction format superclass 16//===----------------------------------------------------------------------===// 17 18include "SparcInstrFormats.td" 19 20//===----------------------------------------------------------------------===// 21// Feature predicates. 22//===----------------------------------------------------------------------===// 23 24// HasV9 - This predicate is true when the target processor supports V9 25// instructions. Note that the machine may be running in 32-bit mode. 26def HasV9 : Predicate<"Subtarget.isV9()">; 27 28// HasNoV9 - This predicate is true when the target doesn't have V9 29// instructions. Use of this is just a hack for the isel not having proper 30// costs for V8 instructions that are more expensive than their V9 ones. 31def HasNoV9 : Predicate<"!Subtarget.isV9()">; 32 33// HasVIS - This is true when the target processor has VIS extensions. 34def HasVIS : Predicate<"Subtarget.isVIS()">; 35 36// UseDeprecatedInsts - This predicate is true when the target processor is a 37// V8, or when it is V9 but the V8 deprecated instructions are efficient enough 38// to use when appropriate. In either of these cases, the instruction selector 39// will pick deprecated instructions. 40def UseDeprecatedInsts : Predicate<"Subtarget.useDeprecatedV8Instructions()">; 41 42//===----------------------------------------------------------------------===// 43// Instruction Pattern Stuff 44//===----------------------------------------------------------------------===// 45 46def simm11 : PatLeaf<(imm), [{ return isInt<11>(N->getSExtValue()); }]>; 47 48def simm13 : PatLeaf<(imm), [{ return isInt<13>(N->getSExtValue()); }]>; 49 50def LO10 : SDNodeXForm<imm, [{ 51 return CurDAG->getTargetConstant((unsigned)N->getZExtValue() & 1023, 52 MVT::i32); 53}]>; 54 55def HI22 : SDNodeXForm<imm, [{ 56 // Transformation function: shift the immediate value down into the low bits. 57 return CurDAG->getTargetConstant((unsigned)N->getZExtValue() >> 10, MVT::i32); 58}]>; 59 60def SETHIimm : PatLeaf<(imm), [{ 61 return (((unsigned)N->getZExtValue() >> 10) << 10) == 62 (unsigned)N->getZExtValue(); 63}], HI22>; 64 65// Addressing modes. 66def ADDRrr : ComplexPattern<i32, 2, "SelectADDRrr", [], []>; 67def ADDRri : ComplexPattern<i32, 2, "SelectADDRri", [frameindex], []>; 68 69// Address operands 70def MEMrr : Operand<i32> { 71 let PrintMethod = "printMemOperand"; 72 let MIOperandInfo = (ops IntRegs, IntRegs); 73} 74def MEMri : Operand<i32> { 75 let PrintMethod = "printMemOperand"; 76 let MIOperandInfo = (ops IntRegs, i32imm); 77} 78 79// Branch targets have OtherVT type. 80def brtarget : Operand<OtherVT>; 81def calltarget : Operand<i32>; 82 83// Operand for printing out a condition code. 84let PrintMethod = "printCCOperand" in 85 def CCOp : Operand<i32>; 86 87def SDTSPcmpfcc : 88SDTypeProfile<0, 2, [SDTCisFP<0>, SDTCisSameAs<0, 1>]>; 89def SDTSPbrcc : 90SDTypeProfile<0, 2, [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>; 91def SDTSPselectcc : 92SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>]>; 93def SDTSPFTOI : 94SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisFP<1>]>; 95def SDTSPITOF : 96SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f32>]>; 97 98def SPcmpicc : SDNode<"SPISD::CMPICC", SDTIntBinOp, [SDNPOutGlue]>; 99def SPcmpfcc : SDNode<"SPISD::CMPFCC", SDTSPcmpfcc, [SDNPOutGlue]>; 100def SPbricc : SDNode<"SPISD::BRICC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>; 101def SPbrfcc : SDNode<"SPISD::BRFCC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>; 102 103def SPhi : SDNode<"SPISD::Hi", SDTIntUnaryOp>; 104def SPlo : SDNode<"SPISD::Lo", SDTIntUnaryOp>; 105 106def SPftoi : SDNode<"SPISD::FTOI", SDTSPFTOI>; 107def SPitof : SDNode<"SPISD::ITOF", SDTSPITOF>; 108 109def SPselecticc : SDNode<"SPISD::SELECT_ICC", SDTSPselectcc, [SDNPInGlue]>; 110def SPselectfcc : SDNode<"SPISD::SELECT_FCC", SDTSPselectcc, [SDNPInGlue]>; 111 112// These are target-independent nodes, but have target-specific formats. 113def SDT_SPCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>; 114def SDT_SPCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, 115 SDTCisVT<1, i32> ]>; 116 117def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_SPCallSeqStart, 118 [SDNPHasChain, SDNPOutGlue]>; 119def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_SPCallSeqEnd, 120 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 121 122def SDT_SPCall : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>; 123def call : SDNode<"SPISD::CALL", SDT_SPCall, 124 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 125 126def retflag : SDNode<"SPISD::RET_FLAG", SDTNone, 127 [SDNPHasChain, SDNPOptInGlue]>; 128 129def getPCX : Operand<i32> { 130 let PrintMethod = "printGetPCX"; 131} 132 133//===----------------------------------------------------------------------===// 134// SPARC Flag Conditions 135//===----------------------------------------------------------------------===// 136 137// Note that these values must be kept in sync with the CCOp::CondCode enum 138// values. 139class ICC_VAL<int N> : PatLeaf<(i32 N)>; 140def ICC_NE : ICC_VAL< 9>; // Not Equal 141def ICC_E : ICC_VAL< 1>; // Equal 142def ICC_G : ICC_VAL<10>; // Greater 143def ICC_LE : ICC_VAL< 2>; // Less or Equal 144def ICC_GE : ICC_VAL<11>; // Greater or Equal 145def ICC_L : ICC_VAL< 3>; // Less 146def ICC_GU : ICC_VAL<12>; // Greater Unsigned 147def ICC_LEU : ICC_VAL< 4>; // Less or Equal Unsigned 148def ICC_CC : ICC_VAL<13>; // Carry Clear/Great or Equal Unsigned 149def ICC_CS : ICC_VAL< 5>; // Carry Set/Less Unsigned 150def ICC_POS : ICC_VAL<14>; // Positive 151def ICC_NEG : ICC_VAL< 6>; // Negative 152def ICC_VC : ICC_VAL<15>; // Overflow Clear 153def ICC_VS : ICC_VAL< 7>; // Overflow Set 154 155class FCC_VAL<int N> : PatLeaf<(i32 N)>; 156def FCC_U : FCC_VAL<23>; // Unordered 157def FCC_G : FCC_VAL<22>; // Greater 158def FCC_UG : FCC_VAL<21>; // Unordered or Greater 159def FCC_L : FCC_VAL<20>; // Less 160def FCC_UL : FCC_VAL<19>; // Unordered or Less 161def FCC_LG : FCC_VAL<18>; // Less or Greater 162def FCC_NE : FCC_VAL<17>; // Not Equal 163def FCC_E : FCC_VAL<25>; // Equal 164def FCC_UE : FCC_VAL<24>; // Unordered or Equal 165def FCC_GE : FCC_VAL<25>; // Greater or Equal 166def FCC_UGE : FCC_VAL<26>; // Unordered or Greater or Equal 167def FCC_LE : FCC_VAL<27>; // Less or Equal 168def FCC_ULE : FCC_VAL<28>; // Unordered or Less or Equal 169def FCC_O : FCC_VAL<29>; // Ordered 170 171//===----------------------------------------------------------------------===// 172// Instruction Class Templates 173//===----------------------------------------------------------------------===// 174 175/// F3_12 multiclass - Define a normal F3_1/F3_2 pattern in one shot. 176multiclass F3_12<string OpcStr, bits<6> Op3Val, SDNode OpNode> { 177 def rr : F3_1<2, Op3Val, 178 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c), 179 !strconcat(OpcStr, " $b, $c, $dst"), 180 [(set IntRegs:$dst, (OpNode IntRegs:$b, IntRegs:$c))]>; 181 def ri : F3_2<2, Op3Val, 182 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c), 183 !strconcat(OpcStr, " $b, $c, $dst"), 184 [(set IntRegs:$dst, (OpNode IntRegs:$b, simm13:$c))]>; 185} 186 187/// F3_12np multiclass - Define a normal F3_1/F3_2 pattern in one shot, with no 188/// pattern. 189multiclass F3_12np<string OpcStr, bits<6> Op3Val> { 190 def rr : F3_1<2, Op3Val, 191 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c), 192 !strconcat(OpcStr, " $b, $c, $dst"), []>; 193 def ri : F3_2<2, Op3Val, 194 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c), 195 !strconcat(OpcStr, " $b, $c, $dst"), []>; 196} 197 198//===----------------------------------------------------------------------===// 199// Instructions 200//===----------------------------------------------------------------------===// 201 202// Pseudo instructions. 203class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern> 204 : InstSP<outs, ins, asmstr, pattern>; 205 206// GETPCX for PIC 207let Defs = [O7], Uses = [O7] in { 208 def GETPCX : Pseudo<(outs getPCX:$getpcseq), (ins), "$getpcseq", [] >; 209} 210 211let Defs = [O6], Uses = [O6] in { 212def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt), 213 "!ADJCALLSTACKDOWN $amt", 214 [(callseq_start timm:$amt)]>; 215def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2), 216 "!ADJCALLSTACKUP $amt1", 217 [(callseq_end timm:$amt1, timm:$amt2)]>; 218} 219 220// FpMOVD/FpNEGD/FpABSD - These are lowered to single-precision ops by the 221// fpmover pass. 222let Predicates = [HasNoV9] in { // Only emit these in V8 mode. 223 def FpMOVD : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$src), 224 "!FpMOVD $src, $dst", []>; 225 def FpNEGD : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$src), 226 "!FpNEGD $src, $dst", 227 [(set DFPRegs:$dst, (fneg DFPRegs:$src))]>; 228 def FpABSD : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$src), 229 "!FpABSD $src, $dst", 230 [(set DFPRegs:$dst, (fabs DFPRegs:$src))]>; 231} 232 233// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after 234// instruction selection into a branch sequence. This has to handle all 235// permutations of selection between i32/f32/f64 on ICC and FCC. 236 // Expanded after instruction selection. 237let Uses = [ICC], usesCustomInserter = 1 in { 238 def SELECT_CC_Int_ICC 239 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond), 240 "; SELECT_CC_Int_ICC PSEUDO!", 241 [(set IntRegs:$dst, (SPselecticc IntRegs:$T, IntRegs:$F, 242 imm:$Cond))]>; 243 def SELECT_CC_FP_ICC 244 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, i32imm:$Cond), 245 "; SELECT_CC_FP_ICC PSEUDO!", 246 [(set FPRegs:$dst, (SPselecticc FPRegs:$T, FPRegs:$F, 247 imm:$Cond))]>; 248 249 def SELECT_CC_DFP_ICC 250 : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, i32imm:$Cond), 251 "; SELECT_CC_DFP_ICC PSEUDO!", 252 [(set DFPRegs:$dst, (SPselecticc DFPRegs:$T, DFPRegs:$F, 253 imm:$Cond))]>; 254} 255 256let usesCustomInserter = 1, Uses = [FCC] in { 257 258 def SELECT_CC_Int_FCC 259 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond), 260 "; SELECT_CC_Int_FCC PSEUDO!", 261 [(set IntRegs:$dst, (SPselectfcc IntRegs:$T, IntRegs:$F, 262 imm:$Cond))]>; 263 264 def SELECT_CC_FP_FCC 265 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, i32imm:$Cond), 266 "; SELECT_CC_FP_FCC PSEUDO!", 267 [(set FPRegs:$dst, (SPselectfcc FPRegs:$T, FPRegs:$F, 268 imm:$Cond))]>; 269 def SELECT_CC_DFP_FCC 270 : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, i32imm:$Cond), 271 "; SELECT_CC_DFP_FCC PSEUDO!", 272 [(set DFPRegs:$dst, (SPselectfcc DFPRegs:$T, DFPRegs:$F, 273 imm:$Cond))]>; 274} 275 276 277// Section A.3 - Synthetic Instructions, p. 85 278// special cases of JMPL: 279let isReturn = 1, isTerminator = 1, hasDelaySlot = 1, isBarrier = 1 in { 280 let rd = O7.Num, rs1 = G0.Num, simm13 = 8 in 281 def RETL: F3_2<2, 0b111000, (outs), (ins), "retl", [(retflag)]>; 282} 283 284// Section B.1 - Load Integer Instructions, p. 90 285def LDSBrr : F3_1<3, 0b001001, 286 (outs IntRegs:$dst), (ins MEMrr:$addr), 287 "ldsb [$addr], $dst", 288 [(set IntRegs:$dst, (sextloadi8 ADDRrr:$addr))]>; 289def LDSBri : F3_2<3, 0b001001, 290 (outs IntRegs:$dst), (ins MEMri:$addr), 291 "ldsb [$addr], $dst", 292 [(set IntRegs:$dst, (sextloadi8 ADDRri:$addr))]>; 293def LDSHrr : F3_1<3, 0b001010, 294 (outs IntRegs:$dst), (ins MEMrr:$addr), 295 "ldsh [$addr], $dst", 296 [(set IntRegs:$dst, (sextloadi16 ADDRrr:$addr))]>; 297def LDSHri : F3_2<3, 0b001010, 298 (outs IntRegs:$dst), (ins MEMri:$addr), 299 "ldsh [$addr], $dst", 300 [(set IntRegs:$dst, (sextloadi16 ADDRri:$addr))]>; 301def LDUBrr : F3_1<3, 0b000001, 302 (outs IntRegs:$dst), (ins MEMrr:$addr), 303 "ldub [$addr], $dst", 304 [(set IntRegs:$dst, (zextloadi8 ADDRrr:$addr))]>; 305def LDUBri : F3_2<3, 0b000001, 306 (outs IntRegs:$dst), (ins MEMri:$addr), 307 "ldub [$addr], $dst", 308 [(set IntRegs:$dst, (zextloadi8 ADDRri:$addr))]>; 309def LDUHrr : F3_1<3, 0b000010, 310 (outs IntRegs:$dst), (ins MEMrr:$addr), 311 "lduh [$addr], $dst", 312 [(set IntRegs:$dst, (zextloadi16 ADDRrr:$addr))]>; 313def LDUHri : F3_2<3, 0b000010, 314 (outs IntRegs:$dst), (ins MEMri:$addr), 315 "lduh [$addr], $dst", 316 [(set IntRegs:$dst, (zextloadi16 ADDRri:$addr))]>; 317def LDrr : F3_1<3, 0b000000, 318 (outs IntRegs:$dst), (ins MEMrr:$addr), 319 "ld [$addr], $dst", 320 [(set IntRegs:$dst, (load ADDRrr:$addr))]>; 321def LDri : F3_2<3, 0b000000, 322 (outs IntRegs:$dst), (ins MEMri:$addr), 323 "ld [$addr], $dst", 324 [(set IntRegs:$dst, (load ADDRri:$addr))]>; 325 326// Section B.2 - Load Floating-point Instructions, p. 92 327def LDFrr : F3_1<3, 0b100000, 328 (outs FPRegs:$dst), (ins MEMrr:$addr), 329 "ld [$addr], $dst", 330 [(set FPRegs:$dst, (load ADDRrr:$addr))]>; 331def LDFri : F3_2<3, 0b100000, 332 (outs FPRegs:$dst), (ins MEMri:$addr), 333 "ld [$addr], $dst", 334 [(set FPRegs:$dst, (load ADDRri:$addr))]>; 335def LDDFrr : F3_1<3, 0b100011, 336 (outs DFPRegs:$dst), (ins MEMrr:$addr), 337 "ldd [$addr], $dst", 338 [(set DFPRegs:$dst, (load ADDRrr:$addr))]>; 339def LDDFri : F3_2<3, 0b100011, 340 (outs DFPRegs:$dst), (ins MEMri:$addr), 341 "ldd [$addr], $dst", 342 [(set DFPRegs:$dst, (load ADDRri:$addr))]>; 343 344// Section B.4 - Store Integer Instructions, p. 95 345def STBrr : F3_1<3, 0b000101, 346 (outs), (ins MEMrr:$addr, IntRegs:$src), 347 "stb $src, [$addr]", 348 [(truncstorei8 IntRegs:$src, ADDRrr:$addr)]>; 349def STBri : F3_2<3, 0b000101, 350 (outs), (ins MEMri:$addr, IntRegs:$src), 351 "stb $src, [$addr]", 352 [(truncstorei8 IntRegs:$src, ADDRri:$addr)]>; 353def STHrr : F3_1<3, 0b000110, 354 (outs), (ins MEMrr:$addr, IntRegs:$src), 355 "sth $src, [$addr]", 356 [(truncstorei16 IntRegs:$src, ADDRrr:$addr)]>; 357def STHri : F3_2<3, 0b000110, 358 (outs), (ins MEMri:$addr, IntRegs:$src), 359 "sth $src, [$addr]", 360 [(truncstorei16 IntRegs:$src, ADDRri:$addr)]>; 361def STrr : F3_1<3, 0b000100, 362 (outs), (ins MEMrr:$addr, IntRegs:$src), 363 "st $src, [$addr]", 364 [(store IntRegs:$src, ADDRrr:$addr)]>; 365def STri : F3_2<3, 0b000100, 366 (outs), (ins MEMri:$addr, IntRegs:$src), 367 "st $src, [$addr]", 368 [(store IntRegs:$src, ADDRri:$addr)]>; 369 370// Section B.5 - Store Floating-point Instructions, p. 97 371def STFrr : F3_1<3, 0b100100, 372 (outs), (ins MEMrr:$addr, FPRegs:$src), 373 "st $src, [$addr]", 374 [(store FPRegs:$src, ADDRrr:$addr)]>; 375def STFri : F3_2<3, 0b100100, 376 (outs), (ins MEMri:$addr, FPRegs:$src), 377 "st $src, [$addr]", 378 [(store FPRegs:$src, ADDRri:$addr)]>; 379def STDFrr : F3_1<3, 0b100111, 380 (outs), (ins MEMrr:$addr, DFPRegs:$src), 381 "std $src, [$addr]", 382 [(store DFPRegs:$src, ADDRrr:$addr)]>; 383def STDFri : F3_2<3, 0b100111, 384 (outs), (ins MEMri:$addr, DFPRegs:$src), 385 "std $src, [$addr]", 386 [(store DFPRegs:$src, ADDRri:$addr)]>; 387 388// Section B.9 - SETHI Instruction, p. 104 389def SETHIi: F2_1<0b100, 390 (outs IntRegs:$dst), (ins i32imm:$src), 391 "sethi $src, $dst", 392 [(set IntRegs:$dst, SETHIimm:$src)]>; 393 394// Section B.10 - NOP Instruction, p. 105 395// (It's a special case of SETHI) 396let rd = 0, imm22 = 0 in 397 def NOP : F2_1<0b100, (outs), (ins), "nop", []>; 398 399// Section B.11 - Logical Instructions, p. 106 400defm AND : F3_12<"and", 0b000001, and>; 401 402def ANDNrr : F3_1<2, 0b000101, 403 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c), 404 "andn $b, $c, $dst", 405 [(set IntRegs:$dst, (and IntRegs:$b, (not IntRegs:$c)))]>; 406def ANDNri : F3_2<2, 0b000101, 407 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c), 408 "andn $b, $c, $dst", []>; 409 410defm OR : F3_12<"or", 0b000010, or>; 411 412def ORNrr : F3_1<2, 0b000110, 413 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c), 414 "orn $b, $c, $dst", 415 [(set IntRegs:$dst, (or IntRegs:$b, (not IntRegs:$c)))]>; 416def ORNri : F3_2<2, 0b000110, 417 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c), 418 "orn $b, $c, $dst", []>; 419defm XOR : F3_12<"xor", 0b000011, xor>; 420 421def XNORrr : F3_1<2, 0b000111, 422 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c), 423 "xnor $b, $c, $dst", 424 [(set IntRegs:$dst, (not (xor IntRegs:$b, IntRegs:$c)))]>; 425def XNORri : F3_2<2, 0b000111, 426 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c), 427 "xnor $b, $c, $dst", []>; 428 429// Section B.12 - Shift Instructions, p. 107 430defm SLL : F3_12<"sll", 0b100101, shl>; 431defm SRL : F3_12<"srl", 0b100110, srl>; 432defm SRA : F3_12<"sra", 0b100111, sra>; 433 434// Section B.13 - Add Instructions, p. 108 435defm ADD : F3_12<"add", 0b000000, add>; 436 437// "LEA" forms of add (patterns to make tblgen happy) 438def LEA_ADDri : F3_2<2, 0b000000, 439 (outs IntRegs:$dst), (ins MEMri:$addr), 440 "add ${addr:arith}, $dst", 441 [(set IntRegs:$dst, ADDRri:$addr)]>; 442 443let Defs = [ICC] in 444 defm ADDCC : F3_12<"addcc", 0b010000, addc>; 445 446let Uses = [ICC] in 447 defm ADDX : F3_12<"addx", 0b001000, adde>; 448 449// Section B.15 - Subtract Instructions, p. 110 450defm SUB : F3_12 <"sub" , 0b000100, sub>; 451let Uses = [ICC] in 452 defm SUBX : F3_12 <"subx" , 0b001100, sube>; 453 454let Defs = [ICC] in 455 defm SUBCC : F3_12 <"subcc", 0b010100, SPcmpicc>; 456 457let Uses = [ICC], Defs = [ICC] in 458 def SUBXCCrr: F3_1<2, 0b011100, 459 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c), 460 "subxcc $b, $c, $dst", []>; 461 462 463// Section B.18 - Multiply Instructions, p. 113 464let Defs = [Y] in { 465 defm UMUL : F3_12np<"umul", 0b001010>; 466 defm SMUL : F3_12 <"smul", 0b001011, mul>; 467} 468 469// Section B.19 - Divide Instructions, p. 115 470let Defs = [Y] in { 471 defm UDIV : F3_12np<"udiv", 0b001110>; 472 defm SDIV : F3_12np<"sdiv", 0b001111>; 473} 474 475// Section B.20 - SAVE and RESTORE, p. 117 476defm SAVE : F3_12np<"save" , 0b111100>; 477defm RESTORE : F3_12np<"restore", 0b111101>; 478 479// Section B.21 - Branch on Integer Condition Codes Instructions, p. 119 480 481// conditional branch class: 482class BranchSP<bits<4> cc, dag ins, string asmstr, list<dag> pattern> 483 : F2_2<cc, 0b010, (outs), ins, asmstr, pattern> { 484 let isBranch = 1; 485 let isTerminator = 1; 486 let hasDelaySlot = 1; 487} 488 489let isBarrier = 1 in 490 def BA : BranchSP<0b1000, (ins brtarget:$dst), 491 "ba $dst", 492 [(br bb:$dst)]>; 493 494// FIXME: the encoding for the JIT should look at the condition field. 495let Uses = [ICC] in 496 def BCOND : BranchSP<0, (ins brtarget:$dst, CCOp:$cc), 497 "b$cc $dst", 498 [(SPbricc bb:$dst, imm:$cc)]>; 499 500 501// Section B.22 - Branch on Floating-point Condition Codes Instructions, p. 121 502 503// floating-point conditional branch class: 504class FPBranchSP<bits<4> cc, dag ins, string asmstr, list<dag> pattern> 505 : F2_2<cc, 0b110, (outs), ins, asmstr, pattern> { 506 let isBranch = 1; 507 let isTerminator = 1; 508 let hasDelaySlot = 1; 509} 510 511// FIXME: the encoding for the JIT should look at the condition field. 512let Uses = [FCC] in 513 def FBCOND : FPBranchSP<0, (ins brtarget:$dst, CCOp:$cc), 514 "fb$cc $dst", 515 [(SPbrfcc bb:$dst, imm:$cc)]>; 516 517 518// Section B.24 - Call and Link Instruction, p. 125 519// This is the only Format 1 instruction 520let Uses = [O0, O1, O2, O3, O4, O5], 521 hasDelaySlot = 1, isCall = 1, 522 Defs = [O0, O1, O2, O3, O4, O5, O7, G1, G2, G3, G4, G5, G6, G7, 523 D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15] in { 524 def CALL : InstSP<(outs), (ins calltarget:$dst), 525 "call $dst", []> { 526 bits<30> disp; 527 let op = 1; 528 let Inst{29-0} = disp; 529 } 530 531 // indirect calls 532 def JMPLrr : F3_1<2, 0b111000, 533 (outs), (ins MEMrr:$ptr), 534 "call $ptr", 535 [(call ADDRrr:$ptr)]>; 536 def JMPLri : F3_2<2, 0b111000, 537 (outs), (ins MEMri:$ptr), 538 "call $ptr", 539 [(call ADDRri:$ptr)]>; 540} 541 542// Section B.28 - Read State Register Instructions 543let Uses = [Y] in 544 def RDY : F3_1<2, 0b101000, 545 (outs IntRegs:$dst), (ins), 546 "rd %y, $dst", []>; 547 548// Section B.29 - Write State Register Instructions 549let Defs = [Y] in { 550 def WRYrr : F3_1<2, 0b110000, 551 (outs), (ins IntRegs:$b, IntRegs:$c), 552 "wr $b, $c, %y", []>; 553 def WRYri : F3_2<2, 0b110000, 554 (outs), (ins IntRegs:$b, i32imm:$c), 555 "wr $b, $c, %y", []>; 556} 557// Convert Integer to Floating-point Instructions, p. 141 558def FITOS : F3_3<2, 0b110100, 0b011000100, 559 (outs FPRegs:$dst), (ins FPRegs:$src), 560 "fitos $src, $dst", 561 [(set FPRegs:$dst, (SPitof FPRegs:$src))]>; 562def FITOD : F3_3<2, 0b110100, 0b011001000, 563 (outs DFPRegs:$dst), (ins FPRegs:$src), 564 "fitod $src, $dst", 565 [(set DFPRegs:$dst, (SPitof FPRegs:$src))]>; 566 567// Convert Floating-point to Integer Instructions, p. 142 568def FSTOI : F3_3<2, 0b110100, 0b011010001, 569 (outs FPRegs:$dst), (ins FPRegs:$src), 570 "fstoi $src, $dst", 571 [(set FPRegs:$dst, (SPftoi FPRegs:$src))]>; 572def FDTOI : F3_3<2, 0b110100, 0b011010010, 573 (outs FPRegs:$dst), (ins DFPRegs:$src), 574 "fdtoi $src, $dst", 575 [(set FPRegs:$dst, (SPftoi DFPRegs:$src))]>; 576 577// Convert between Floating-point Formats Instructions, p. 143 578def FSTOD : F3_3<2, 0b110100, 0b011001001, 579 (outs DFPRegs:$dst), (ins FPRegs:$src), 580 "fstod $src, $dst", 581 [(set DFPRegs:$dst, (fextend FPRegs:$src))]>; 582def FDTOS : F3_3<2, 0b110100, 0b011000110, 583 (outs FPRegs:$dst), (ins DFPRegs:$src), 584 "fdtos $src, $dst", 585 [(set FPRegs:$dst, (fround DFPRegs:$src))]>; 586 587// Floating-point Move Instructions, p. 144 588def FMOVS : F3_3<2, 0b110100, 0b000000001, 589 (outs FPRegs:$dst), (ins FPRegs:$src), 590 "fmovs $src, $dst", []>; 591def FNEGS : F3_3<2, 0b110100, 0b000000101, 592 (outs FPRegs:$dst), (ins FPRegs:$src), 593 "fnegs $src, $dst", 594 [(set FPRegs:$dst, (fneg FPRegs:$src))]>; 595def FABSS : F3_3<2, 0b110100, 0b000001001, 596 (outs FPRegs:$dst), (ins FPRegs:$src), 597 "fabss $src, $dst", 598 [(set FPRegs:$dst, (fabs FPRegs:$src))]>; 599 600 601// Floating-point Square Root Instructions, p.145 602def FSQRTS : F3_3<2, 0b110100, 0b000101001, 603 (outs FPRegs:$dst), (ins FPRegs:$src), 604 "fsqrts $src, $dst", 605 [(set FPRegs:$dst, (fsqrt FPRegs:$src))]>; 606def FSQRTD : F3_3<2, 0b110100, 0b000101010, 607 (outs DFPRegs:$dst), (ins DFPRegs:$src), 608 "fsqrtd $src, $dst", 609 [(set DFPRegs:$dst, (fsqrt DFPRegs:$src))]>; 610 611 612 613// Floating-point Add and Subtract Instructions, p. 146 614def FADDS : F3_3<2, 0b110100, 0b001000001, 615 (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2), 616 "fadds $src1, $src2, $dst", 617 [(set FPRegs:$dst, (fadd FPRegs:$src1, FPRegs:$src2))]>; 618def FADDD : F3_3<2, 0b110100, 0b001000010, 619 (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2), 620 "faddd $src1, $src2, $dst", 621 [(set DFPRegs:$dst, (fadd DFPRegs:$src1, DFPRegs:$src2))]>; 622def FSUBS : F3_3<2, 0b110100, 0b001000101, 623 (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2), 624 "fsubs $src1, $src2, $dst", 625 [(set FPRegs:$dst, (fsub FPRegs:$src1, FPRegs:$src2))]>; 626def FSUBD : F3_3<2, 0b110100, 0b001000110, 627 (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2), 628 "fsubd $src1, $src2, $dst", 629 [(set DFPRegs:$dst, (fsub DFPRegs:$src1, DFPRegs:$src2))]>; 630 631// Floating-point Multiply and Divide Instructions, p. 147 632def FMULS : F3_3<2, 0b110100, 0b001001001, 633 (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2), 634 "fmuls $src1, $src2, $dst", 635 [(set FPRegs:$dst, (fmul FPRegs:$src1, FPRegs:$src2))]>; 636def FMULD : F3_3<2, 0b110100, 0b001001010, 637 (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2), 638 "fmuld $src1, $src2, $dst", 639 [(set DFPRegs:$dst, (fmul DFPRegs:$src1, DFPRegs:$src2))]>; 640def FSMULD : F3_3<2, 0b110100, 0b001101001, 641 (outs DFPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2), 642 "fsmuld $src1, $src2, $dst", 643 [(set DFPRegs:$dst, (fmul (fextend FPRegs:$src1), 644 (fextend FPRegs:$src2)))]>; 645def FDIVS : F3_3<2, 0b110100, 0b001001101, 646 (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2), 647 "fdivs $src1, $src2, $dst", 648 [(set FPRegs:$dst, (fdiv FPRegs:$src1, FPRegs:$src2))]>; 649def FDIVD : F3_3<2, 0b110100, 0b001001110, 650 (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2), 651 "fdivd $src1, $src2, $dst", 652 [(set DFPRegs:$dst, (fdiv DFPRegs:$src1, DFPRegs:$src2))]>; 653 654// Floating-point Compare Instructions, p. 148 655// Note: the 2nd template arg is different for these guys. 656// Note 2: the result of a FCMP is not available until the 2nd cycle 657// after the instr is retired, but there is no interlock. This behavior 658// is modelled with a forced noop after the instruction. 659let Defs = [FCC] in { 660 def FCMPS : F3_3<2, 0b110101, 0b001010001, 661 (outs), (ins FPRegs:$src1, FPRegs:$src2), 662 "fcmps $src1, $src2\n\tnop", 663 [(SPcmpfcc FPRegs:$src1, FPRegs:$src2)]>; 664 def FCMPD : F3_3<2, 0b110101, 0b001010010, 665 (outs), (ins DFPRegs:$src1, DFPRegs:$src2), 666 "fcmpd $src1, $src2\n\tnop", 667 [(SPcmpfcc DFPRegs:$src1, DFPRegs:$src2)]>; 668} 669 670//===----------------------------------------------------------------------===// 671// V9 Instructions 672//===----------------------------------------------------------------------===// 673 674// V9 Conditional Moves. 675let Predicates = [HasV9], Constraints = "$T = $dst" in { 676 // Move Integer Register on Condition (MOVcc) p. 194 of the V9 manual. 677 // FIXME: Add instruction encodings for the JIT some day. 678 def MOVICCrr 679 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, CCOp:$cc), 680 "mov$cc %icc, $F, $dst", 681 [(set IntRegs:$dst, 682 (SPselecticc IntRegs:$F, IntRegs:$T, imm:$cc))]>; 683 def MOVICCri 684 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, i32imm:$F, CCOp:$cc), 685 "mov$cc %icc, $F, $dst", 686 [(set IntRegs:$dst, 687 (SPselecticc simm11:$F, IntRegs:$T, imm:$cc))]>; 688 689 def MOVFCCrr 690 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, CCOp:$cc), 691 "mov$cc %fcc0, $F, $dst", 692 [(set IntRegs:$dst, 693 (SPselectfcc IntRegs:$F, IntRegs:$T, imm:$cc))]>; 694 def MOVFCCri 695 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, i32imm:$F, CCOp:$cc), 696 "mov$cc %fcc0, $F, $dst", 697 [(set IntRegs:$dst, 698 (SPselectfcc simm11:$F, IntRegs:$T, imm:$cc))]>; 699 700 def FMOVS_ICC 701 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, CCOp:$cc), 702 "fmovs$cc %icc, $F, $dst", 703 [(set FPRegs:$dst, 704 (SPselecticc FPRegs:$F, FPRegs:$T, imm:$cc))]>; 705 def FMOVD_ICC 706 : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, CCOp:$cc), 707 "fmovd$cc %icc, $F, $dst", 708 [(set DFPRegs:$dst, 709 (SPselecticc DFPRegs:$F, DFPRegs:$T, imm:$cc))]>; 710 def FMOVS_FCC 711 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, CCOp:$cc), 712 "fmovs$cc %fcc0, $F, $dst", 713 [(set FPRegs:$dst, 714 (SPselectfcc FPRegs:$F, FPRegs:$T, imm:$cc))]>; 715 def FMOVD_FCC 716 : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, CCOp:$cc), 717 "fmovd$cc %fcc0, $F, $dst", 718 [(set DFPRegs:$dst, 719 (SPselectfcc DFPRegs:$F, DFPRegs:$T, imm:$cc))]>; 720 721} 722 723// Floating-Point Move Instructions, p. 164 of the V9 manual. 724let Predicates = [HasV9] in { 725 def FMOVD : F3_3<2, 0b110100, 0b000000010, 726 (outs DFPRegs:$dst), (ins DFPRegs:$src), 727 "fmovd $src, $dst", []>; 728 def FNEGD : F3_3<2, 0b110100, 0b000000110, 729 (outs DFPRegs:$dst), (ins DFPRegs:$src), 730 "fnegd $src, $dst", 731 [(set DFPRegs:$dst, (fneg DFPRegs:$src))]>; 732 def FABSD : F3_3<2, 0b110100, 0b000001010, 733 (outs DFPRegs:$dst), (ins DFPRegs:$src), 734 "fabsd $src, $dst", 735 [(set DFPRegs:$dst, (fabs DFPRegs:$src))]>; 736} 737 738// POPCrr - This does a ctpop of a 64-bit register. As such, we have to clear 739// the top 32-bits before using it. To do this clearing, we use a SLLri X,0. 740def POPCrr : F3_1<2, 0b101110, 741 (outs IntRegs:$dst), (ins IntRegs:$src), 742 "popc $src, $dst", []>, Requires<[HasV9]>; 743def : Pat<(ctpop IntRegs:$src), 744 (POPCrr (SLLri IntRegs:$src, 0))>; 745 746//===----------------------------------------------------------------------===// 747// Non-Instruction Patterns 748//===----------------------------------------------------------------------===// 749 750// Small immediates. 751def : Pat<(i32 simm13:$val), 752 (ORri G0, imm:$val)>; 753// Arbitrary immediates. 754def : Pat<(i32 imm:$val), 755 (ORri (SETHIi (HI22 imm:$val)), (LO10 imm:$val))>; 756 757// subc 758def : Pat<(subc IntRegs:$b, IntRegs:$c), 759 (SUBCCrr IntRegs:$b, IntRegs:$c)>; 760def : Pat<(subc IntRegs:$b, simm13:$val), 761 (SUBCCri IntRegs:$b, imm:$val)>; 762 763// Global addresses, constant pool entries 764def : Pat<(SPhi tglobaladdr:$in), (SETHIi tglobaladdr:$in)>; 765def : Pat<(SPlo tglobaladdr:$in), (ORri G0, tglobaladdr:$in)>; 766def : Pat<(SPhi tconstpool:$in), (SETHIi tconstpool:$in)>; 767def : Pat<(SPlo tconstpool:$in), (ORri G0, tconstpool:$in)>; 768 769// Add reg, lo. This is used when taking the addr of a global/constpool entry. 770def : Pat<(add IntRegs:$r, (SPlo tglobaladdr:$in)), 771 (ADDri IntRegs:$r, tglobaladdr:$in)>; 772def : Pat<(add IntRegs:$r, (SPlo tconstpool:$in)), 773 (ADDri IntRegs:$r, tconstpool:$in)>; 774 775// Calls: 776def : Pat<(call tglobaladdr:$dst), 777 (CALL tglobaladdr:$dst)>; 778def : Pat<(call texternalsym:$dst), 779 (CALL texternalsym:$dst)>; 780 781// Map integer extload's to zextloads. 782def : Pat<(i32 (extloadi1 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>; 783def : Pat<(i32 (extloadi1 ADDRri:$src)), (LDUBri ADDRri:$src)>; 784def : Pat<(i32 (extloadi8 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>; 785def : Pat<(i32 (extloadi8 ADDRri:$src)), (LDUBri ADDRri:$src)>; 786def : Pat<(i32 (extloadi16 ADDRrr:$src)), (LDUHrr ADDRrr:$src)>; 787def : Pat<(i32 (extloadi16 ADDRri:$src)), (LDUHri ADDRri:$src)>; 788 789// zextload bool -> zextload byte 790def : Pat<(i32 (zextloadi1 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>; 791def : Pat<(i32 (zextloadi1 ADDRri:$src)), (LDUBri ADDRri:$src)>; 792