SparcInstrInfo.td revision f613fcb74161d63dd8c4f5fc1dc0d7527a18f43e
1//===- SparcInstrInfo.td - Target Description for Sparc Target ------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the Sparc instructions in TableGen format. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// Instruction format superclass 16//===----------------------------------------------------------------------===// 17 18include "SparcInstrFormats.td" 19 20//===----------------------------------------------------------------------===// 21// Feature predicates. 22//===----------------------------------------------------------------------===// 23 24// HasV9 - This predicate is true when the target processor supports V9 25// instructions. Note that the machine may be running in 32-bit mode. 26def HasV9 : Predicate<"Subtarget.isV9()">; 27 28// HasNoV9 - This predicate is true when the target doesn't have V9 29// instructions. Use of this is just a hack for the isel not having proper 30// costs for V8 instructions that are more expensive than their V9 ones. 31def HasNoV9 : Predicate<"!Subtarget.isV9()">; 32 33// HasVIS - This is true when the target processor has VIS extensions. 34def HasVIS : Predicate<"Subtarget.isVIS()">; 35 36// UseDeprecatedInsts - This predicate is true when the target processor is a 37// V8, or when it is V9 but the V8 deprecated instructions are efficient enough 38// to use when appropriate. In either of these cases, the instruction selector 39// will pick deprecated instructions. 40def UseDeprecatedInsts : Predicate<"Subtarget.useDeprecatedV8Instructions()">; 41 42//===----------------------------------------------------------------------===// 43// Instruction Pattern Stuff 44//===----------------------------------------------------------------------===// 45 46def simm11 : PatLeaf<(imm), [{ 47 // simm11 predicate - True if the imm fits in a 11-bit sign extended field. 48 return (((int)N->getValue() << (32-11)) >> (32-11)) == (int)N->getValue(); 49}]>; 50 51def simm13 : PatLeaf<(imm), [{ 52 // simm13 predicate - True if the imm fits in a 13-bit sign extended field. 53 return (((int)N->getValue() << (32-13)) >> (32-13)) == (int)N->getValue(); 54}]>; 55 56def LO10 : SDNodeXForm<imm, [{ 57 return CurDAG->getTargetConstant((unsigned)N->getValue() & 1023, MVT::i32); 58}]>; 59 60def HI22 : SDNodeXForm<imm, [{ 61 // Transformation function: shift the immediate value down into the low bits. 62 return CurDAG->getTargetConstant((unsigned)N->getValue() >> 10, MVT::i32); 63}]>; 64 65def SETHIimm : PatLeaf<(imm), [{ 66 return (((unsigned)N->getValue() >> 10) << 10) == (unsigned)N->getValue(); 67}], HI22>; 68 69// Addressing modes. 70def ADDRrr : ComplexPattern<i32, 2, "SelectADDRrr", []>; 71def ADDRri : ComplexPattern<i32, 2, "SelectADDRri", []>; 72 73// Address operands 74def MEMrr : Operand<i32> { 75 let PrintMethod = "printMemOperand"; 76 let NumMIOperands = 2; 77 let MIOperandInfo = (ops IntRegs, IntRegs); 78} 79def MEMri : Operand<i32> { 80 let PrintMethod = "printMemOperand"; 81 let NumMIOperands = 2; 82 let MIOperandInfo = (ops IntRegs, i32imm); 83} 84 85// Branch targets have OtherVT type. 86def brtarget : Operand<OtherVT>; 87def calltarget : Operand<i32>; 88 89// Operand for printing out a condition code. 90let PrintMethod = "printCCOperand" in 91 def CCOp : Operand<i32>; 92 93def SDTSPcmpfcc : 94SDTypeProfile<0, 2, [SDTCisFP<0>, SDTCisSameAs<0, 1>]>; 95def SDTSPbrcc : 96SDTypeProfile<0, 2, [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>; 97def SDTSPselectcc : 98SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>]>; 99def SDTSPFTOI : 100SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisFP<1>]>; 101def SDTSPITOF : 102SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f32>]>; 103 104def SPcmpicc : SDNode<"SPISD::CMPICC", SDTIntBinOp, [SDNPOutFlag]>; 105def SPcmpfcc : SDNode<"SPISD::CMPFCC", SDTSPcmpfcc, [SDNPOutFlag]>; 106def SPbricc : SDNode<"SPISD::BRICC", SDTSPbrcc, [SDNPHasChain, SDNPInFlag]>; 107def SPbrfcc : SDNode<"SPISD::BRFCC", SDTSPbrcc, [SDNPHasChain, SDNPInFlag]>; 108 109def SPhi : SDNode<"SPISD::Hi", SDTIntUnaryOp>; 110def SPlo : SDNode<"SPISD::Lo", SDTIntUnaryOp>; 111 112def SPftoi : SDNode<"SPISD::FTOI", SDTSPFTOI>; 113def SPitof : SDNode<"SPISD::ITOF", SDTSPITOF>; 114 115def SPselecticc : SDNode<"SPISD::SELECT_ICC", SDTSPselectcc, [SDNPInFlag]>; 116def SPselectfcc : SDNode<"SPISD::SELECT_FCC", SDTSPselectcc, [SDNPInFlag]>; 117 118// These are target-independent nodes, but have target-specific formats. 119def SDT_SPCallSeq : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>; 120def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_SPCallSeq, [SDNPHasChain]>; 121def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_SPCallSeq, [SDNPHasChain]>; 122 123def SDT_SPCall : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>; 124def call : SDNode<"SPISD::CALL", SDT_SPCall, 125 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; 126 127def SDT_SPRetFlag : SDTypeProfile<0, 0, []>; 128def retflag : SDNode<"SPISD::RET_FLAG", SDT_SPRetFlag, 129 [SDNPHasChain, SDNPOptInFlag]>; 130 131//===----------------------------------------------------------------------===// 132// SPARC Flag Conditions 133//===----------------------------------------------------------------------===// 134 135// Note that these values must be kept in sync with the CCOp::CondCode enum 136// values. 137class ICC_VAL<int N> : PatLeaf<(i32 N)>; 138def ICC_NE : ICC_VAL< 9>; // Not Equal 139def ICC_E : ICC_VAL< 1>; // Equal 140def ICC_G : ICC_VAL<10>; // Greater 141def ICC_LE : ICC_VAL< 2>; // Less or Equal 142def ICC_GE : ICC_VAL<11>; // Greater or Equal 143def ICC_L : ICC_VAL< 3>; // Less 144def ICC_GU : ICC_VAL<12>; // Greater Unsigned 145def ICC_LEU : ICC_VAL< 4>; // Less or Equal Unsigned 146def ICC_CC : ICC_VAL<13>; // Carry Clear/Great or Equal Unsigned 147def ICC_CS : ICC_VAL< 5>; // Carry Set/Less Unsigned 148def ICC_POS : ICC_VAL<14>; // Positive 149def ICC_NEG : ICC_VAL< 6>; // Negative 150def ICC_VC : ICC_VAL<15>; // Overflow Clear 151def ICC_VS : ICC_VAL< 7>; // Overflow Set 152 153class FCC_VAL<int N> : PatLeaf<(i32 N)>; 154def FCC_U : FCC_VAL<23>; // Unordered 155def FCC_G : FCC_VAL<22>; // Greater 156def FCC_UG : FCC_VAL<21>; // Unordered or Greater 157def FCC_L : FCC_VAL<20>; // Less 158def FCC_UL : FCC_VAL<19>; // Unordered or Less 159def FCC_LG : FCC_VAL<18>; // Less or Greater 160def FCC_NE : FCC_VAL<17>; // Not Equal 161def FCC_E : FCC_VAL<25>; // Equal 162def FCC_UE : FCC_VAL<24>; // Unordered or Equal 163def FCC_GE : FCC_VAL<25>; // Greater or Equal 164def FCC_UGE : FCC_VAL<26>; // Unordered or Greater or Equal 165def FCC_LE : FCC_VAL<27>; // Less or Equal 166def FCC_ULE : FCC_VAL<28>; // Unordered or Less or Equal 167def FCC_O : FCC_VAL<29>; // Ordered 168 169 170//===----------------------------------------------------------------------===// 171// Instructions 172//===----------------------------------------------------------------------===// 173 174// Pseudo instructions. 175class Pseudo<dag ops, string asmstr, list<dag> pattern> 176 : InstSP<ops, asmstr, pattern>; 177 178def ADJCALLSTACKDOWN : Pseudo<(ops i32imm:$amt), 179 "!ADJCALLSTACKDOWN $amt", 180 [(callseq_start imm:$amt)]>; 181def ADJCALLSTACKUP : Pseudo<(ops i32imm:$amt), 182 "!ADJCALLSTACKUP $amt", 183 [(callseq_end imm:$amt)]>; 184def IMPLICIT_DEF_Int : Pseudo<(ops IntRegs:$dst), 185 "!IMPLICIT_DEF $dst", 186 [(set IntRegs:$dst, (undef))]>; 187def IMPLICIT_DEF_FP : Pseudo<(ops FPRegs:$dst), "!IMPLICIT_DEF $dst", 188 [(set FPRegs:$dst, (undef))]>; 189def IMPLICIT_DEF_DFP : Pseudo<(ops DFPRegs:$dst), "!IMPLICIT_DEF $dst", 190 [(set DFPRegs:$dst, (undef))]>; 191 192// FpMOVD/FpNEGD/FpABSD - These are lowered to single-precision ops by the 193// fpmover pass. 194let Predicates = [HasNoV9] in { // Only emit these in SP mode. 195 def FpMOVD : Pseudo<(ops DFPRegs:$dst, DFPRegs:$src), 196 "!FpMOVD $src, $dst", []>; 197 def FpNEGD : Pseudo<(ops DFPRegs:$dst, DFPRegs:$src), 198 "!FpNEGD $src, $dst", 199 [(set DFPRegs:$dst, (fneg DFPRegs:$src))]>; 200 def FpABSD : Pseudo<(ops DFPRegs:$dst, DFPRegs:$src), 201 "!FpABSD $src, $dst", 202 [(set DFPRegs:$dst, (fabs DFPRegs:$src))]>; 203} 204 205// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded by the 206// scheduler into a branch sequence. This has to handle all permutations of 207// selection between i32/f32/f64 on ICC and FCC. 208let usesCustomDAGSchedInserter = 1, // Expanded by the scheduler. 209 Predicates = [HasNoV9] in { // V9 has conditional moves 210 def SELECT_CC_Int_ICC 211 : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F, i32imm:$Cond), 212 "; SELECT_CC_Int_ICC PSEUDO!", 213 [(set IntRegs:$dst, (SPselecticc IntRegs:$T, IntRegs:$F, 214 imm:$Cond))]>; 215 def SELECT_CC_Int_FCC 216 : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F, i32imm:$Cond), 217 "; SELECT_CC_Int_FCC PSEUDO!", 218 [(set IntRegs:$dst, (SPselectfcc IntRegs:$T, IntRegs:$F, 219 imm:$Cond))]>; 220 def SELECT_CC_FP_ICC 221 : Pseudo<(ops FPRegs:$dst, FPRegs:$T, FPRegs:$F, i32imm:$Cond), 222 "; SELECT_CC_FP_ICC PSEUDO!", 223 [(set FPRegs:$dst, (SPselecticc FPRegs:$T, FPRegs:$F, 224 imm:$Cond))]>; 225 def SELECT_CC_FP_FCC 226 : Pseudo<(ops FPRegs:$dst, FPRegs:$T, FPRegs:$F, i32imm:$Cond), 227 "; SELECT_CC_FP_FCC PSEUDO!", 228 [(set FPRegs:$dst, (SPselectfcc FPRegs:$T, FPRegs:$F, 229 imm:$Cond))]>; 230 def SELECT_CC_DFP_ICC 231 : Pseudo<(ops DFPRegs:$dst, DFPRegs:$T, DFPRegs:$F, i32imm:$Cond), 232 "; SELECT_CC_DFP_ICC PSEUDO!", 233 [(set DFPRegs:$dst, (SPselecticc DFPRegs:$T, DFPRegs:$F, 234 imm:$Cond))]>; 235 def SELECT_CC_DFP_FCC 236 : Pseudo<(ops DFPRegs:$dst, DFPRegs:$T, DFPRegs:$F, i32imm:$Cond), 237 "; SELECT_CC_DFP_FCC PSEUDO!", 238 [(set DFPRegs:$dst, (SPselectfcc DFPRegs:$T, DFPRegs:$F, 239 imm:$Cond))]>; 240} 241 242 243// Section A.3 - Synthetic Instructions, p. 85 244// special cases of JMPL: 245let isReturn = 1, isTerminator = 1, hasDelaySlot = 1, noResults = 1 in { 246 let rd = O7.Num, rs1 = G0.Num, simm13 = 8 in 247 def RETL: F3_2<2, 0b111000, (ops), "retl", [(retflag)]>; 248} 249 250// Section B.1 - Load Integer Instructions, p. 90 251def LDSBrr : F3_1<3, 0b001001, 252 (ops IntRegs:$dst, MEMrr:$addr), 253 "ldsb [$addr], $dst", 254 [(set IntRegs:$dst, (sextload ADDRrr:$addr, i8))]>; 255def LDSBri : F3_2<3, 0b001001, 256 (ops IntRegs:$dst, MEMri:$addr), 257 "ldsb [$addr], $dst", 258 [(set IntRegs:$dst, (sextload ADDRri:$addr, i8))]>; 259def LDSHrr : F3_1<3, 0b001010, 260 (ops IntRegs:$dst, MEMrr:$addr), 261 "ldsh [$addr], $dst", 262 [(set IntRegs:$dst, (sextload ADDRrr:$addr, i16))]>; 263def LDSHri : F3_2<3, 0b001010, 264 (ops IntRegs:$dst, MEMri:$addr), 265 "ldsh [$addr], $dst", 266 [(set IntRegs:$dst, (sextload ADDRri:$addr, i16))]>; 267def LDUBrr : F3_1<3, 0b000001, 268 (ops IntRegs:$dst, MEMrr:$addr), 269 "ldub [$addr], $dst", 270 [(set IntRegs:$dst, (zextload ADDRrr:$addr, i8))]>; 271def LDUBri : F3_2<3, 0b000001, 272 (ops IntRegs:$dst, MEMri:$addr), 273 "ldub [$addr], $dst", 274 [(set IntRegs:$dst, (zextload ADDRri:$addr, i8))]>; 275def LDUHrr : F3_1<3, 0b000010, 276 (ops IntRegs:$dst, MEMrr:$addr), 277 "lduh [$addr], $dst", 278 [(set IntRegs:$dst, (zextload ADDRrr:$addr, i16))]>; 279def LDUHri : F3_2<3, 0b000010, 280 (ops IntRegs:$dst, MEMri:$addr), 281 "lduh [$addr], $dst", 282 [(set IntRegs:$dst, (zextload ADDRri:$addr, i16))]>; 283def LDrr : F3_1<3, 0b000000, 284 (ops IntRegs:$dst, MEMrr:$addr), 285 "ld [$addr], $dst", 286 [(set IntRegs:$dst, (load ADDRrr:$addr))]>; 287def LDri : F3_2<3, 0b000000, 288 (ops IntRegs:$dst, MEMri:$addr), 289 "ld [$addr], $dst", 290 [(set IntRegs:$dst, (load ADDRri:$addr))]>; 291 292// Section B.2 - Load Floating-point Instructions, p. 92 293def LDFrr : F3_1<3, 0b100000, 294 (ops FPRegs:$dst, MEMrr:$addr), 295 "ld [$addr], $dst", 296 [(set FPRegs:$dst, (load ADDRrr:$addr))]>; 297def LDFri : F3_2<3, 0b100000, 298 (ops FPRegs:$dst, MEMri:$addr), 299 "ld [$addr], $dst", 300 [(set FPRegs:$dst, (load ADDRri:$addr))]>; 301def LDDFrr : F3_1<3, 0b100011, 302 (ops DFPRegs:$dst, MEMrr:$addr), 303 "ldd [$addr], $dst", 304 [(set DFPRegs:$dst, (load ADDRrr:$addr))]>; 305def LDDFri : F3_2<3, 0b100011, 306 (ops DFPRegs:$dst, MEMri:$addr), 307 "ldd [$addr], $dst", 308 [(set DFPRegs:$dst, (load ADDRri:$addr))]>; 309 310// Section B.4 - Store Integer Instructions, p. 95 311def STBrr : F3_1<3, 0b000101, 312 (ops MEMrr:$addr, IntRegs:$src), 313 "stb $src, [$addr]", 314 [(truncstore IntRegs:$src, ADDRrr:$addr, i8)]>; 315def STBri : F3_2<3, 0b000101, 316 (ops MEMri:$addr, IntRegs:$src), 317 "stb $src, [$addr]", 318 [(truncstore IntRegs:$src, ADDRri:$addr, i8)]>; 319def STHrr : F3_1<3, 0b000110, 320 (ops MEMrr:$addr, IntRegs:$src), 321 "sth $src, [$addr]", 322 [(truncstore IntRegs:$src, ADDRrr:$addr, i16)]>; 323def STHri : F3_2<3, 0b000110, 324 (ops MEMri:$addr, IntRegs:$src), 325 "sth $src, [$addr]", 326 [(truncstore IntRegs:$src, ADDRri:$addr, i16)]>; 327def STrr : F3_1<3, 0b000100, 328 (ops MEMrr:$addr, IntRegs:$src), 329 "st $src, [$addr]", 330 [(store IntRegs:$src, ADDRrr:$addr)]>; 331def STri : F3_2<3, 0b000100, 332 (ops MEMri:$addr, IntRegs:$src), 333 "st $src, [$addr]", 334 [(store IntRegs:$src, ADDRri:$addr)]>; 335 336// Section B.5 - Store Floating-point Instructions, p. 97 337def STFrr : F3_1<3, 0b100100, 338 (ops MEMrr:$addr, FPRegs:$src), 339 "st $src, [$addr]", 340 [(store FPRegs:$src, ADDRrr:$addr)]>; 341def STFri : F3_2<3, 0b100100, 342 (ops MEMri:$addr, FPRegs:$src), 343 "st $src, [$addr]", 344 [(store FPRegs:$src, ADDRri:$addr)]>; 345def STDFrr : F3_1<3, 0b100111, 346 (ops MEMrr:$addr, DFPRegs:$src), 347 "std $src, [$addr]", 348 [(store DFPRegs:$src, ADDRrr:$addr)]>; 349def STDFri : F3_2<3, 0b100111, 350 (ops MEMri:$addr, DFPRegs:$src), 351 "std $src, [$addr]", 352 [(store DFPRegs:$src, ADDRri:$addr)]>; 353 354// Section B.9 - SETHI Instruction, p. 104 355def SETHIi: F2_1<0b100, 356 (ops IntRegs:$dst, i32imm:$src), 357 "sethi $src, $dst", 358 [(set IntRegs:$dst, SETHIimm:$src)]>; 359 360// Section B.10 - NOP Instruction, p. 105 361// (It's a special case of SETHI) 362let rd = 0, imm22 = 0 in 363 def NOP : F2_1<0b100, (ops), "nop", []>; 364 365// Section B.11 - Logical Instructions, p. 106 366def ANDrr : F3_1<2, 0b000001, 367 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 368 "and $b, $c, $dst", 369 [(set IntRegs:$dst, (and IntRegs:$b, IntRegs:$c))]>; 370def ANDri : F3_2<2, 0b000001, 371 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 372 "and $b, $c, $dst", 373 [(set IntRegs:$dst, (and IntRegs:$b, simm13:$c))]>; 374def ANDNrr : F3_1<2, 0b000101, 375 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 376 "andn $b, $c, $dst", 377 [(set IntRegs:$dst, (and IntRegs:$b, (not IntRegs:$c)))]>; 378def ANDNri : F3_2<2, 0b000101, 379 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 380 "andn $b, $c, $dst", []>; 381def ORrr : F3_1<2, 0b000010, 382 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 383 "or $b, $c, $dst", 384 [(set IntRegs:$dst, (or IntRegs:$b, IntRegs:$c))]>; 385def ORri : F3_2<2, 0b000010, 386 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 387 "or $b, $c, $dst", 388 [(set IntRegs:$dst, (or IntRegs:$b, simm13:$c))]>; 389def ORNrr : F3_1<2, 0b000110, 390 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 391 "orn $b, $c, $dst", 392 [(set IntRegs:$dst, (or IntRegs:$b, (not IntRegs:$c)))]>; 393def ORNri : F3_2<2, 0b000110, 394 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 395 "orn $b, $c, $dst", []>; 396def XORrr : F3_1<2, 0b000011, 397 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 398 "xor $b, $c, $dst", 399 [(set IntRegs:$dst, (xor IntRegs:$b, IntRegs:$c))]>; 400def XORri : F3_2<2, 0b000011, 401 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 402 "xor $b, $c, $dst", 403 [(set IntRegs:$dst, (xor IntRegs:$b, simm13:$c))]>; 404def XNORrr : F3_1<2, 0b000111, 405 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 406 "xnor $b, $c, $dst", 407 [(set IntRegs:$dst, (not (xor IntRegs:$b, IntRegs:$c)))]>; 408def XNORri : F3_2<2, 0b000111, 409 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 410 "xnor $b, $c, $dst", []>; 411 412// Section B.12 - Shift Instructions, p. 107 413def SLLrr : F3_1<2, 0b100101, 414 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 415 "sll $b, $c, $dst", 416 [(set IntRegs:$dst, (shl IntRegs:$b, IntRegs:$c))]>; 417def SLLri : F3_2<2, 0b100101, 418 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 419 "sll $b, $c, $dst", 420 [(set IntRegs:$dst, (shl IntRegs:$b, simm13:$c))]>; 421def SRLrr : F3_1<2, 0b100110, 422 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 423 "srl $b, $c, $dst", 424 [(set IntRegs:$dst, (srl IntRegs:$b, IntRegs:$c))]>; 425def SRLri : F3_2<2, 0b100110, 426 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 427 "srl $b, $c, $dst", 428 [(set IntRegs:$dst, (srl IntRegs:$b, simm13:$c))]>; 429def SRArr : F3_1<2, 0b100111, 430 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 431 "sra $b, $c, $dst", 432 [(set IntRegs:$dst, (sra IntRegs:$b, IntRegs:$c))]>; 433def SRAri : F3_2<2, 0b100111, 434 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 435 "sra $b, $c, $dst", 436 [(set IntRegs:$dst, (sra IntRegs:$b, simm13:$c))]>; 437 438// Section B.13 - Add Instructions, p. 108 439def ADDrr : F3_1<2, 0b000000, 440 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 441 "add $b, $c, $dst", 442 [(set IntRegs:$dst, (add IntRegs:$b, IntRegs:$c))]>; 443def ADDri : F3_2<2, 0b000000, 444 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 445 "add $b, $c, $dst", 446 [(set IntRegs:$dst, (add IntRegs:$b, simm13:$c))]>; 447def ADDCCrr : F3_1<2, 0b010000, 448 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 449 "addcc $b, $c, $dst", []>; 450def ADDCCri : F3_2<2, 0b010000, 451 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 452 "addcc $b, $c, $dst", []>; 453def ADDXrr : F3_1<2, 0b001000, 454 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 455 "addx $b, $c, $dst", []>; 456def ADDXri : F3_2<2, 0b001000, 457 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 458 "addx $b, $c, $dst", []>; 459 460// Section B.15 - Subtract Instructions, p. 110 461def SUBrr : F3_1<2, 0b000100, 462 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 463 "sub $b, $c, $dst", 464 [(set IntRegs:$dst, (sub IntRegs:$b, IntRegs:$c))]>; 465def SUBri : F3_2<2, 0b000100, 466 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 467 "sub $b, $c, $dst", 468 [(set IntRegs:$dst, (sub IntRegs:$b, simm13:$c))]>; 469def SUBXrr : F3_1<2, 0b001100, 470 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 471 "subx $b, $c, $dst", []>; 472def SUBXri : F3_2<2, 0b001100, 473 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 474 "subx $b, $c, $dst", []>; 475def SUBCCrr : F3_1<2, 0b010100, 476 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 477 "subcc $b, $c, $dst", 478 [(set IntRegs:$dst, (SPcmpicc IntRegs:$b, IntRegs:$c))]>; 479def SUBCCri : F3_2<2, 0b010100, 480 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 481 "subcc $b, $c, $dst", 482 [(set IntRegs:$dst, (SPcmpicc IntRegs:$b, simm13:$c))]>; 483def SUBXCCrr: F3_1<2, 0b011100, 484 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 485 "subxcc $b, $c, $dst", []>; 486 487// Section B.18 - Multiply Instructions, p. 113 488def UMULrr : F3_1<2, 0b001010, 489 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 490 "umul $b, $c, $dst", []>; 491def UMULri : F3_2<2, 0b001010, 492 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 493 "umul $b, $c, $dst", []>; 494 495def SMULrr : F3_1<2, 0b001011, 496 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 497 "smul $b, $c, $dst", 498 [(set IntRegs:$dst, (mul IntRegs:$b, IntRegs:$c))]>; 499def SMULri : F3_2<2, 0b001011, 500 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 501 "smul $b, $c, $dst", 502 [(set IntRegs:$dst, (mul IntRegs:$b, simm13:$c))]>; 503 504/* 505//===------------------------- 506// Sparc Example 507defm intinst<id OPC1, id OPC2, bits Opc, string asmstr, SDNode code> { 508 def OPC1 : F3_1<2, Opc, asmstr, (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 509 [(set IntRegs:$dst, (code IntRegs:$b, IntRegs:$c))]>; 510 def OPC2 : F3_2<2, Opc, asmstr, (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 511 [(set IntRegs:$dst, (code IntRegs:$b, simm13:$c))]>; 512} 513defm intinst_np<id OPC1, id OPC2, bits Opc, string asmstr> { 514 def OPC1 : F3_1<2, Opc, asmstr, (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 515 []>; 516 def OPC2 : F3_2<2, Opc, asmstr, (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 517 []>; 518} 519 520def intinstnp< ADDXrr, ADDXri, 0b001000, "addx $b, $c, $dst">; 521def intinst < SUBrr, SUBri, 0b000100, "sub $b, $c, $dst", sub>; 522def intinstnp< SUBXrr, SUBXri, 0b001100, "subx $b, $c, $dst">; 523def intinst <SUBCCrr, SUBCCri, 0b010100, "subcc $b, $c, $dst", SPcmpicc>; 524def intinst < SMULrr, SMULri, 0b001011, "smul $b, $c, $dst", mul>; 525 526//===------------------------- 527// X86 Example 528defm cmov32<id OPC1, id OPC2, int opc, string asmstr, PatLeaf cond> { 529 def OPC1 : I<opc, MRMSrcReg, (ops R32:$dst, R32:$src1, R32:$src2), 530 asmstr+" {$src2, $dst|$dst, $src2}", 531 [(set R32:$dst, (X86cmov R32:$src1, R32:$src2, cond))]>, TB; 532 def OPC2 : I<opc, MRMSrcMem, (ops R32:$dst, R32:$src1, i32mem:$src2), 533 asmstr+" {$src2, $dst|$dst, $src2}", 534 [(set R32:$dst, (X86cmov R32:$src1, 535 (loadi32 addr:$src2), cond))]>, TB; 536} 537 538def cmov<CMOVL32rr, CMOVL32rm, 0x4C, "cmovl", X86_COND_L>; 539def cmov<CMOVB32rr, CMOVB32rm, 0x4C, "cmovb", X86_COND_B>; 540 541//===------------------------- 542// PPC Example 543 544def fpunop<id OPC1, id OPC2, id FORM, int op1, int op2, int op3, string asmstr, 545 SDNode code> { 546 def OPC1 : FORM<op1, op3, (ops F4RC:$frD, F4RC:$frB), 547 asmstr+" $frD, $frB", FPGeneral, 548 [(set F4RC:$frD, (code F4RC:$frB))]>; 549 def OPC2 : FORM<op2, op3, (ops F8RC:$frD, F8RC:$frB), 550 asmstr+" $frD, $frB", FPGeneral, 551 [(set F8RC:$frD, (code F8RC:$frB))]>; 552} 553 554def fpunop< FABSS, FABSD, XForm_26, 63, 63, 264, "fabs", fabs>; 555def fpunop<FNABSS, FNABSD, XForm_26, 63, 63, 136, "fnabs", fnabs>; 556def fpunop< FNEGS, FNEGD, XForm_26, 63, 63, 40, "fneg", fneg>; 557*/ 558 559// Section B.19 - Divide Instructions, p. 115 560def UDIVrr : F3_1<2, 0b001110, 561 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 562 "udiv $b, $c, $dst", []>; 563def UDIVri : F3_2<2, 0b001110, 564 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 565 "udiv $b, $c, $dst", []>; 566def SDIVrr : F3_1<2, 0b001111, 567 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 568 "sdiv $b, $c, $dst", []>; 569def SDIVri : F3_2<2, 0b001111, 570 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 571 "sdiv $b, $c, $dst", []>; 572 573// Section B.20 - SAVE and RESTORE, p. 117 574def SAVErr : F3_1<2, 0b111100, 575 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 576 "save $b, $c, $dst", []>; 577def SAVEri : F3_2<2, 0b111100, 578 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 579 "save $b, $c, $dst", []>; 580def RESTORErr : F3_1<2, 0b111101, 581 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), 582 "restore $b, $c, $dst", []>; 583def RESTOREri : F3_2<2, 0b111101, 584 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), 585 "restore $b, $c, $dst", []>; 586 587// Section B.21 - Branch on Integer Condition Codes Instructions, p. 119 588 589// conditional branch class: 590class BranchSP<bits<4> cc, dag ops, string asmstr, list<dag> pattern> 591 : F2_2<cc, 0b010, ops, asmstr, pattern> { 592 let isBranch = 1; 593 let isTerminator = 1; 594 let hasDelaySlot = 1; 595 let noResults = 1; 596} 597 598let isBarrier = 1 in 599 def BA : BranchSP<0b1000, (ops brtarget:$dst), 600 "ba $dst", 601 [(br bb:$dst)]>; 602 603// FIXME: the encoding for the JIT should look at the condition field. 604def BCOND : BranchSP<0, (ops brtarget:$dst, CCOp:$cc), 605 "b$cc $dst", 606 [(SPbricc bb:$dst, imm:$cc)]>; 607 608 609// Section B.22 - Branch on Floating-point Condition Codes Instructions, p. 121 610 611// floating-point conditional branch class: 612class FPBranchSP<bits<4> cc, dag ops, string asmstr, list<dag> pattern> 613 : F2_2<cc, 0b110, ops, asmstr, pattern> { 614 let isBranch = 1; 615 let isTerminator = 1; 616 let hasDelaySlot = 1; 617 let noResults = 1; 618} 619 620// FIXME: the encoding for the JIT should look at the condition field. 621def FBCOND : FPBranchSP<0, (ops brtarget:$dst, CCOp:$cc), 622 "fb$cc $dst", 623 [(SPbrfcc bb:$dst, imm:$cc)]>; 624 625 626// Section B.24 - Call and Link Instruction, p. 125 627// This is the only Format 1 instruction 628let Uses = [O0, O1, O2, O3, O4, O5], 629 hasDelaySlot = 1, isCall = 1, noResults = 1, 630 Defs = [O0, O1, O2, O3, O4, O5, O7, G1, G2, G3, G4, G5, G6, G7, 631 D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15] in { 632 def CALL : InstSP<(ops calltarget:$dst), 633 "call $dst", []> { 634 bits<30> disp; 635 let op = 1; 636 let Inst{29-0} = disp; 637 } 638 639 // indirect calls 640 def JMPLrr : F3_1<2, 0b111000, 641 (ops MEMrr:$ptr), 642 "call $ptr", 643 [(call ADDRrr:$ptr)]>; 644 def JMPLri : F3_2<2, 0b111000, 645 (ops MEMri:$ptr), 646 "call $ptr", 647 [(call ADDRri:$ptr)]>; 648} 649 650// Section B.28 - Read State Register Instructions 651def RDY : F3_1<2, 0b101000, 652 (ops IntRegs:$dst), 653 "rd %y, $dst", []>; 654 655// Section B.29 - Write State Register Instructions 656def WRYrr : F3_1<2, 0b110000, 657 (ops IntRegs:$b, IntRegs:$c), 658 "wr $b, $c, %y", []>; 659def WRYri : F3_2<2, 0b110000, 660 (ops IntRegs:$b, i32imm:$c), 661 "wr $b, $c, %y", []>; 662 663// Convert Integer to Floating-point Instructions, p. 141 664def FITOS : F3_3<2, 0b110100, 0b011000100, 665 (ops FPRegs:$dst, FPRegs:$src), 666 "fitos $src, $dst", 667 [(set FPRegs:$dst, (SPitof FPRegs:$src))]>; 668def FITOD : F3_3<2, 0b110100, 0b011001000, 669 (ops DFPRegs:$dst, FPRegs:$src), 670 "fitod $src, $dst", 671 [(set DFPRegs:$dst, (SPitof FPRegs:$src))]>; 672 673// Convert Floating-point to Integer Instructions, p. 142 674def FSTOI : F3_3<2, 0b110100, 0b011010001, 675 (ops FPRegs:$dst, FPRegs:$src), 676 "fstoi $src, $dst", 677 [(set FPRegs:$dst, (SPftoi FPRegs:$src))]>; 678def FDTOI : F3_3<2, 0b110100, 0b011010010, 679 (ops FPRegs:$dst, DFPRegs:$src), 680 "fdtoi $src, $dst", 681 [(set FPRegs:$dst, (SPftoi DFPRegs:$src))]>; 682 683// Convert between Floating-point Formats Instructions, p. 143 684def FSTOD : F3_3<2, 0b110100, 0b011001001, 685 (ops DFPRegs:$dst, FPRegs:$src), 686 "fstod $src, $dst", 687 [(set DFPRegs:$dst, (fextend FPRegs:$src))]>; 688def FDTOS : F3_3<2, 0b110100, 0b011000110, 689 (ops FPRegs:$dst, DFPRegs:$src), 690 "fdtos $src, $dst", 691 [(set FPRegs:$dst, (fround DFPRegs:$src))]>; 692 693// Floating-point Move Instructions, p. 144 694def FMOVS : F3_3<2, 0b110100, 0b000000001, 695 (ops FPRegs:$dst, FPRegs:$src), 696 "fmovs $src, $dst", []>; 697def FNEGS : F3_3<2, 0b110100, 0b000000101, 698 (ops FPRegs:$dst, FPRegs:$src), 699 "fnegs $src, $dst", 700 [(set FPRegs:$dst, (fneg FPRegs:$src))]>; 701def FABSS : F3_3<2, 0b110100, 0b000001001, 702 (ops FPRegs:$dst, FPRegs:$src), 703 "fabss $src, $dst", 704 [(set FPRegs:$dst, (fabs FPRegs:$src))]>; 705 706 707// Floating-point Square Root Instructions, p.145 708def FSQRTS : F3_3<2, 0b110100, 0b000101001, 709 (ops FPRegs:$dst, FPRegs:$src), 710 "fsqrts $src, $dst", 711 [(set FPRegs:$dst, (fsqrt FPRegs:$src))]>; 712def FSQRTD : F3_3<2, 0b110100, 0b000101010, 713 (ops DFPRegs:$dst, DFPRegs:$src), 714 "fsqrtd $src, $dst", 715 [(set DFPRegs:$dst, (fsqrt DFPRegs:$src))]>; 716 717 718 719// Floating-point Add and Subtract Instructions, p. 146 720def FADDS : F3_3<2, 0b110100, 0b001000001, 721 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2), 722 "fadds $src1, $src2, $dst", 723 [(set FPRegs:$dst, (fadd FPRegs:$src1, FPRegs:$src2))]>; 724def FADDD : F3_3<2, 0b110100, 0b001000010, 725 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2), 726 "faddd $src1, $src2, $dst", 727 [(set DFPRegs:$dst, (fadd DFPRegs:$src1, DFPRegs:$src2))]>; 728def FSUBS : F3_3<2, 0b110100, 0b001000101, 729 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2), 730 "fsubs $src1, $src2, $dst", 731 [(set FPRegs:$dst, (fsub FPRegs:$src1, FPRegs:$src2))]>; 732def FSUBD : F3_3<2, 0b110100, 0b001000110, 733 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2), 734 "fsubd $src1, $src2, $dst", 735 [(set DFPRegs:$dst, (fsub DFPRegs:$src1, DFPRegs:$src2))]>; 736 737// Floating-point Multiply and Divide Instructions, p. 147 738def FMULS : F3_3<2, 0b110100, 0b001001001, 739 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2), 740 "fmuls $src1, $src2, $dst", 741 [(set FPRegs:$dst, (fmul FPRegs:$src1, FPRegs:$src2))]>; 742def FMULD : F3_3<2, 0b110100, 0b001001010, 743 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2), 744 "fmuld $src1, $src2, $dst", 745 [(set DFPRegs:$dst, (fmul DFPRegs:$src1, DFPRegs:$src2))]>; 746def FSMULD : F3_3<2, 0b110100, 0b001101001, 747 (ops DFPRegs:$dst, FPRegs:$src1, FPRegs:$src2), 748 "fsmuld $src1, $src2, $dst", 749 [(set DFPRegs:$dst, (fmul (fextend FPRegs:$src1), 750 (fextend FPRegs:$src2)))]>; 751def FDIVS : F3_3<2, 0b110100, 0b001001101, 752 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2), 753 "fdivs $src1, $src2, $dst", 754 [(set FPRegs:$dst, (fdiv FPRegs:$src1, FPRegs:$src2))]>; 755def FDIVD : F3_3<2, 0b110100, 0b001001110, 756 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2), 757 "fdivd $src1, $src2, $dst", 758 [(set DFPRegs:$dst, (fdiv DFPRegs:$src1, DFPRegs:$src2))]>; 759 760// Floating-point Compare Instructions, p. 148 761// Note: the 2nd template arg is different for these guys. 762// Note 2: the result of a FCMP is not available until the 2nd cycle 763// after the instr is retired, but there is no interlock. This behavior 764// is modelled with a forced noop after the instruction. 765def FCMPS : F3_3<2, 0b110101, 0b001010001, 766 (ops FPRegs:$src1, FPRegs:$src2), 767 "fcmps $src1, $src2\n\tnop", 768 [(SPcmpfcc FPRegs:$src1, FPRegs:$src2)]>; 769def FCMPD : F3_3<2, 0b110101, 0b001010010, 770 (ops DFPRegs:$src1, DFPRegs:$src2), 771 "fcmpd $src1, $src2\n\tnop", 772 [(SPcmpfcc DFPRegs:$src1, DFPRegs:$src2)]>; 773 774 775//===----------------------------------------------------------------------===// 776// V9 Instructions 777//===----------------------------------------------------------------------===// 778 779// V9 Conditional Moves. 780let Predicates = [HasV9], isTwoAddress = 1 in { 781 // Move Integer Register on Condition (MOVcc) p. 194 of the V9 manual. 782 // FIXME: Add instruction encodings for the JIT some day. 783 def MOVICCrr 784 : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F, CCOp:$cc), 785 "mov$cc %icc, $F, $dst", 786 [(set IntRegs:$dst, 787 (SPselecticc IntRegs:$F, IntRegs:$T, imm:$cc))]>; 788 def MOVICCri 789 : Pseudo<(ops IntRegs:$dst, IntRegs:$T, i32imm:$F, CCOp:$cc), 790 "mov$cc %icc, $F, $dst", 791 [(set IntRegs:$dst, 792 (SPselecticc simm11:$F, IntRegs:$T, imm:$cc))]>; 793 794 def MOVFCCrr 795 : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F, CCOp:$cc), 796 "mov$cc %fcc0, $F, $dst", 797 [(set IntRegs:$dst, 798 (SPselectfcc IntRegs:$F, IntRegs:$T, imm:$cc))]>; 799 def MOVFCCri 800 : Pseudo<(ops IntRegs:$dst, IntRegs:$T, i32imm:$F, CCOp:$cc), 801 "mov$cc %fcc0, $F, $dst", 802 [(set IntRegs:$dst, 803 (SPselectfcc simm11:$F, IntRegs:$T, imm:$cc))]>; 804 805 def FMOVS_ICC 806 : Pseudo<(ops FPRegs:$dst, FPRegs:$T, FPRegs:$F, CCOp:$cc), 807 "fmovs$cc %icc, $F, $dst", 808 [(set FPRegs:$dst, 809 (SPselecticc FPRegs:$F, FPRegs:$T, imm:$cc))]>; 810 def FMOVD_ICC 811 : Pseudo<(ops DFPRegs:$dst, DFPRegs:$T, DFPRegs:$F, CCOp:$cc), 812 "fmovd$cc %icc, $F, $dst", 813 [(set DFPRegs:$dst, 814 (SPselecticc DFPRegs:$F, DFPRegs:$T, imm:$cc))]>; 815 def FMOVS_FCC 816 : Pseudo<(ops FPRegs:$dst, FPRegs:$T, FPRegs:$F, CCOp:$cc), 817 "fmovs$cc %fcc0, $F, $dst", 818 [(set FPRegs:$dst, 819 (SPselectfcc FPRegs:$F, FPRegs:$T, imm:$cc))]>; 820 def FMOVD_FCC 821 : Pseudo<(ops DFPRegs:$dst, DFPRegs:$T, DFPRegs:$F, CCOp:$cc), 822 "fmovd$cc %fcc0, $F, $dst", 823 [(set DFPRegs:$dst, 824 (SPselectfcc DFPRegs:$F, DFPRegs:$T, imm:$cc))]>; 825 826} 827 828// Floating-Point Move Instructions, p. 164 of the V9 manual. 829let Predicates = [HasV9] in { 830 def FMOVD : F3_3<2, 0b110100, 0b000000010, 831 (ops DFPRegs:$dst, DFPRegs:$src), 832 "fmovd $src, $dst", []>; 833 def FNEGD : F3_3<2, 0b110100, 0b000000110, 834 (ops DFPRegs:$dst, DFPRegs:$src), 835 "fnegd $src, $dst", 836 [(set DFPRegs:$dst, (fneg DFPRegs:$src))]>; 837 def FABSD : F3_3<2, 0b110100, 0b000001010, 838 (ops DFPRegs:$dst, DFPRegs:$src), 839 "fabsd $src, $dst", 840 [(set DFPRegs:$dst, (fabs DFPRegs:$src))]>; 841} 842 843// POPCrr - This does a ctpop of a 64-bit register. As such, we have to clear 844// the top 32-bits before using it. To do this clearing, we use a SLLri X,0. 845def POPCrr : F3_1<2, 0b101110, 846 (ops IntRegs:$dst, IntRegs:$src), 847 "popc $src, $dst", []>, Requires<[HasV9]>; 848def : Pat<(ctpop IntRegs:$src), 849 (POPCrr (SLLri IntRegs:$src, 0))>; 850 851//===----------------------------------------------------------------------===// 852// Non-Instruction Patterns 853//===----------------------------------------------------------------------===// 854 855// Small immediates. 856def : Pat<(i32 simm13:$val), 857 (ORri G0, imm:$val)>; 858// Arbitrary immediates. 859def : Pat<(i32 imm:$val), 860 (ORri (SETHIi (HI22 imm:$val)), (LO10 imm:$val))>; 861 862// Global addresses, constant pool entries 863def : Pat<(SPhi tglobaladdr:$in), (SETHIi tglobaladdr:$in)>; 864def : Pat<(SPlo tglobaladdr:$in), (ORri G0, tglobaladdr:$in)>; 865def : Pat<(SPhi tconstpool:$in), (SETHIi tconstpool:$in)>; 866def : Pat<(SPlo tconstpool:$in), (ORri G0, tconstpool:$in)>; 867 868// Add reg, lo. This is used when taking the addr of a global/constpool entry. 869def : Pat<(add IntRegs:$r, (SPlo tglobaladdr:$in)), 870 (ADDri IntRegs:$r, tglobaladdr:$in)>; 871def : Pat<(add IntRegs:$r, (SPlo tconstpool:$in)), 872 (ADDri IntRegs:$r, tconstpool:$in)>; 873 874 875// Calls: 876def : Pat<(call tglobaladdr:$dst), 877 (CALL tglobaladdr:$dst)>; 878def : Pat<(call externalsym:$dst), 879 (CALL externalsym:$dst)>; 880 881def : Pat<(ret), (RETL)>; 882 883// Map integer extload's to zextloads. 884def : Pat<(i32 (extload ADDRrr:$src, i1)), (LDUBrr ADDRrr:$src)>; 885def : Pat<(i32 (extload ADDRri:$src, i1)), (LDUBri ADDRri:$src)>; 886def : Pat<(i32 (extload ADDRrr:$src, i8)), (LDUBrr ADDRrr:$src)>; 887def : Pat<(i32 (extload ADDRri:$src, i8)), (LDUBri ADDRri:$src)>; 888def : Pat<(i32 (extload ADDRrr:$src, i16)), (LDUHrr ADDRrr:$src)>; 889def : Pat<(i32 (extload ADDRri:$src, i16)), (LDUHri ADDRri:$src)>; 890 891// zextload bool -> zextload byte 892def : Pat<(i32 (zextload ADDRrr:$src, i1)), (LDUBrr ADDRrr:$src)>; 893def : Pat<(i32 (zextload ADDRri:$src, i1)), (LDUBri ADDRri:$src)>; 894 895// truncstore bool -> truncstore byte. 896def : Pat<(truncstore IntRegs:$src, ADDRrr:$addr, i1), 897 (STBrr ADDRrr:$addr, IntRegs:$src)>; 898def : Pat<(truncstore IntRegs:$src, ADDRri:$addr, i1), 899 (STBri ADDRri:$addr, IntRegs:$src)>; 900