SparcInstrInfo.td revision ff96efee98f8a06e8fdf29d34843659932a83e95
1//===-- SparcInstrInfo.td - Target Description for Sparc Target -----------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the Sparc instructions in TableGen format. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// Instruction format superclass 16//===----------------------------------------------------------------------===// 17 18include "SparcInstrFormats.td" 19 20//===----------------------------------------------------------------------===// 21// Feature predicates. 22//===----------------------------------------------------------------------===// 23 24// True when generating 32-bit code. 25def Is32Bit : Predicate<"!Subtarget.is64Bit()">; 26 27// True when generating 64-bit code. This also implies HasV9. 28def Is64Bit : Predicate<"Subtarget.is64Bit()">; 29 30// HasV9 - This predicate is true when the target processor supports V9 31// instructions. Note that the machine may be running in 32-bit mode. 32def HasV9 : Predicate<"Subtarget.isV9()">; 33 34// HasNoV9 - This predicate is true when the target doesn't have V9 35// instructions. Use of this is just a hack for the isel not having proper 36// costs for V8 instructions that are more expensive than their V9 ones. 37def HasNoV9 : Predicate<"!Subtarget.isV9()">; 38 39// HasVIS - This is true when the target processor has VIS extensions. 40def HasVIS : Predicate<"Subtarget.isVIS()">; 41 42// HasHardQuad - This is true when the target processor supports quad floating 43// point instructions. 44def HasHardQuad : Predicate<"Subtarget.hasHardQuad()">; 45 46// UseDeprecatedInsts - This predicate is true when the target processor is a 47// V8, or when it is V9 but the V8 deprecated instructions are efficient enough 48// to use when appropriate. In either of these cases, the instruction selector 49// will pick deprecated instructions. 50def UseDeprecatedInsts : Predicate<"Subtarget.useDeprecatedV8Instructions()">; 51 52//===----------------------------------------------------------------------===// 53// Instruction Pattern Stuff 54//===----------------------------------------------------------------------===// 55 56def simm11 : PatLeaf<(imm), [{ return isInt<11>(N->getSExtValue()); }]>; 57 58def simm13 : PatLeaf<(imm), [{ return isInt<13>(N->getSExtValue()); }]>; 59 60def LO10 : SDNodeXForm<imm, [{ 61 return CurDAG->getTargetConstant((unsigned)N->getZExtValue() & 1023, 62 MVT::i32); 63}]>; 64 65def HI22 : SDNodeXForm<imm, [{ 66 // Transformation function: shift the immediate value down into the low bits. 67 return CurDAG->getTargetConstant((unsigned)N->getZExtValue() >> 10, MVT::i32); 68}]>; 69 70def SETHIimm : PatLeaf<(imm), [{ 71 return isShiftedUInt<22, 10>(N->getZExtValue()); 72}], HI22>; 73 74// Addressing modes. 75def ADDRrr : ComplexPattern<iPTR, 2, "SelectADDRrr", [], []>; 76def ADDRri : ComplexPattern<iPTR, 2, "SelectADDRri", [frameindex], []>; 77 78// Address operands 79def MEMrr : Operand<iPTR> { 80 let PrintMethod = "printMemOperand"; 81 let MIOperandInfo = (ops ptr_rc, ptr_rc); 82} 83def MEMri : Operand<iPTR> { 84 let PrintMethod = "printMemOperand"; 85 let MIOperandInfo = (ops ptr_rc, i32imm); 86} 87 88def TLSSym : Operand<iPTR>; 89 90// Branch targets have OtherVT type. 91def brtarget : Operand<OtherVT>; 92def calltarget : Operand<i32>; 93 94// Operand for printing out a condition code. 95let PrintMethod = "printCCOperand" in 96 def CCOp : Operand<i32>; 97 98def SDTSPcmpicc : 99SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>]>; 100def SDTSPcmpfcc : 101SDTypeProfile<0, 2, [SDTCisFP<0>, SDTCisSameAs<0, 1>]>; 102def SDTSPbrcc : 103SDTypeProfile<0, 2, [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>; 104def SDTSPselectcc : 105SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>]>; 106def SDTSPFTOI : 107SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisFP<1>]>; 108def SDTSPITOF : 109SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f32>]>; 110 111def SDTSPtlsadd : 112SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>, SDTCisPtrTy<2>]>; 113def SDTSPtlsld : 114SDTypeProfile<1, 2, [SDTCisPtrTy<0>, SDTCisPtrTy<1>]>; 115 116def SPcmpicc : SDNode<"SPISD::CMPICC", SDTSPcmpicc, [SDNPOutGlue]>; 117def SPcmpfcc : SDNode<"SPISD::CMPFCC", SDTSPcmpfcc, [SDNPOutGlue]>; 118def SPbricc : SDNode<"SPISD::BRICC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>; 119def SPbrxcc : SDNode<"SPISD::BRXCC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>; 120def SPbrfcc : SDNode<"SPISD::BRFCC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>; 121 122def SPhi : SDNode<"SPISD::Hi", SDTIntUnaryOp>; 123def SPlo : SDNode<"SPISD::Lo", SDTIntUnaryOp>; 124 125def SPftoi : SDNode<"SPISD::FTOI", SDTSPFTOI>; 126def SPitof : SDNode<"SPISD::ITOF", SDTSPITOF>; 127 128def SPselecticc : SDNode<"SPISD::SELECT_ICC", SDTSPselectcc, [SDNPInGlue]>; 129def SPselectxcc : SDNode<"SPISD::SELECT_XCC", SDTSPselectcc, [SDNPInGlue]>; 130def SPselectfcc : SDNode<"SPISD::SELECT_FCC", SDTSPselectcc, [SDNPInGlue]>; 131 132// These are target-independent nodes, but have target-specific formats. 133def SDT_SPCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>; 134def SDT_SPCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, 135 SDTCisVT<1, i32> ]>; 136 137def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_SPCallSeqStart, 138 [SDNPHasChain, SDNPOutGlue]>; 139def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_SPCallSeqEnd, 140 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 141 142def SDT_SPCall : SDTypeProfile<0, -1, [SDTCisVT<0, i32>]>; 143def call : SDNode<"SPISD::CALL", SDT_SPCall, 144 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 145 SDNPVariadic]>; 146 147def SDT_SPRet : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>; 148def retflag : SDNode<"SPISD::RET_FLAG", SDT_SPRet, 149 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 150 151def flushw : SDNode<"SPISD::FLUSHW", SDTNone, 152 [SDNPHasChain, SDNPSideEffect, SDNPMayStore]>; 153 154def tlsadd : SDNode<"SPISD::TLS_ADD", SDTSPtlsadd>; 155def tlsld : SDNode<"SPISD::TLS_LD", SDTSPtlsld>; 156def tlscall : SDNode<"SPISD::TLS_CALL", SDT_SPCall, 157 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 158 SDNPVariadic]>; 159 160def getPCX : Operand<i32> { 161 let PrintMethod = "printGetPCX"; 162} 163 164//===----------------------------------------------------------------------===// 165// SPARC Flag Conditions 166//===----------------------------------------------------------------------===// 167 168// Note that these values must be kept in sync with the CCOp::CondCode enum 169// values. 170class ICC_VAL<int N> : PatLeaf<(i32 N)>; 171def ICC_NE : ICC_VAL< 9>; // Not Equal 172def ICC_E : ICC_VAL< 1>; // Equal 173def ICC_G : ICC_VAL<10>; // Greater 174def ICC_LE : ICC_VAL< 2>; // Less or Equal 175def ICC_GE : ICC_VAL<11>; // Greater or Equal 176def ICC_L : ICC_VAL< 3>; // Less 177def ICC_GU : ICC_VAL<12>; // Greater Unsigned 178def ICC_LEU : ICC_VAL< 4>; // Less or Equal Unsigned 179def ICC_CC : ICC_VAL<13>; // Carry Clear/Great or Equal Unsigned 180def ICC_CS : ICC_VAL< 5>; // Carry Set/Less Unsigned 181def ICC_POS : ICC_VAL<14>; // Positive 182def ICC_NEG : ICC_VAL< 6>; // Negative 183def ICC_VC : ICC_VAL<15>; // Overflow Clear 184def ICC_VS : ICC_VAL< 7>; // Overflow Set 185 186class FCC_VAL<int N> : PatLeaf<(i32 N)>; 187def FCC_U : FCC_VAL<23>; // Unordered 188def FCC_G : FCC_VAL<22>; // Greater 189def FCC_UG : FCC_VAL<21>; // Unordered or Greater 190def FCC_L : FCC_VAL<20>; // Less 191def FCC_UL : FCC_VAL<19>; // Unordered or Less 192def FCC_LG : FCC_VAL<18>; // Less or Greater 193def FCC_NE : FCC_VAL<17>; // Not Equal 194def FCC_E : FCC_VAL<25>; // Equal 195def FCC_UE : FCC_VAL<24>; // Unordered or Equal 196def FCC_GE : FCC_VAL<25>; // Greater or Equal 197def FCC_UGE : FCC_VAL<26>; // Unordered or Greater or Equal 198def FCC_LE : FCC_VAL<27>; // Less or Equal 199def FCC_ULE : FCC_VAL<28>; // Unordered or Less or Equal 200def FCC_O : FCC_VAL<29>; // Ordered 201 202//===----------------------------------------------------------------------===// 203// Instruction Class Templates 204//===----------------------------------------------------------------------===// 205 206/// F3_12 multiclass - Define a normal F3_1/F3_2 pattern in one shot. 207multiclass F3_12<string OpcStr, bits<6> Op3Val, SDNode OpNode> { 208 def rr : F3_1<2, Op3Val, 209 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c), 210 !strconcat(OpcStr, " $b, $c, $dst"), 211 [(set i32:$dst, (OpNode i32:$b, i32:$c))]>; 212 def ri : F3_2<2, Op3Val, 213 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c), 214 !strconcat(OpcStr, " $b, $c, $dst"), 215 [(set i32:$dst, (OpNode i32:$b, (i32 simm13:$c)))]>; 216} 217 218/// F3_12np multiclass - Define a normal F3_1/F3_2 pattern in one shot, with no 219/// pattern. 220multiclass F3_12np<string OpcStr, bits<6> Op3Val> { 221 def rr : F3_1<2, Op3Val, 222 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c), 223 !strconcat(OpcStr, " $b, $c, $dst"), []>; 224 def ri : F3_2<2, Op3Val, 225 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c), 226 !strconcat(OpcStr, " $b, $c, $dst"), []>; 227} 228 229//===----------------------------------------------------------------------===// 230// Instructions 231//===----------------------------------------------------------------------===// 232 233// Pseudo instructions. 234class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern> 235 : InstSP<outs, ins, asmstr, pattern>; 236 237// GETPCX for PIC 238let Defs = [O7] in { 239 def GETPCX : Pseudo<(outs getPCX:$getpcseq), (ins), "$getpcseq", [] >; 240} 241 242let Defs = [O6], Uses = [O6] in { 243def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt), 244 "!ADJCALLSTACKDOWN $amt", 245 [(callseq_start timm:$amt)]>; 246def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2), 247 "!ADJCALLSTACKUP $amt1", 248 [(callseq_end timm:$amt1, timm:$amt2)]>; 249} 250 251let hasSideEffects = 1, mayStore = 1 in { 252 let rd = 0, rs1 = 0, rs2 = 0 in 253 def FLUSHW : F3_1<0b10, 0b101011, (outs), (ins), 254 "flushw", 255 [(flushw)]>, Requires<[HasV9]>; 256 let rd = 0, rs1 = 1, simm13 = 3 in 257 def TA3 : F3_2<0b10, 0b111010, (outs), (ins), 258 "ta 3", 259 [(flushw)]>; 260} 261 262let rd = 0 in 263 def UNIMP : F2_1<0b000, (outs), (ins i32imm:$val), 264 "unimp $val", []>; 265 266// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after 267// instruction selection into a branch sequence. This has to handle all 268// permutations of selection between i32/f32/f64 on ICC and FCC. 269// Expanded after instruction selection. 270let Uses = [ICC], usesCustomInserter = 1 in { 271 def SELECT_CC_Int_ICC 272 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond), 273 "; SELECT_CC_Int_ICC PSEUDO!", 274 [(set i32:$dst, (SPselecticc i32:$T, i32:$F, imm:$Cond))]>; 275 def SELECT_CC_FP_ICC 276 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, i32imm:$Cond), 277 "; SELECT_CC_FP_ICC PSEUDO!", 278 [(set f32:$dst, (SPselecticc f32:$T, f32:$F, imm:$Cond))]>; 279 280 def SELECT_CC_DFP_ICC 281 : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, i32imm:$Cond), 282 "; SELECT_CC_DFP_ICC PSEUDO!", 283 [(set f64:$dst, (SPselecticc f64:$T, f64:$F, imm:$Cond))]>; 284 285 def SELECT_CC_QFP_ICC 286 : Pseudo<(outs QFPRegs:$dst), (ins QFPRegs:$T, QFPRegs:$F, i32imm:$Cond), 287 "; SELECT_CC_QFP_ICC PSEUDO!", 288 [(set f128:$dst, (SPselecticc f128:$T, f128:$F, imm:$Cond))]>; 289} 290 291let usesCustomInserter = 1, Uses = [FCC] in { 292 293 def SELECT_CC_Int_FCC 294 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond), 295 "; SELECT_CC_Int_FCC PSEUDO!", 296 [(set i32:$dst, (SPselectfcc i32:$T, i32:$F, imm:$Cond))]>; 297 298 def SELECT_CC_FP_FCC 299 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, i32imm:$Cond), 300 "; SELECT_CC_FP_FCC PSEUDO!", 301 [(set f32:$dst, (SPselectfcc f32:$T, f32:$F, imm:$Cond))]>; 302 def SELECT_CC_DFP_FCC 303 : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, i32imm:$Cond), 304 "; SELECT_CC_DFP_FCC PSEUDO!", 305 [(set f64:$dst, (SPselectfcc f64:$T, f64:$F, imm:$Cond))]>; 306 def SELECT_CC_QFP_FCC 307 : Pseudo<(outs QFPRegs:$dst), (ins QFPRegs:$T, QFPRegs:$F, i32imm:$Cond), 308 "; SELECT_CC_QFP_FCC PSEUDO!", 309 [(set f128:$dst, (SPselectfcc f128:$T, f128:$F, imm:$Cond))]>; 310} 311 312 313// Section A.3 - Synthetic Instructions, p. 85 314// special cases of JMPL: 315let isReturn = 1, isTerminator = 1, hasDelaySlot = 1, isBarrier = 1 in { 316 let rd = 0, rs1 = 15 in 317 def RETL: F3_2<2, 0b111000, (outs), (ins i32imm:$val), 318 "jmp %o7+$val", [(retflag simm13:$val)]>; 319 320 let rd = 0, rs1 = 31 in 321 def RET: F3_2<2, 0b111000, (outs), (ins i32imm:$val), 322 "jmp %i7+$val", []>; 323} 324 325// Section B.1 - Load Integer Instructions, p. 90 326def LDSBrr : F3_1<3, 0b001001, 327 (outs IntRegs:$dst), (ins MEMrr:$addr), 328 "ldsb [$addr], $dst", 329 [(set i32:$dst, (sextloadi8 ADDRrr:$addr))]>; 330def LDSBri : F3_2<3, 0b001001, 331 (outs IntRegs:$dst), (ins MEMri:$addr), 332 "ldsb [$addr], $dst", 333 [(set i32:$dst, (sextloadi8 ADDRri:$addr))]>; 334def LDSHrr : F3_1<3, 0b001010, 335 (outs IntRegs:$dst), (ins MEMrr:$addr), 336 "ldsh [$addr], $dst", 337 [(set i32:$dst, (sextloadi16 ADDRrr:$addr))]>; 338def LDSHri : F3_2<3, 0b001010, 339 (outs IntRegs:$dst), (ins MEMri:$addr), 340 "ldsh [$addr], $dst", 341 [(set i32:$dst, (sextloadi16 ADDRri:$addr))]>; 342def LDUBrr : F3_1<3, 0b000001, 343 (outs IntRegs:$dst), (ins MEMrr:$addr), 344 "ldub [$addr], $dst", 345 [(set i32:$dst, (zextloadi8 ADDRrr:$addr))]>; 346def LDUBri : F3_2<3, 0b000001, 347 (outs IntRegs:$dst), (ins MEMri:$addr), 348 "ldub [$addr], $dst", 349 [(set i32:$dst, (zextloadi8 ADDRri:$addr))]>; 350def LDUHrr : F3_1<3, 0b000010, 351 (outs IntRegs:$dst), (ins MEMrr:$addr), 352 "lduh [$addr], $dst", 353 [(set i32:$dst, (zextloadi16 ADDRrr:$addr))]>; 354def LDUHri : F3_2<3, 0b000010, 355 (outs IntRegs:$dst), (ins MEMri:$addr), 356 "lduh [$addr], $dst", 357 [(set i32:$dst, (zextloadi16 ADDRri:$addr))]>; 358def LDrr : F3_1<3, 0b000000, 359 (outs IntRegs:$dst), (ins MEMrr:$addr), 360 "ld [$addr], $dst", 361 [(set i32:$dst, (load ADDRrr:$addr))]>; 362def LDri : F3_2<3, 0b000000, 363 (outs IntRegs:$dst), (ins MEMri:$addr), 364 "ld [$addr], $dst", 365 [(set i32:$dst, (load ADDRri:$addr))]>; 366 367// Section B.2 - Load Floating-point Instructions, p. 92 368def LDFrr : F3_1<3, 0b100000, 369 (outs FPRegs:$dst), (ins MEMrr:$addr), 370 "ld [$addr], $dst", 371 [(set f32:$dst, (load ADDRrr:$addr))]>; 372def LDFri : F3_2<3, 0b100000, 373 (outs FPRegs:$dst), (ins MEMri:$addr), 374 "ld [$addr], $dst", 375 [(set f32:$dst, (load ADDRri:$addr))]>; 376def LDDFrr : F3_1<3, 0b100011, 377 (outs DFPRegs:$dst), (ins MEMrr:$addr), 378 "ldd [$addr], $dst", 379 [(set f64:$dst, (load ADDRrr:$addr))]>; 380def LDDFri : F3_2<3, 0b100011, 381 (outs DFPRegs:$dst), (ins MEMri:$addr), 382 "ldd [$addr], $dst", 383 [(set f64:$dst, (load ADDRri:$addr))]>; 384def LDQFrr : F3_1<3, 0b100010, 385 (outs QFPRegs:$dst), (ins MEMrr:$addr), 386 "ldq [$addr], $dst", 387 [(set f128:$dst, (load ADDRrr:$addr))]>, 388 Requires<[HasV9, HasHardQuad]>; 389def LDQFri : F3_2<3, 0b100010, 390 (outs QFPRegs:$dst), (ins MEMri:$addr), 391 "ldq [$addr], $dst", 392 [(set f128:$dst, (load ADDRri:$addr))]>, 393 Requires<[HasV9, HasHardQuad]>; 394 395// Section B.4 - Store Integer Instructions, p. 95 396def STBrr : F3_1<3, 0b000101, 397 (outs), (ins MEMrr:$addr, IntRegs:$src), 398 "stb $src, [$addr]", 399 [(truncstorei8 i32:$src, ADDRrr:$addr)]>; 400def STBri : F3_2<3, 0b000101, 401 (outs), (ins MEMri:$addr, IntRegs:$src), 402 "stb $src, [$addr]", 403 [(truncstorei8 i32:$src, ADDRri:$addr)]>; 404def STHrr : F3_1<3, 0b000110, 405 (outs), (ins MEMrr:$addr, IntRegs:$src), 406 "sth $src, [$addr]", 407 [(truncstorei16 i32:$src, ADDRrr:$addr)]>; 408def STHri : F3_2<3, 0b000110, 409 (outs), (ins MEMri:$addr, IntRegs:$src), 410 "sth $src, [$addr]", 411 [(truncstorei16 i32:$src, ADDRri:$addr)]>; 412def STrr : F3_1<3, 0b000100, 413 (outs), (ins MEMrr:$addr, IntRegs:$src), 414 "st $src, [$addr]", 415 [(store i32:$src, ADDRrr:$addr)]>; 416def STri : F3_2<3, 0b000100, 417 (outs), (ins MEMri:$addr, IntRegs:$src), 418 "st $src, [$addr]", 419 [(store i32:$src, ADDRri:$addr)]>; 420 421// Section B.5 - Store Floating-point Instructions, p. 97 422def STFrr : F3_1<3, 0b100100, 423 (outs), (ins MEMrr:$addr, FPRegs:$src), 424 "st $src, [$addr]", 425 [(store f32:$src, ADDRrr:$addr)]>; 426def STFri : F3_2<3, 0b100100, 427 (outs), (ins MEMri:$addr, FPRegs:$src), 428 "st $src, [$addr]", 429 [(store f32:$src, ADDRri:$addr)]>; 430def STDFrr : F3_1<3, 0b100111, 431 (outs), (ins MEMrr:$addr, DFPRegs:$src), 432 "std $src, [$addr]", 433 [(store f64:$src, ADDRrr:$addr)]>; 434def STDFri : F3_2<3, 0b100111, 435 (outs), (ins MEMri:$addr, DFPRegs:$src), 436 "std $src, [$addr]", 437 [(store f64:$src, ADDRri:$addr)]>; 438def STQFrr : F3_1<3, 0b100110, 439 (outs), (ins MEMrr:$addr, QFPRegs:$src), 440 "stq $src, [$addr]", 441 [(store f128:$src, ADDRrr:$addr)]>, 442 Requires<[HasV9, HasHardQuad]>; 443def STQFri : F3_2<3, 0b100110, 444 (outs), (ins MEMri:$addr, QFPRegs:$src), 445 "stq $src, [$addr]", 446 [(store f128:$src, ADDRri:$addr)]>, 447 Requires<[HasV9, HasHardQuad]>; 448 449// Section B.9 - SETHI Instruction, p. 104 450def SETHIi: F2_1<0b100, 451 (outs IntRegs:$dst), (ins i32imm:$src), 452 "sethi $src, $dst", 453 [(set i32:$dst, SETHIimm:$src)]>; 454 455// Section B.10 - NOP Instruction, p. 105 456// (It's a special case of SETHI) 457let rd = 0, imm22 = 0 in 458 def NOP : F2_1<0b100, (outs), (ins), "nop", []>; 459 460// Section B.11 - Logical Instructions, p. 106 461defm AND : F3_12<"and", 0b000001, and>; 462 463def ANDNrr : F3_1<2, 0b000101, 464 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c), 465 "andn $b, $c, $dst", 466 [(set i32:$dst, (and i32:$b, (not i32:$c)))]>; 467def ANDNri : F3_2<2, 0b000101, 468 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c), 469 "andn $b, $c, $dst", []>; 470 471defm OR : F3_12<"or", 0b000010, or>; 472 473def ORNrr : F3_1<2, 0b000110, 474 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c), 475 "orn $b, $c, $dst", 476 [(set i32:$dst, (or i32:$b, (not i32:$c)))]>; 477def ORNri : F3_2<2, 0b000110, 478 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c), 479 "orn $b, $c, $dst", []>; 480defm XOR : F3_12<"xor", 0b000011, xor>; 481 482def XNORrr : F3_1<2, 0b000111, 483 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c), 484 "xnor $b, $c, $dst", 485 [(set i32:$dst, (not (xor i32:$b, i32:$c)))]>; 486def XNORri : F3_2<2, 0b000111, 487 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c), 488 "xnor $b, $c, $dst", []>; 489 490// Section B.12 - Shift Instructions, p. 107 491defm SLL : F3_12<"sll", 0b100101, shl>; 492defm SRL : F3_12<"srl", 0b100110, srl>; 493defm SRA : F3_12<"sra", 0b100111, sra>; 494 495// Section B.13 - Add Instructions, p. 108 496defm ADD : F3_12<"add", 0b000000, add>; 497 498// "LEA" forms of add (patterns to make tblgen happy) 499def LEA_ADDri : F3_2<2, 0b000000, 500 (outs IntRegs:$dst), (ins MEMri:$addr), 501 "add ${addr:arith}, $dst", 502 [(set iPTR:$dst, ADDRri:$addr)]>; 503 504let Defs = [ICC] in 505 defm ADDCC : F3_12<"addcc", 0b010000, addc>; 506 507let Uses = [ICC] in 508 defm ADDX : F3_12<"addx", 0b001000, adde>; 509 510// Section B.15 - Subtract Instructions, p. 110 511defm SUB : F3_12 <"sub" , 0b000100, sub>; 512let Uses = [ICC] in 513 defm SUBX : F3_12 <"subx" , 0b001100, sube>; 514 515let Defs = [ICC] in 516 defm SUBCC : F3_12 <"subcc", 0b010100, subc>; 517 518let Defs = [ICC], rd = 0 in { 519 def CMPrr : F3_1<2, 0b010100, 520 (outs), (ins IntRegs:$b, IntRegs:$c), 521 "cmp $b, $c", 522 [(SPcmpicc i32:$b, i32:$c)]>; 523 def CMPri : F3_2<2, 0b010100, 524 (outs), (ins IntRegs:$b, i32imm:$c), 525 "cmp $b, $c", 526 [(SPcmpicc i32:$b, (i32 simm13:$c))]>; 527} 528 529let Uses = [ICC], Defs = [ICC] in 530 def SUBXCCrr: F3_1<2, 0b011100, 531 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c), 532 "subxcc $b, $c, $dst", []>; 533 534 535// Section B.18 - Multiply Instructions, p. 113 536let Defs = [Y] in { 537 defm UMUL : F3_12np<"umul", 0b001010>; 538 defm SMUL : F3_12 <"smul", 0b001011, mul>; 539} 540 541// Section B.19 - Divide Instructions, p. 115 542let Defs = [Y] in { 543 defm UDIV : F3_12np<"udiv", 0b001110>; 544 defm SDIV : F3_12np<"sdiv", 0b001111>; 545} 546 547// Section B.20 - SAVE and RESTORE, p. 117 548defm SAVE : F3_12np<"save" , 0b111100>; 549defm RESTORE : F3_12np<"restore", 0b111101>; 550 551// Section B.21 - Branch on Integer Condition Codes Instructions, p. 119 552 553// unconditional branch class. 554class BranchAlways<dag ins, string asmstr, list<dag> pattern> 555 : F2_2<0b010, (outs), ins, asmstr, pattern> { 556 let isBranch = 1; 557 let isTerminator = 1; 558 let hasDelaySlot = 1; 559 let isBarrier = 1; 560} 561 562let cond = 8 in 563 def BA : BranchAlways<(ins brtarget:$imm22), "ba $imm22", [(br bb:$imm22)]>; 564 565// conditional branch class: 566class BranchSP<dag ins, string asmstr, list<dag> pattern> 567 : F2_2<0b010, (outs), ins, asmstr, pattern> { 568 let isBranch = 1; 569 let isTerminator = 1; 570 let hasDelaySlot = 1; 571} 572 573// Indirect branch instructions. 574let isTerminator = 1, isBarrier = 1, 575 hasDelaySlot = 1, isBranch =1, 576 isIndirectBranch = 1, rd = 0 in { 577 def BINDrr : F3_1<2, 0b111000, 578 (outs), (ins MEMrr:$ptr), 579 "jmp $ptr", 580 [(brind ADDRrr:$ptr)]>; 581 def BINDri : F3_2<2, 0b111000, 582 (outs), (ins MEMri:$ptr), 583 "jmp $ptr", 584 [(brind ADDRri:$ptr)]>; 585} 586 587let Uses = [ICC] in 588 def BCOND : BranchSP<(ins brtarget:$imm22, CCOp:$cond), 589 "b$cond $imm22", 590 [(SPbricc bb:$imm22, imm:$cond)]>; 591 592// Section B.22 - Branch on Floating-point Condition Codes Instructions, p. 121 593 594// floating-point conditional branch class: 595class FPBranchSP<dag ins, string asmstr, list<dag> pattern> 596 : F2_2<0b110, (outs), ins, asmstr, pattern> { 597 let isBranch = 1; 598 let isTerminator = 1; 599 let hasDelaySlot = 1; 600} 601 602let Uses = [FCC] in 603 def FBCOND : FPBranchSP<(ins brtarget:$imm22, CCOp:$cond), 604 "fb$cond $imm22", 605 [(SPbrfcc bb:$imm22, imm:$cond)]>; 606 607 608// Section B.24 - Call and Link Instruction, p. 125 609// This is the only Format 1 instruction 610let Uses = [O6], 611 hasDelaySlot = 1, isCall = 1 in { 612 def CALL : InstSP<(outs), (ins calltarget:$dst, variable_ops), 613 "call $dst", []> { 614 bits<30> disp; 615 let op = 1; 616 let Inst{29-0} = disp; 617 } 618 619 // indirect calls 620 def JMPLrr : F3_1<2, 0b111000, 621 (outs), (ins MEMrr:$ptr, variable_ops), 622 "call $ptr", 623 [(call ADDRrr:$ptr)]> { let rd = 15; } 624 def JMPLri : F3_2<2, 0b111000, 625 (outs), (ins MEMri:$ptr, variable_ops), 626 "call $ptr", 627 [(call ADDRri:$ptr)]> { let rd = 15; } 628} 629 630// Section B.28 - Read State Register Instructions 631let Uses = [Y], rs1 = 0, rs2 = 0 in 632 def RDY : F3_1<2, 0b101000, 633 (outs IntRegs:$dst), (ins), 634 "rd %y, $dst", []>; 635 636// Section B.29 - Write State Register Instructions 637let Defs = [Y], rd = 0 in { 638 def WRYrr : F3_1<2, 0b110000, 639 (outs), (ins IntRegs:$b, IntRegs:$c), 640 "wr $b, $c, %y", []>; 641 def WRYri : F3_2<2, 0b110000, 642 (outs), (ins IntRegs:$b, i32imm:$c), 643 "wr $b, $c, %y", []>; 644} 645// Convert Integer to Floating-point Instructions, p. 141 646def FITOS : F3_3u<2, 0b110100, 0b011000100, 647 (outs FPRegs:$dst), (ins FPRegs:$src), 648 "fitos $src, $dst", 649 [(set FPRegs:$dst, (SPitof FPRegs:$src))]>; 650def FITOD : F3_3u<2, 0b110100, 0b011001000, 651 (outs DFPRegs:$dst), (ins FPRegs:$src), 652 "fitod $src, $dst", 653 [(set DFPRegs:$dst, (SPitof FPRegs:$src))]>; 654def FITOQ : F3_3u<2, 0b110100, 0b011001100, 655 (outs QFPRegs:$dst), (ins FPRegs:$src), 656 "fitoq $src, $dst", 657 [(set QFPRegs:$dst, (SPitof FPRegs:$src))]>, 658 Requires<[HasHardQuad]>; 659 660// Convert Floating-point to Integer Instructions, p. 142 661def FSTOI : F3_3u<2, 0b110100, 0b011010001, 662 (outs FPRegs:$dst), (ins FPRegs:$src), 663 "fstoi $src, $dst", 664 [(set FPRegs:$dst, (SPftoi FPRegs:$src))]>; 665def FDTOI : F3_3u<2, 0b110100, 0b011010010, 666 (outs FPRegs:$dst), (ins DFPRegs:$src), 667 "fdtoi $src, $dst", 668 [(set FPRegs:$dst, (SPftoi DFPRegs:$src))]>; 669def FQTOI : F3_3u<2, 0b110100, 0b011010011, 670 (outs FPRegs:$dst), (ins QFPRegs:$src), 671 "fqtoi $src, $dst", 672 [(set FPRegs:$dst, (SPftoi QFPRegs:$src))]>, 673 Requires<[HasHardQuad]>; 674 675// Convert between Floating-point Formats Instructions, p. 143 676def FSTOD : F3_3u<2, 0b110100, 0b011001001, 677 (outs DFPRegs:$dst), (ins FPRegs:$src), 678 "fstod $src, $dst", 679 [(set f64:$dst, (fextend f32:$src))]>; 680def FSTOQ : F3_3u<2, 0b110100, 0b011001101, 681 (outs QFPRegs:$dst), (ins FPRegs:$src), 682 "fstoq $src, $dst", 683 [(set f128:$dst, (fextend f32:$src))]>, 684 Requires<[HasHardQuad]>; 685def FDTOS : F3_3u<2, 0b110100, 0b011000110, 686 (outs FPRegs:$dst), (ins DFPRegs:$src), 687 "fdtos $src, $dst", 688 [(set f32:$dst, (fround f64:$src))]>; 689def FDTOQ : F3_3u<2, 0b110100, 0b01101110, 690 (outs QFPRegs:$dst), (ins DFPRegs:$src), 691 "fdtoq $src, $dst", 692 [(set f128:$dst, (fextend f64:$src))]>, 693 Requires<[HasHardQuad]>; 694def FQTOS : F3_3u<2, 0b110100, 0b011000111, 695 (outs FPRegs:$dst), (ins QFPRegs:$src), 696 "fqtos $src, $dst", 697 [(set f32:$dst, (fround f128:$src))]>, 698 Requires<[HasHardQuad]>; 699def FQTOD : F3_3u<2, 0b110100, 0b011001011, 700 (outs DFPRegs:$dst), (ins QFPRegs:$src), 701 "fqtod $src, $dst", 702 [(set f64:$dst, (fround f128:$src))]>, 703 Requires<[HasHardQuad]>; 704 705// Floating-point Move Instructions, p. 144 706def FMOVS : F3_3u<2, 0b110100, 0b000000001, 707 (outs FPRegs:$dst), (ins FPRegs:$src), 708 "fmovs $src, $dst", []>; 709def FNEGS : F3_3u<2, 0b110100, 0b000000101, 710 (outs FPRegs:$dst), (ins FPRegs:$src), 711 "fnegs $src, $dst", 712 [(set f32:$dst, (fneg f32:$src))]>; 713def FABSS : F3_3u<2, 0b110100, 0b000001001, 714 (outs FPRegs:$dst), (ins FPRegs:$src), 715 "fabss $src, $dst", 716 [(set f32:$dst, (fabs f32:$src))]>; 717 718 719// Floating-point Square Root Instructions, p.145 720def FSQRTS : F3_3u<2, 0b110100, 0b000101001, 721 (outs FPRegs:$dst), (ins FPRegs:$src), 722 "fsqrts $src, $dst", 723 [(set f32:$dst, (fsqrt f32:$src))]>; 724def FSQRTD : F3_3u<2, 0b110100, 0b000101010, 725 (outs DFPRegs:$dst), (ins DFPRegs:$src), 726 "fsqrtd $src, $dst", 727 [(set f64:$dst, (fsqrt f64:$src))]>; 728def FSQRTQ : F3_3u<2, 0b110100, 0b000101011, 729 (outs QFPRegs:$dst), (ins QFPRegs:$src), 730 "fsqrtq $src, $dst", 731 [(set f128:$dst, (fsqrt f128:$src))]>, 732 Requires<[HasHardQuad]>; 733 734 735 736// Floating-point Add and Subtract Instructions, p. 146 737def FADDS : F3_3<2, 0b110100, 0b001000001, 738 (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2), 739 "fadds $src1, $src2, $dst", 740 [(set f32:$dst, (fadd f32:$src1, f32:$src2))]>; 741def FADDD : F3_3<2, 0b110100, 0b001000010, 742 (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2), 743 "faddd $src1, $src2, $dst", 744 [(set f64:$dst, (fadd f64:$src1, f64:$src2))]>; 745def FADDQ : F3_3<2, 0b110100, 0b001000011, 746 (outs QFPRegs:$dst), (ins QFPRegs:$src1, QFPRegs:$src2), 747 "faddq $src1, $src2, $dst", 748 [(set f128:$dst, (fadd f128:$src1, f128:$src2))]>, 749 Requires<[HasHardQuad]>; 750 751def FSUBS : F3_3<2, 0b110100, 0b001000101, 752 (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2), 753 "fsubs $src1, $src2, $dst", 754 [(set f32:$dst, (fsub f32:$src1, f32:$src2))]>; 755def FSUBD : F3_3<2, 0b110100, 0b001000110, 756 (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2), 757 "fsubd $src1, $src2, $dst", 758 [(set f64:$dst, (fsub f64:$src1, f64:$src2))]>; 759def FSUBQ : F3_3<2, 0b110100, 0b001000111, 760 (outs QFPRegs:$dst), (ins QFPRegs:$src1, QFPRegs:$src2), 761 "fsubq $src1, $src2, $dst", 762 [(set f128:$dst, (fsub f128:$src1, f128:$src2))]>, 763 Requires<[HasHardQuad]>; 764 765 766// Floating-point Multiply and Divide Instructions, p. 147 767def FMULS : F3_3<2, 0b110100, 0b001001001, 768 (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2), 769 "fmuls $src1, $src2, $dst", 770 [(set f32:$dst, (fmul f32:$src1, f32:$src2))]>; 771def FMULD : F3_3<2, 0b110100, 0b001001010, 772 (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2), 773 "fmuld $src1, $src2, $dst", 774 [(set f64:$dst, (fmul f64:$src1, f64:$src2))]>; 775def FMULQ : F3_3<2, 0b110100, 0b001001011, 776 (outs QFPRegs:$dst), (ins QFPRegs:$src1, QFPRegs:$src2), 777 "fmulq $src1, $src2, $dst", 778 [(set f128:$dst, (fmul f128:$src1, f128:$src2))]>, 779 Requires<[HasHardQuad]>; 780 781def FSMULD : F3_3<2, 0b110100, 0b001101001, 782 (outs DFPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2), 783 "fsmuld $src1, $src2, $dst", 784 [(set f64:$dst, (fmul (fextend f32:$src1), 785 (fextend f32:$src2)))]>; 786def FDMULQ : F3_3<2, 0b110100, 0b001101110, 787 (outs QFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2), 788 "fdmulq $src1, $src2, $dst", 789 [(set f128:$dst, (fmul (fextend f64:$src1), 790 (fextend f64:$src2)))]>, 791 Requires<[HasHardQuad]>; 792 793def FDIVS : F3_3<2, 0b110100, 0b001001101, 794 (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2), 795 "fdivs $src1, $src2, $dst", 796 [(set f32:$dst, (fdiv f32:$src1, f32:$src2))]>; 797def FDIVD : F3_3<2, 0b110100, 0b001001110, 798 (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2), 799 "fdivd $src1, $src2, $dst", 800 [(set f64:$dst, (fdiv f64:$src1, f64:$src2))]>; 801def FDIVQ : F3_3<2, 0b110100, 0b001001111, 802 (outs QFPRegs:$dst), (ins QFPRegs:$src1, QFPRegs:$src2), 803 "fdivq $src1, $src2, $dst", 804 [(set f128:$dst, (fdiv f128:$src1, f128:$src2))]>, 805 Requires<[HasHardQuad]>; 806 807// Floating-point Compare Instructions, p. 148 808// Note: the 2nd template arg is different for these guys. 809// Note 2: the result of a FCMP is not available until the 2nd cycle 810// after the instr is retired, but there is no interlock. This behavior 811// is modelled with a forced noop after the instruction. 812let Defs = [FCC] in { 813 def FCMPS : F3_3c<2, 0b110101, 0b001010001, 814 (outs), (ins FPRegs:$src1, FPRegs:$src2), 815 "fcmps $src1, $src2\n\tnop", 816 [(SPcmpfcc f32:$src1, f32:$src2)]>; 817 def FCMPD : F3_3c<2, 0b110101, 0b001010010, 818 (outs), (ins DFPRegs:$src1, DFPRegs:$src2), 819 "fcmpd $src1, $src2\n\tnop", 820 [(SPcmpfcc f64:$src1, f64:$src2)]>; 821 def FCMPQ : F3_3c<2, 0b110101, 0b001010011, 822 (outs), (ins QFPRegs:$src1, QFPRegs:$src2), 823 "fcmpq $src1, $src2\n\tnop", 824 [(SPcmpfcc f128:$src1, f128:$src2)]>, 825 Requires<[HasHardQuad]>; 826} 827 828//===----------------------------------------------------------------------===// 829// Instructions for Thread Local Storage(TLS). 830//===----------------------------------------------------------------------===// 831 832def TLS_ADDrr : F3_1<2, 0b000000, 833 (outs IntRegs:$rd), 834 (ins IntRegs:$rs1, IntRegs:$rs2, TLSSym:$sym), 835 "add $rs1, $rs2, $rd, $sym", 836 [(set i32:$rd, 837 (tlsadd i32:$rs1, i32:$rs2, tglobaltlsaddr:$sym))]>; 838 839let mayLoad = 1 in 840 def TLS_LDrr : F3_1<3, 0b000000, 841 (outs IntRegs:$dst), (ins MEMrr:$addr, TLSSym:$sym), 842 "ld [$addr], $dst, $sym", 843 [(set i32:$dst, 844 (tlsld ADDRrr:$addr, tglobaltlsaddr:$sym))]>; 845 846let Uses = [O6], isCall = 1 in 847 def TLS_CALL : InstSP<(outs), 848 (ins calltarget:$disp, TLSSym:$sym, variable_ops), 849 "call $disp, $sym\n\tnop", 850 [(tlscall texternalsym:$disp, tglobaltlsaddr:$sym)]> { 851 bits<30> disp; 852 let op = 1; 853 let Inst{29-0} = disp; 854} 855 856//===----------------------------------------------------------------------===// 857// V9 Instructions 858//===----------------------------------------------------------------------===// 859 860// V9 Conditional Moves. 861let Predicates = [HasV9], Constraints = "$f = $rd" in { 862 // Move Integer Register on Condition (MOVcc) p. 194 of the V9 manual. 863 let Uses = [ICC], cc = 0b100 in { 864 def MOVICCrr 865 : F4_1<0b101100, (outs IntRegs:$rd), 866 (ins IntRegs:$rs2, IntRegs:$f, CCOp:$cond), 867 "mov$cond %icc, $rs2, $rd", 868 [(set i32:$rd, (SPselecticc i32:$rs2, i32:$f, imm:$cond))]>; 869 870 def MOVICCri 871 : F4_2<0b101100, (outs IntRegs:$rd), 872 (ins i32imm:$simm11, IntRegs:$f, CCOp:$cond), 873 "mov$cond %icc, $simm11, $rd", 874 [(set i32:$rd, 875 (SPselecticc simm11:$simm11, i32:$f, imm:$cond))]>; 876 } 877 878 let Uses = [FCC], cc = 0b000 in { 879 def MOVFCCrr 880 : F4_1<0b101100, (outs IntRegs:$rd), 881 (ins IntRegs:$rs2, IntRegs:$f, CCOp:$cond), 882 "mov$cond %fcc0, $rs2, $rd", 883 [(set i32:$rd, (SPselectfcc i32:$rs2, i32:$f, imm:$cond))]>; 884 def MOVFCCri 885 : F4_2<0b101100, (outs IntRegs:$rd), 886 (ins i32imm:$simm11, IntRegs:$f, CCOp:$cond), 887 "mov$cond %fcc0, $simm11, $rd", 888 [(set i32:$rd, 889 (SPselectfcc simm11:$simm11, i32:$f, imm:$cond))]>; 890 } 891 892 let Uses = [ICC], opf_cc = 0b100 in { 893 def FMOVS_ICC 894 : F4_3<0b110101, 0b000001, (outs FPRegs:$rd), 895 (ins FPRegs:$rs2, FPRegs:$f, CCOp:$cond), 896 "fmovs$cond %icc, $rs2, $rd", 897 [(set f32:$rd, (SPselecticc f32:$rs2, f32:$f, imm:$cond))]>; 898 def FMOVD_ICC 899 : F4_3<0b110101, 0b000010, (outs DFPRegs:$rd), 900 (ins DFPRegs:$rs2, DFPRegs:$f, CCOp:$cond), 901 "fmovd$cond %icc, $rs2, $rd", 902 [(set f64:$rd, (SPselecticc f64:$rs2, f64:$f, imm:$cond))]>; 903 def FMOVQ_ICC 904 : F4_3<0b110101, 0b000011, (outs QFPRegs:$rd), 905 (ins QFPRegs:$rs2, QFPRegs:$f, CCOp:$cond), 906 "fmovd$cond %icc, $rs2, $rd", 907 [(set f128:$rd, (SPselecticc f128:$rs2, f128:$f, imm:$cond))]>; 908 } 909 910 let Uses = [FCC], opf_cc = 0b000 in { 911 def FMOVS_FCC 912 : F4_3<0b110101, 0b000001, (outs FPRegs:$rd), 913 (ins FPRegs:$rs2, FPRegs:$f, CCOp:$cond), 914 "fmovs$cond %fcc0, $rs2, $rd", 915 [(set f32:$rd, (SPselectfcc f32:$rs2, f32:$f, imm:$cond))]>; 916 def FMOVD_FCC 917 : F4_3<0b110101, 0b000010, (outs DFPRegs:$rd), 918 (ins DFPRegs:$rs2, DFPRegs:$f, CCOp:$cond), 919 "fmovd$cond %fcc0, $rs2, $rd", 920 [(set f64:$rd, (SPselectfcc f64:$rs2, f64:$f, imm:$cond))]>; 921 def FMOVQ_FCC 922 : F4_3<0b110101, 0b000011, (outs QFPRegs:$rd), 923 (ins QFPRegs:$rs2, QFPRegs:$f, CCOp:$cond), 924 "fmovd$cond %fcc0, $rs2, $rd", 925 [(set f128:$rd, (SPselectfcc f128:$rs2, f128:$f, imm:$cond))]>; 926 } 927 928} 929 930// Floating-Point Move Instructions, p. 164 of the V9 manual. 931let Predicates = [HasV9] in { 932 def FMOVD : F3_3u<2, 0b110100, 0b000000010, 933 (outs DFPRegs:$dst), (ins DFPRegs:$src), 934 "fmovd $src, $dst", []>; 935 def FMOVQ : F3_3u<2, 0b110100, 0b000000011, 936 (outs QFPRegs:$dst), (ins QFPRegs:$src), 937 "fmovq $src, $dst", []>, 938 Requires<[HasHardQuad]>; 939 def FNEGD : F3_3u<2, 0b110100, 0b000000110, 940 (outs DFPRegs:$dst), (ins DFPRegs:$src), 941 "fnegd $src, $dst", 942 [(set f64:$dst, (fneg f64:$src))]>; 943 def FNEGQ : F3_3u<2, 0b110100, 0b000000111, 944 (outs QFPRegs:$dst), (ins QFPRegs:$src), 945 "fnegq $src, $dst", 946 [(set f128:$dst, (fneg f128:$src))]>, 947 Requires<[HasHardQuad]>; 948 def FABSD : F3_3u<2, 0b110100, 0b000001010, 949 (outs DFPRegs:$dst), (ins DFPRegs:$src), 950 "fabsd $src, $dst", 951 [(set f64:$dst, (fabs f64:$src))]>; 952 def FABSQ : F3_3u<2, 0b110100, 0b000001011, 953 (outs QFPRegs:$dst), (ins QFPRegs:$src), 954 "fabsq $src, $dst", 955 [(set f128:$dst, (fabs f128:$src))]>, 956 Requires<[HasHardQuad]>; 957} 958 959// POPCrr - This does a ctpop of a 64-bit register. As such, we have to clear 960// the top 32-bits before using it. To do this clearing, we use a SLLri X,0. 961let rs1 = 0 in 962 def POPCrr : F3_1<2, 0b101110, 963 (outs IntRegs:$dst), (ins IntRegs:$src), 964 "popc $src, $dst", []>, Requires<[HasV9]>; 965def : Pat<(ctpop i32:$src), 966 (POPCrr (SLLri $src, 0))>; 967 968//===----------------------------------------------------------------------===// 969// Non-Instruction Patterns 970//===----------------------------------------------------------------------===// 971 972// Small immediates. 973def : Pat<(i32 simm13:$val), 974 (ORri (i32 G0), imm:$val)>; 975// Arbitrary immediates. 976def : Pat<(i32 imm:$val), 977 (ORri (SETHIi (HI22 imm:$val)), (LO10 imm:$val))>; 978 979 980// Global addresses, constant pool entries 981def : Pat<(SPhi tglobaladdr:$in), (SETHIi tglobaladdr:$in)>; 982def : Pat<(SPlo tglobaladdr:$in), (ORri (i32 G0), tglobaladdr:$in)>; 983def : Pat<(SPhi tconstpool:$in), (SETHIi tconstpool:$in)>; 984def : Pat<(SPlo tconstpool:$in), (ORri (i32 G0), tconstpool:$in)>; 985 986// GlobalTLS addresses 987def : Pat<(SPhi tglobaltlsaddr:$in), (SETHIi tglobaltlsaddr:$in)>; 988def : Pat<(SPlo tglobaltlsaddr:$in), (ORri (i32 G0), tglobaltlsaddr:$in)>; 989def : Pat<(add (SPhi tglobaltlsaddr:$in1), (SPlo tglobaltlsaddr:$in2)), 990 (ADDri (SETHIi tglobaltlsaddr:$in1), (tglobaltlsaddr:$in2))>; 991def : Pat<(xor (SPhi tglobaltlsaddr:$in1), (SPlo tglobaltlsaddr:$in2)), 992 (XORri (SETHIi tglobaltlsaddr:$in1), (tglobaltlsaddr:$in2))>; 993 994// Blockaddress 995def : Pat<(SPhi tblockaddress:$in), (SETHIi tblockaddress:$in)>; 996def : Pat<(SPlo tblockaddress:$in), (ORri (i32 G0), tblockaddress:$in)>; 997 998// Add reg, lo. This is used when taking the addr of a global/constpool entry. 999def : Pat<(add iPTR:$r, (SPlo tglobaladdr:$in)), (ADDri $r, tglobaladdr:$in)>; 1000def : Pat<(add iPTR:$r, (SPlo tconstpool:$in)), (ADDri $r, tconstpool:$in)>; 1001def : Pat<(add iPTR:$r, (SPlo tblockaddress:$in)), 1002 (ADDri $r, tblockaddress:$in)>; 1003 1004// Calls: 1005def : Pat<(call tglobaladdr:$dst), 1006 (CALL tglobaladdr:$dst)>; 1007def : Pat<(call texternalsym:$dst), 1008 (CALL texternalsym:$dst)>; 1009 1010// Map integer extload's to zextloads. 1011def : Pat<(i32 (extloadi1 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>; 1012def : Pat<(i32 (extloadi1 ADDRri:$src)), (LDUBri ADDRri:$src)>; 1013def : Pat<(i32 (extloadi8 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>; 1014def : Pat<(i32 (extloadi8 ADDRri:$src)), (LDUBri ADDRri:$src)>; 1015def : Pat<(i32 (extloadi16 ADDRrr:$src)), (LDUHrr ADDRrr:$src)>; 1016def : Pat<(i32 (extloadi16 ADDRri:$src)), (LDUHri ADDRri:$src)>; 1017 1018// zextload bool -> zextload byte 1019def : Pat<(i32 (zextloadi1 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>; 1020def : Pat<(i32 (zextloadi1 ADDRri:$src)), (LDUBri ADDRri:$src)>; 1021 1022// store 0, addr -> store %g0, addr 1023def : Pat<(store (i32 0), ADDRrr:$dst), (STrr ADDRrr:$dst, (i32 G0))>; 1024def : Pat<(store (i32 0), ADDRri:$dst), (STri ADDRri:$dst, (i32 G0))>; 1025 1026include "SparcInstr64Bit.td" 1027