SparcRegisterInfo.cpp revision 09e460662a8d7328da1b938d5581a6ef3740b51d 
1//===- SparcRegisterInfo.cpp - SPARC Register Information -------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file was developed by the LLVM research group and is distributed under
6// the University of Illinois Open Source License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the SPARC implementation of the MRegisterInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "Sparc.h"
15#include "SparcRegisterInfo.h"
16#include "SparcSubtarget.h"
17#include "llvm/CodeGen/MachineInstrBuilder.h"
18#include "llvm/CodeGen/MachineFunction.h"
19#include "llvm/CodeGen/MachineFrameInfo.h"
20#include "llvm/CodeGen/MachineLocation.h"
21#include "llvm/Type.h"
22#include "llvm/ADT/STLExtras.h"
23#include <iostream>
24using namespace llvm;
25
26SparcRegisterInfo::SparcRegisterInfo(SparcSubtarget &st)
27  : SparcGenRegisterInfo(SP::ADJCALLSTACKDOWN, SP::ADJCALLSTACKUP),
28    Subtarget(st) {
29}
30
31void SparcRegisterInfo::
32storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
33                    unsigned SrcReg, int FI,
34                    const TargetRegisterClass *RC) const {
35  // On the order of operands here: think "[FrameIdx + 0] = SrcReg".
36  if (RC == SP::IntRegsRegisterClass)
37    BuildMI(MBB, I, SP::STri, 3).addFrameIndex(FI).addImm(0).addReg(SrcReg);
38  else if (RC == SP::FPRegsRegisterClass)
39    BuildMI(MBB, I, SP::STFri, 3).addFrameIndex(FI).addImm(0).addReg(SrcReg);
40  else if (RC == SP::DFPRegsRegisterClass)
41    BuildMI(MBB, I, SP::STDFri, 3).addFrameIndex(FI).addImm(0).addReg(SrcReg);
42  else
43    assert(0 && "Can't store this register to stack slot");
44}
45
46void SparcRegisterInfo::
47loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
48                     unsigned DestReg, int FI,
49                     const TargetRegisterClass *RC) const {
50  if (RC == SP::IntRegsRegisterClass)
51    BuildMI(MBB, I, SP::LDri, 2, DestReg).addFrameIndex(FI).addImm(0);
52  else if (RC == SP::FPRegsRegisterClass)
53    BuildMI(MBB, I, SP::LDFri, 2, DestReg).addFrameIndex(FI).addImm (0);
54  else if (RC == SP::DFPRegsRegisterClass)
55    BuildMI(MBB, I, SP::LDDFri, 2, DestReg).addFrameIndex(FI).addImm(0);
56  else
57    assert(0 && "Can't load this register from stack slot");
58}
59
60void SparcRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
61                                     MachineBasicBlock::iterator I,
62                                     unsigned DestReg, unsigned SrcReg,
63                                     const TargetRegisterClass *RC) const {
64  if (RC == SP::IntRegsRegisterClass)
65    BuildMI(MBB, I, SP::ORrr, 2, DestReg).addReg(SP::G0).addReg(SrcReg);
66  else if (RC == SP::FPRegsRegisterClass)
67    BuildMI(MBB, I, SP::FMOVS, 1, DestReg).addReg(SrcReg);
68  else if (RC == SP::DFPRegsRegisterClass)
69    BuildMI(MBB, I, Subtarget.isV9() ? SP::FMOVD : SP::FpMOVD,
70            1, DestReg).addReg(SrcReg);
71  else
72    assert (0 && "Can't copy this register");
73}
74
75MachineInstr *SparcRegisterInfo::foldMemoryOperand(MachineInstr* MI,
76                                                   unsigned OpNum,
77                                                   int FI) const {
78  bool isFloat = false;
79  switch (MI->getOpcode()) {
80  case SP::ORrr:
81    if (MI->getOperand(1).isRegister() && MI->getOperand(1).getReg() == SP::G0&&
82        MI->getOperand(0).isRegister() && MI->getOperand(2).isRegister()) {
83      if (OpNum == 0)    // COPY -> STORE
84        return BuildMI(SP::STri, 3).addFrameIndex(FI).addImm(0)
85                                   .addReg(MI->getOperand(2).getReg());
86      else               // COPY -> LOAD
87        return BuildMI(SP::LDri, 2, MI->getOperand(0).getReg())
88                      .addFrameIndex(FI).addImm(0);
89    }
90    break;
91  case SP::FMOVS:
92    isFloat = true;
93    // FALLTHROUGH
94  case SP::FMOVD:
95    if (OpNum == 0)  // COPY -> STORE
96      return BuildMI(isFloat ? SP::STFri : SP::STDFri, 3)
97               .addFrameIndex(FI).addImm(0).addReg(MI->getOperand(1).getReg());
98    else             // COPY -> LOAD
99      return BuildMI(isFloat ? SP::LDFri : SP::LDDFri, 2,
100                     MI->getOperand(0).getReg()).addFrameIndex(FI).addImm(0);
101    break;
102  }
103  return 0;
104}
105
106const unsigned* SparcRegisterInfo::getCalleeSaveRegs() const {
107  static const unsigned CalleeSaveRegs[] = { 0 };
108  return CalleeSaveRegs;
109}
110
111const TargetRegisterClass* const*
112SparcRegisterInfo::getCalleeSaveRegClasses() const {
113  static const TargetRegisterClass * const CalleeSaveRegClasses[] = { 0 };
114  return CalleeSaveRegClasses;
115}
116
117
118void SparcRegisterInfo::
119eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
120                              MachineBasicBlock::iterator I) const {
121  MachineInstr &MI = *I;
122  int Size = MI.getOperand(0).getImmedValue();
123  if (MI.getOpcode() == SP::ADJCALLSTACKDOWN)
124    Size = -Size;
125  if (Size)
126    BuildMI(MBB, I, SP::ADDri, 2, SP::O6).addReg(SP::O6).addImm(Size);
127  MBB.erase(I);
128}
129
130void
131SparcRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
132  unsigned i = 0;
133  MachineInstr &MI = *II;
134  while (!MI.getOperand(i).isFrameIndex()) {
135    ++i;
136    assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
137  }
138
139  int FrameIndex = MI.getOperand(i).getFrameIndex();
140
141  // Addressable stack objects are accessed using neg. offsets from %fp
142  MachineFunction &MF = *MI.getParent()->getParent();
143  int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
144               MI.getOperand(i+1).getImmedValue();
145
146  // Replace frame index with a frame pointer reference.
147  if (Offset >= -4096 && Offset <= 4095) {
148    // If the offset is small enough to fit in the immediate field, directly
149    // encode it.
150    MI.getOperand(i).ChangeToRegister(SP::I6, false);
151    MI.getOperand(i+1).ChangeToImmediate(Offset);
152  } else {
153    // Otherwise, emit a G1 = SETHI %hi(offset).  FIXME: it would be better to
154    // scavenge a register here instead of reserving G1 all of the time.
155    unsigned OffHi = (unsigned)Offset >> 10U;
156    BuildMI(*MI.getParent(), II, SP::SETHIi, 1, SP::G1).addImm(OffHi);
157    // Emit G1 = G1 + I6
158    BuildMI(*MI.getParent(), II, SP::ADDrr, 2,
159            SP::G1).addReg(SP::G1).addReg(SP::I6);
160    // Insert: G1+%lo(offset) into the user.
161    MI.getOperand(i).ChangeToRegister(SP::G1, false);
162    MI.getOperand(i+1).ChangeToImmediate(Offset & ((1 << 10)-1));
163  }
164}
165
166void SparcRegisterInfo::
167processFunctionBeforeFrameFinalized(MachineFunction &MF) const {}
168
169void SparcRegisterInfo::emitPrologue(MachineFunction &MF) const {
170  MachineBasicBlock &MBB = MF.front();
171  MachineFrameInfo *MFI = MF.getFrameInfo();
172
173  // Get the number of bytes to allocate from the FrameInfo
174  int NumBytes = (int) MFI->getStackSize();
175
176  // Emit the correct save instruction based on the number of bytes in
177  // the frame. Minimum stack frame size according to V8 ABI is:
178  //   16 words for register window spill
179  //    1 word for address of returned aggregate-value
180  // +  6 words for passing parameters on the stack
181  // ----------
182  //   23 words * 4 bytes per word = 92 bytes
183  NumBytes += 92;
184  // Round up to next doubleword boundary -- a double-word boundary
185  // is required by the ABI.
186  NumBytes = (NumBytes + 7) & ~7;
187  NumBytes = -NumBytes;
188
189  if (NumBytes >= -4096) {
190    BuildMI(MBB, MBB.begin(), SP::SAVEri, 2,
191            SP::O6).addImm(NumBytes).addReg(SP::O6);
192  } else {
193    MachineBasicBlock::iterator InsertPt = MBB.begin();
194    // Emit this the hard way.  This clobbers G1 which we always know is
195    // available here.
196    unsigned OffHi = (unsigned)NumBytes >> 10U;
197    BuildMI(MBB, InsertPt, SP::SETHIi, 1, SP::G1).addImm(OffHi);
198    // Emit G1 = G1 + I6
199    BuildMI(MBB, InsertPt, SP::ORri, 2, SP::G1)
200      .addReg(SP::G1).addImm(NumBytes & ((1 << 10)-1));
201    BuildMI(MBB, InsertPt, SP::SAVErr, 2,
202            SP::O6).addReg(SP::O6).addReg(SP::G1);
203  }
204}
205
206void SparcRegisterInfo::emitEpilogue(MachineFunction &MF,
207                                     MachineBasicBlock &MBB) const {
208  MachineBasicBlock::iterator MBBI = prior(MBB.end());
209  assert(MBBI->getOpcode() == SP::RETL &&
210         "Can only put epilog before 'retl' instruction!");
211  BuildMI(MBB, MBBI, SP::RESTORErr, 2, SP::G0).addReg(SP::G0).addReg(SP::G0);
212}
213
214unsigned SparcRegisterInfo::getRARegister() const {
215  assert(0 && "What is the return address register");
216  return 0;
217}
218
219unsigned SparcRegisterInfo::getFrameRegister(MachineFunction &MF) const {
220  assert(0 && "What is the frame register");
221  return SP::G1;
222}
223
224#include "SparcGenRegisterInfo.inc"
225
226