SparcRegisterInfo.cpp revision 1b41835f02f77c04a93323f722cf158cc566acae 
1//===-- SparcRegisterInfo.cpp - SPARC Register Information ----------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the SPARC implementation of the TargetRegisterInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "SparcRegisterInfo.h"
15#include "Sparc.h"
16#include "SparcMachineFunctionInfo.h"
17#include "SparcSubtarget.h"
18#include "llvm/ADT/BitVector.h"
19#include "llvm/ADT/STLExtras.h"
20#include "llvm/CodeGen/MachineFrameInfo.h"
21#include "llvm/CodeGen/MachineFunction.h"
22#include "llvm/CodeGen/MachineInstrBuilder.h"
23#include "llvm/IR/Type.h"
24#include "llvm/Support/CommandLine.h"
25#include "llvm/Support/ErrorHandling.h"
26#include "llvm/Target/TargetInstrInfo.h"
27
28#define GET_REGINFO_TARGET_DESC
29#include "SparcGenRegisterInfo.inc"
30
31using namespace llvm;
32
33static cl::opt<bool>
34ReserveAppRegisters("sparc-reserve-app-registers", cl::Hidden, cl::init(false),
35                    cl::desc("Reserve application registers (%g2-%g4)"));
36
37SparcRegisterInfo::SparcRegisterInfo(SparcSubtarget &st)
38  : SparcGenRegisterInfo(SP::I7), Subtarget(st) {
39}
40
41const uint16_t* SparcRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF)
42                                                                         const {
43  return CSR_SaveList;
44}
45
46const uint32_t*
47SparcRegisterInfo::getCallPreservedMask(CallingConv::ID CC) const {
48  return CSR_RegMask;
49}
50
51const uint32_t*
52SparcRegisterInfo::getRTCallPreservedMask(CallingConv::ID CC) const {
53  return RTCSR_RegMask;
54}
55
56BitVector SparcRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
57  BitVector Reserved(getNumRegs());
58  // FIXME: G1 reserved for now for large imm generation by frame code.
59  Reserved.set(SP::G1);
60
61  // G1-G4 can be used in applications.
62  if (ReserveAppRegisters) {
63    Reserved.set(SP::G2);
64    Reserved.set(SP::G3);
65    Reserved.set(SP::G4);
66  }
67  // G5 is not reserved in 64 bit mode.
68  if (!Subtarget.is64Bit())
69    Reserved.set(SP::G5);
70
71  Reserved.set(SP::O6);
72  Reserved.set(SP::I6);
73  Reserved.set(SP::I7);
74  Reserved.set(SP::G0);
75  Reserved.set(SP::G6);
76  Reserved.set(SP::G7);
77
78  // Unaliased double registers are not available in non-V9 targets.
79  if (!Subtarget.isV9()) {
80    for (unsigned n = 0; n != 16; ++n) {
81      for (MCRegAliasIterator AI(SP::D16 + n, this, true); AI.isValid(); ++AI)
82        Reserved.set(*AI);
83    }
84  }
85
86  return Reserved;
87}
88
89const TargetRegisterClass*
90SparcRegisterInfo::getPointerRegClass(const MachineFunction &MF,
91                                      unsigned Kind) const {
92  return Subtarget.is64Bit() ? &SP::I64RegsRegClass : &SP::IntRegsRegClass;
93}
94
95static void replaceFI(MachineFunction &MF,
96                      MachineBasicBlock::iterator II,
97                      MachineInstr &MI,
98                      DebugLoc dl,
99                      unsigned FIOperandNum, int Offset,
100                      unsigned FramePtr)
101{
102  // Replace frame index with a frame pointer reference.
103  if (Offset >= -4096 && Offset <= 4095) {
104    // If the offset is small enough to fit in the immediate field, directly
105    // encode it.
106    MI.getOperand(FIOperandNum).ChangeToRegister(FramePtr, false);
107    MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
108  } else {
109    // Otherwise, emit a G1 = SETHI %hi(offset).  FIXME: it would be better to
110    // scavenge a register here instead of reserving G1 all of the time.
111    const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
112    unsigned OffHi = (unsigned)Offset >> 10U;
113    BuildMI(*MI.getParent(), II, dl, TII.get(SP::SETHIi), SP::G1).addImm(OffHi);
114    // Emit G1 = G1 + I6
115    BuildMI(*MI.getParent(), II, dl, TII.get(SP::ADDrr), SP::G1).addReg(SP::G1)
116      .addReg(FramePtr);
117    // Insert: G1+%lo(offset) into the user.
118    MI.getOperand(FIOperandNum).ChangeToRegister(SP::G1, false);
119    MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset & ((1 << 10)-1));
120  }
121}
122
123
124void
125SparcRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
126                                       int SPAdj, unsigned FIOperandNum,
127                                       RegScavenger *RS) const {
128  assert(SPAdj == 0 && "Unexpected");
129
130  MachineInstr &MI = *II;
131  DebugLoc dl = MI.getDebugLoc();
132  int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
133
134  // Addressable stack objects are accessed using neg. offsets from %fp
135  MachineFunction &MF = *MI.getParent()->getParent();
136  int64_t Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
137                   MI.getOperand(FIOperandNum + 1).getImm() +
138                   Subtarget.getStackPointerBias();
139  SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();
140  unsigned FramePtr = SP::I6;
141  if (FuncInfo->isLeafProc()) {
142    // Use %sp and adjust offset if needed.
143    FramePtr = SP::O6;
144    int stackSize = MF.getFrameInfo()->getStackSize();
145    Offset += (stackSize) ? Subtarget.getAdjustedFrameSize(stackSize) : 0 ;
146  }
147
148  if (!Subtarget.isV9() || !Subtarget.hasHardQuad()) {
149    if (MI.getOpcode() == SP::STQFri) {
150      const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
151      unsigned SrcReg = MI.getOperand(2).getReg();
152      unsigned SrcEvenReg = getSubReg(SrcReg, SP::sub_even64);
153      unsigned SrcOddReg  = getSubReg(SrcReg, SP::sub_odd64);
154      MachineInstr *StMI =
155        BuildMI(*MI.getParent(), II, dl, TII.get(SP::STDFri))
156        .addReg(FramePtr).addImm(0).addReg(SrcEvenReg);
157      replaceFI(MF, II, *StMI, dl, 0, Offset, FramePtr);
158      MI.setDesc(TII.get(SP::STDFri));
159      MI.getOperand(2).setReg(SrcOddReg);
160      Offset += 8;
161    } else if (MI.getOpcode() == SP::LDQFri) {
162      const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
163      unsigned DestReg     = MI.getOperand(0).getReg();
164      unsigned DestEvenReg = getSubReg(DestReg, SP::sub_even64);
165      unsigned DestOddReg  = getSubReg(DestReg, SP::sub_odd64);
166      MachineInstr *StMI =
167        BuildMI(*MI.getParent(), II, dl, TII.get(SP::LDDFri), DestEvenReg)
168        .addReg(FramePtr).addImm(0);
169      replaceFI(MF, II, *StMI, dl, 1, Offset, FramePtr);
170
171      MI.setDesc(TII.get(SP::LDDFri));
172      MI.getOperand(0).setReg(DestOddReg);
173      Offset += 8;
174    }
175  }
176
177  replaceFI(MF, II, MI, dl, FIOperandNum, Offset, FramePtr);
178
179}
180
181unsigned SparcRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
182  return SP::I6;
183}
184
185unsigned SparcRegisterInfo::getEHExceptionRegister() const {
186  llvm_unreachable("What is the exception register");
187}
188
189unsigned SparcRegisterInfo::getEHHandlerRegister() const {
190  llvm_unreachable("What is the exception handler register");
191}
192