SparcRegisterInfo.cpp revision 2a9d1ca9c244aeac98044a5fc9a081ff3df7b2ff 
1//===- SparcRegisterInfo.cpp - SPARC Register Information -------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the SPARC implementation of the TargetRegisterInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "Sparc.h"
15#include "SparcRegisterInfo.h"
16#include "SparcSubtarget.h"
17#include "llvm/CodeGen/MachineInstrBuilder.h"
18#include "llvm/CodeGen/MachineFunction.h"
19#include "llvm/CodeGen/MachineFrameInfo.h"
20#include "llvm/CodeGen/MachineLocation.h"
21#include "llvm/Support/ErrorHandling.h"
22#include "llvm/Target/TargetInstrInfo.h"
23#include "llvm/Type.h"
24#include "llvm/ADT/BitVector.h"
25#include "llvm/ADT/STLExtras.h"
26using namespace llvm;
27
28SparcRegisterInfo::SparcRegisterInfo(SparcSubtarget &st,
29                                     const TargetInstrInfo &tii)
30  : SparcGenRegisterInfo(SP::ADJCALLSTACKDOWN, SP::ADJCALLSTACKUP),
31    Subtarget(st), TII(tii) {
32}
33
34const unsigned* SparcRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF)
35                                                                         const {
36  static const unsigned CalleeSavedRegs[] = { 0 };
37  return CalleeSavedRegs;
38}
39
40BitVector SparcRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
41  BitVector Reserved(getNumRegs());
42  // FIXME: G1 reserved for now for large imm generation by frame code.
43  Reserved.set(SP::G1);
44  Reserved.set(SP::G2);
45  Reserved.set(SP::G3);
46  Reserved.set(SP::G4);
47  Reserved.set(SP::O6);
48  Reserved.set(SP::I6);
49  Reserved.set(SP::I7);
50  Reserved.set(SP::G0);
51  Reserved.set(SP::G5);
52  Reserved.set(SP::G6);
53  Reserved.set(SP::G7);
54  return Reserved;
55}
56
57void SparcRegisterInfo::
58eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
59                              MachineBasicBlock::iterator I) const {
60  MachineInstr &MI = *I;
61  DebugLoc dl = MI.getDebugLoc();
62  int Size = MI.getOperand(0).getImm();
63  if (MI.getOpcode() == SP::ADJCALLSTACKDOWN)
64    Size = -Size;
65  if (Size)
66    BuildMI(MBB, I, dl, TII.get(SP::ADDri), SP::O6).addReg(SP::O6).addImm(Size);
67  MBB.erase(I);
68}
69
70void
71SparcRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
72                                       int SPAdj, RegScavenger *RS) const {
73  assert(SPAdj == 0 && "Unexpected");
74
75  unsigned i = 0;
76  MachineInstr &MI = *II;
77  DebugLoc dl = MI.getDebugLoc();
78  while (!MI.getOperand(i).isFI()) {
79    ++i;
80    assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
81  }
82
83  int FrameIndex = MI.getOperand(i).getIndex();
84
85  // Addressable stack objects are accessed using neg. offsets from %fp
86  MachineFunction &MF = *MI.getParent()->getParent();
87  int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
88               MI.getOperand(i+1).getImm();
89
90  // Replace frame index with a frame pointer reference.
91  if (Offset >= -4096 && Offset <= 4095) {
92    // If the offset is small enough to fit in the immediate field, directly
93    // encode it.
94    MI.getOperand(i).ChangeToRegister(SP::I6, false);
95    MI.getOperand(i+1).ChangeToImmediate(Offset);
96  } else {
97    // Otherwise, emit a G1 = SETHI %hi(offset).  FIXME: it would be better to
98    // scavenge a register here instead of reserving G1 all of the time.
99    unsigned OffHi = (unsigned)Offset >> 10U;
100    BuildMI(*MI.getParent(), II, dl, TII.get(SP::SETHIi), SP::G1).addImm(OffHi);
101    // Emit G1 = G1 + I6
102    BuildMI(*MI.getParent(), II, dl, TII.get(SP::ADDrr), SP::G1).addReg(SP::G1)
103      .addReg(SP::I6);
104    // Insert: G1+%lo(offset) into the user.
105    MI.getOperand(i).ChangeToRegister(SP::G1, false);
106    MI.getOperand(i+1).ChangeToImmediate(Offset & ((1 << 10)-1));
107  }
108}
109
110void SparcRegisterInfo::
111processFunctionBeforeFrameFinalized(MachineFunction &MF) const {}
112
113unsigned SparcRegisterInfo::getRARegister() const {
114  return SP::I7;
115}
116
117unsigned SparcRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
118  return SP::I6;
119}
120
121unsigned SparcRegisterInfo::getEHExceptionRegister() const {
122  llvm_unreachable("What is the exception register");
123  return 0;
124}
125
126unsigned SparcRegisterInfo::getEHHandlerRegister() const {
127  llvm_unreachable("What is the exception handler register");
128  return 0;
129}
130
131int SparcRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
132  return SparcGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
133}
134
135int SparcRegisterInfo::getLLVMRegNum(unsigned DwarfRegNo, bool isEH) const {
136  return SparcGenRegisterInfo::getLLVMRegNumFull(DwarfRegNo,0);
137}
138
139#include "SparcGenRegisterInfo.inc"
140
141