SparcRegisterInfo.cpp revision 57f1b67c347b9ba1f8a1cdc3a55362d4f2aa8653 
1//===- SparcV8RegisterInfo.cpp - SparcV8 Register Information ---*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file was developed by the LLVM research group and is distributed under
6// the University of Illinois Open Source License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the SparcV8 implementation of the MRegisterInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "SparcV8.h"
15#include "SparcV8RegisterInfo.h"
16#include "llvm/CodeGen/MachineInstrBuilder.h"
17#include "llvm/CodeGen/MachineFunction.h"
18#include "llvm/CodeGen/MachineFrameInfo.h"
19#include "llvm/Type.h"
20#include "Support/STLExtras.h"
21#include <iostream>
22using namespace llvm;
23
24SparcV8RegisterInfo::SparcV8RegisterInfo()
25  : SparcV8GenRegisterInfo(V8::ADJCALLSTACKDOWN,
26                           V8::ADJCALLSTACKUP) {}
27
28int SparcV8RegisterInfo::
29storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
30                    unsigned SrcReg, int FrameIdx) const {
31  const TargetRegisterClass *RC = getRegClass(SrcReg);
32
33  // On the order of operands here: think "[FrameIdx + 0] = SrcReg".
34  if (RC == SparcV8::IntRegsRegisterClass)
35    BuildMI (MBB, I, V8::ST, 3).addFrameIndex (FrameIdx).addSImm (0)
36      .addReg (SrcReg);
37  else if (RC == SparcV8::FPRegsRegisterClass)
38    BuildMI (MBB, I, V8::STFri, 3).addFrameIndex (FrameIdx).addSImm (0)
39      .addReg (SrcReg);
40  else if (RC == SparcV8::DFPRegsRegisterClass)
41    BuildMI (MBB, I, V8::STDFri, 3).addFrameIndex (FrameIdx).addSImm (0)
42      .addReg (SrcReg);
43  else
44    assert (0 && "Can't store this register to stack slot");
45  return 1;
46}
47
48int SparcV8RegisterInfo::
49loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
50                     unsigned DestReg, int FrameIdx) const {
51  const TargetRegisterClass *RC = getRegClass(DestReg);
52  if (RC == SparcV8::IntRegsRegisterClass)
53    BuildMI (MBB, I, V8::LD, 2, DestReg).addFrameIndex (FrameIdx).addSImm (0);
54  else if (RC == SparcV8::FPRegsRegisterClass)
55    BuildMI (MBB, I, V8::LDFri, 2, DestReg).addFrameIndex (FrameIdx)
56      .addSImm (0);
57  else if (RC == SparcV8::DFPRegsRegisterClass)
58    BuildMI (MBB, I, V8::LDDFri, 2, DestReg).addFrameIndex (FrameIdx)
59      .addSImm (0);
60  else
61    assert (0 && "Can't load this register from stack slot");
62  return 1;
63}
64
65int SparcV8RegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
66                                      MachineBasicBlock::iterator I,
67                                      unsigned DestReg, unsigned SrcReg,
68                                      const TargetRegisterClass *RC) const {
69  if (RC == SparcV8::IntRegsRegisterClass)
70    BuildMI (MBB, I, V8::ORrr, 2, DestReg).addReg (V8::G0).addReg (SrcReg);
71  else if (RC == SparcV8::FPRegsRegisterClass)
72    BuildMI (MBB, I, V8::FMOVS, 1, DestReg).addReg (SrcReg);
73  else
74    assert (0 && "Can't copy this register");
75  return 1;
76}
77
78void SparcV8RegisterInfo::
79eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
80                              MachineBasicBlock::iterator I) const {
81  std::cerr
82    << "Sorry, I don't know how to eliminate call frame pseudo instrs yet, in\n"
83    << __FUNCTION__ << " at " << __FILE__ << ":" << __LINE__ << "\n";
84  abort();
85}
86
87void
88SparcV8RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
89  unsigned i = 0;
90  MachineInstr &MI = *II;
91  while (!MI.getOperand(i).isFrameIndex()) {
92    ++i;
93    assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
94  }
95
96  int FrameIndex = MI.getOperand(i).getFrameIndex();
97
98  // Replace frame index with a frame pointer reference
99  MI.SetMachineOperandReg (i, V8::FP);
100
101  // Addressable stack objects are accessed using neg. offsets from %fp
102  MachineFunction &MF = *MI.getParent()->getParent();
103  int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
104               MI.getOperand(i+1).getImmedValue();
105  // note: Offset < 0
106  MI.SetMachineOperandConst (i+1, MachineOperand::MO_SignExtendedImmed, Offset);
107}
108
109void SparcV8RegisterInfo::
110processFunctionBeforeFrameFinalized(MachineFunction &MF) const {}
111
112void SparcV8RegisterInfo::emitPrologue(MachineFunction &MF) const {
113  MachineBasicBlock &MBB = MF.front();
114  MachineFrameInfo *MFI = MF.getFrameInfo();
115
116  // Get the number of bytes to allocate from the FrameInfo
117  int NumBytes = (int) MFI->getStackSize();
118
119  // Emit the correct save instruction based on the number of bytes in the frame.
120  // Minimum stack frame size according to V8 ABI is:
121  //   16 words for register window spill
122  //    1 word for address of returned aggregate-value
123  // +  6 words for passing parameters on the stack
124  // ----------
125  //   23 words * 4 bytes per word = 92 bytes
126  NumBytes += 92;
127  // Round up to next doubleword boundary -- a double-word boundary
128  // is required by the ABI.
129  NumBytes = (NumBytes + 7) & ~7;
130  BuildMI(MBB, MBB.begin(), V8::SAVEri, 2,
131          V8::SP).addImm(-NumBytes).addReg(V8::SP);
132}
133
134void SparcV8RegisterInfo::emitEpilogue(MachineFunction &MF,
135                                       MachineBasicBlock &MBB) const {
136  MachineBasicBlock::iterator MBBI = prior(MBB.end());
137  assert(MBBI->getOpcode() == V8::RETL &&
138         "Can only put epilog before 'retl' instruction!");
139  BuildMI(MBB, MBBI, V8::RESTORErr, 2, V8::G0).addReg(V8::G0).addReg(V8::G0);
140}
141
142#include "SparcV8GenRegisterInfo.inc"
143
144const TargetRegisterClass*
145SparcV8RegisterInfo::getRegClassForType(const Type* Ty) const {
146  switch (Ty->getTypeID()) {
147  case Type::FloatTyID:  return &FPRegsInstance;
148  case Type::DoubleTyID: return &DFPRegsInstance;
149  case Type::LongTyID:
150  case Type::ULongTyID:  assert(0 && "Long values do not fit in registers!");
151  default:               assert(0 && "Invalid type to getClass!");
152  case Type::BoolTyID:
153  case Type::SByteTyID:
154  case Type::UByteTyID:
155  case Type::ShortTyID:
156  case Type::UShortTyID:
157  case Type::IntTyID:
158  case Type::UIntTyID:
159  case Type::PointerTyID: return &IntRegsInstance;
160  }
161}
162
163