SparcRegisterInfo.cpp revision 6844f7bcdec8c2691c8d1067d90e4a02cf658c27 
1//===- SparcRegisterInfo.cpp - SPARC Register Information -------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the SPARC implementation of the TargetRegisterInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "Sparc.h"
15#include "SparcRegisterInfo.h"
16#include "SparcSubtarget.h"
17#include "llvm/CodeGen/MachineInstrBuilder.h"
18#include "llvm/CodeGen/MachineFunction.h"
19#include "llvm/CodeGen/MachineFrameInfo.h"
20#include "llvm/CodeGen/MachineLocation.h"
21#include "llvm/Support/ErrorHandling.h"
22#include "llvm/Target/TargetInstrInfo.h"
23#include "llvm/Type.h"
24#include "llvm/ADT/BitVector.h"
25#include "llvm/ADT/STLExtras.h"
26
27#define GET_REGINFO_MC_DESC
28#define GET_REGINFO_TARGET_DESC
29#include "SparcGenRegisterInfo.inc"
30
31using namespace llvm;
32
33SparcRegisterInfo::SparcRegisterInfo(SparcSubtarget &st,
34                                     const TargetInstrInfo &tii)
35  : SparcGenRegisterInfo(SP::ADJCALLSTACKDOWN, SP::ADJCALLSTACKUP),
36    Subtarget(st), TII(tii) {
37}
38
39const unsigned* SparcRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF)
40                                                                         const {
41  static const unsigned CalleeSavedRegs[] = { 0 };
42  return CalleeSavedRegs;
43}
44
45BitVector SparcRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
46  BitVector Reserved(getNumRegs());
47  // FIXME: G1 reserved for now for large imm generation by frame code.
48  Reserved.set(SP::G1);
49  Reserved.set(SP::G2);
50  Reserved.set(SP::G3);
51  Reserved.set(SP::G4);
52  Reserved.set(SP::O6);
53  Reserved.set(SP::I6);
54  Reserved.set(SP::I7);
55  Reserved.set(SP::G0);
56  Reserved.set(SP::G5);
57  Reserved.set(SP::G6);
58  Reserved.set(SP::G7);
59  return Reserved;
60}
61
62void SparcRegisterInfo::
63eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
64                              MachineBasicBlock::iterator I) const {
65  MachineInstr &MI = *I;
66  DebugLoc dl = MI.getDebugLoc();
67  int Size = MI.getOperand(0).getImm();
68  if (MI.getOpcode() == SP::ADJCALLSTACKDOWN)
69    Size = -Size;
70  if (Size)
71    BuildMI(MBB, I, dl, TII.get(SP::ADDri), SP::O6).addReg(SP::O6).addImm(Size);
72  MBB.erase(I);
73}
74
75void
76SparcRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
77                                       int SPAdj, RegScavenger *RS) const {
78  assert(SPAdj == 0 && "Unexpected");
79
80  unsigned i = 0;
81  MachineInstr &MI = *II;
82  DebugLoc dl = MI.getDebugLoc();
83  while (!MI.getOperand(i).isFI()) {
84    ++i;
85    assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
86  }
87
88  int FrameIndex = MI.getOperand(i).getIndex();
89
90  // Addressable stack objects are accessed using neg. offsets from %fp
91  MachineFunction &MF = *MI.getParent()->getParent();
92  int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
93               MI.getOperand(i+1).getImm();
94
95  // Replace frame index with a frame pointer reference.
96  if (Offset >= -4096 && Offset <= 4095) {
97    // If the offset is small enough to fit in the immediate field, directly
98    // encode it.
99    MI.getOperand(i).ChangeToRegister(SP::I6, false);
100    MI.getOperand(i+1).ChangeToImmediate(Offset);
101  } else {
102    // Otherwise, emit a G1 = SETHI %hi(offset).  FIXME: it would be better to
103    // scavenge a register here instead of reserving G1 all of the time.
104    unsigned OffHi = (unsigned)Offset >> 10U;
105    BuildMI(*MI.getParent(), II, dl, TII.get(SP::SETHIi), SP::G1).addImm(OffHi);
106    // Emit G1 = G1 + I6
107    BuildMI(*MI.getParent(), II, dl, TII.get(SP::ADDrr), SP::G1).addReg(SP::G1)
108      .addReg(SP::I6);
109    // Insert: G1+%lo(offset) into the user.
110    MI.getOperand(i).ChangeToRegister(SP::G1, false);
111    MI.getOperand(i+1).ChangeToImmediate(Offset & ((1 << 10)-1));
112  }
113}
114
115void SparcRegisterInfo::
116processFunctionBeforeFrameFinalized(MachineFunction &MF) const {}
117
118unsigned SparcRegisterInfo::getRARegister() const {
119  return SP::I7;
120}
121
122unsigned SparcRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
123  return SP::I6;
124}
125
126unsigned SparcRegisterInfo::getEHExceptionRegister() const {
127  llvm_unreachable("What is the exception register");
128  return 0;
129}
130
131unsigned SparcRegisterInfo::getEHHandlerRegister() const {
132  llvm_unreachable("What is the exception handler register");
133  return 0;
134}
135
136int SparcRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
137  return SparcGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
138}
139
140int SparcRegisterInfo::getLLVMRegNum(unsigned DwarfRegNo, bool isEH) const {
141  return SparcGenRegisterInfo::getLLVMRegNumFull(DwarfRegNo,0);
142}
143