SparcRegisterInfo.cpp revision 6bd555176318e802bfe987ab7d7f34eee45d1423
18e01cdce135d5d816f92d7bb83f9a930aa1b45aeLucas Eckels//===- SparcV8RegisterInfo.cpp - SparcV8 Register Information ---*- C++ -*-===// 28e01cdce135d5d816f92d7bb83f9a930aa1b45aeLucas Eckels// 38e01cdce135d5d816f92d7bb83f9a930aa1b45aeLucas Eckels// The LLVM Compiler Infrastructure 48e01cdce135d5d816f92d7bb83f9a930aa1b45aeLucas Eckels// 58e01cdce135d5d816f92d7bb83f9a930aa1b45aeLucas Eckels// This file was developed by the LLVM research group and is distributed under 68e01cdce135d5d816f92d7bb83f9a930aa1b45aeLucas Eckels// the University of Illinois Open Source License. See LICENSE.TXT for details. 78e01cdce135d5d816f92d7bb83f9a930aa1b45aeLucas Eckels// 88e01cdce135d5d816f92d7bb83f9a930aa1b45aeLucas Eckels//===----------------------------------------------------------------------===// 98e01cdce135d5d816f92d7bb83f9a930aa1b45aeLucas Eckels// 108e01cdce135d5d816f92d7bb83f9a930aa1b45aeLucas Eckels// This file contains the SparcV8 implementation of the MRegisterInfo class. 118e01cdce135d5d816f92d7bb83f9a930aa1b45aeLucas Eckels// 128e01cdce135d5d816f92d7bb83f9a930aa1b45aeLucas Eckels//===----------------------------------------------------------------------===// 138e01cdce135d5d816f92d7bb83f9a930aa1b45aeLucas Eckels 148e01cdce135d5d816f92d7bb83f9a930aa1b45aeLucas Eckels#include "SparcV8.h" 158e01cdce135d5d816f92d7bb83f9a930aa1b45aeLucas Eckels#include "SparcV8RegisterInfo.h" 168e01cdce135d5d816f92d7bb83f9a930aa1b45aeLucas Eckels#include "llvm/CodeGen/MachineInstrBuilder.h" 178e01cdce135d5d816f92d7bb83f9a930aa1b45aeLucas Eckels#include "llvm/CodeGen/MachineFunction.h" 188e01cdce135d5d816f92d7bb83f9a930aa1b45aeLucas Eckels#include "llvm/CodeGen/MachineFrameInfo.h" 198e01cdce135d5d816f92d7bb83f9a930aa1b45aeLucas Eckels#include "llvm/Type.h" 208e01cdce135d5d816f92d7bb83f9a930aa1b45aeLucas Eckels#include "Support/STLExtras.h" 218e01cdce135d5d816f92d7bb83f9a930aa1b45aeLucas Eckelsusing namespace llvm; 228e01cdce135d5d816f92d7bb83f9a930aa1b45aeLucas Eckels 238e01cdce135d5d816f92d7bb83f9a930aa1b45aeLucas EckelsSparcV8RegisterInfo::SparcV8RegisterInfo() 248e01cdce135d5d816f92d7bb83f9a930aa1b45aeLucas Eckels : SparcV8GenRegisterInfo(V8::ADJCALLSTACKDOWN, 258e01cdce135d5d816f92d7bb83f9a930aa1b45aeLucas Eckels V8::ADJCALLSTACKUP) {} 268e01cdce135d5d816f92d7bb83f9a930aa1b45aeLucas Eckels 278e01cdce135d5d816f92d7bb83f9a930aa1b45aeLucas Eckelsint SparcV8RegisterInfo::storeRegToStackSlot( 288e01cdce135d5d816f92d7bb83f9a930aa1b45aeLucas Eckels MachineBasicBlock &MBB, 298e01cdce135d5d816f92d7bb83f9a930aa1b45aeLucas Eckels MachineBasicBlock::iterator I, 308e01cdce135d5d816f92d7bb83f9a930aa1b45aeLucas Eckels unsigned SrcReg, int FrameIdx, 318e01cdce135d5d816f92d7bb83f9a930aa1b45aeLucas Eckels const TargetRegisterClass *RC) const 328e01cdce135d5d816f92d7bb83f9a930aa1b45aeLucas Eckels{ 338e01cdce135d5d816f92d7bb83f9a930aa1b45aeLucas Eckels // On the order of operands here: think "[FrameIdx + 0] = SrcReg". 348e01cdce135d5d816f92d7bb83f9a930aa1b45aeLucas Eckels if (RC == SparcV8::IntRegsRegisterClass) 358e01cdce135d5d816f92d7bb83f9a930aa1b45aeLucas Eckels BuildMI (MBB, I, V8::ST, 3).addFrameIndex (FrameIdx).addSImm (0) 368e01cdce135d5d816f92d7bb83f9a930aa1b45aeLucas Eckels .addReg (SrcReg); 378e01cdce135d5d816f92d7bb83f9a930aa1b45aeLucas Eckels else if (RC == SparcV8::FPRegsRegisterClass) 388e01cdce135d5d816f92d7bb83f9a930aa1b45aeLucas Eckels BuildMI (MBB, I, V8::STFri, 3).addFrameIndex (FrameIdx).addSImm (0) 398e01cdce135d5d816f92d7bb83f9a930aa1b45aeLucas Eckels .addReg (SrcReg); 408e01cdce135d5d816f92d7bb83f9a930aa1b45aeLucas Eckels else if (RC == SparcV8::DFPRegsRegisterClass) 418e01cdce135d5d816f92d7bb83f9a930aa1b45aeLucas Eckels BuildMI (MBB, I, V8::STDFri, 3).addFrameIndex (FrameIdx).addSImm (0) 428e01cdce135d5d816f92d7bb83f9a930aa1b45aeLucas Eckels .addReg (SrcReg); 438e01cdce135d5d816f92d7bb83f9a930aa1b45aeLucas Eckels else 448e01cdce135d5d816f92d7bb83f9a930aa1b45aeLucas Eckels assert (0 && "Can't store this register to stack slot"); 458e01cdce135d5d816f92d7bb83f9a930aa1b45aeLucas Eckels return 1; 468e01cdce135d5d816f92d7bb83f9a930aa1b45aeLucas Eckels} 478e01cdce135d5d816f92d7bb83f9a930aa1b45aeLucas Eckels 488e01cdce135d5d816f92d7bb83f9a930aa1b45aeLucas Eckelsint SparcV8RegisterInfo::loadRegFromStackSlot( 498e01cdce135d5d816f92d7bb83f9a930aa1b45aeLucas Eckels MachineBasicBlock &MBB, 50 MachineBasicBlock::iterator I, 51 unsigned DestReg, int FrameIdx, 52 const TargetRegisterClass *RC) const 53{ 54 if (RC == SparcV8::IntRegsRegisterClass) 55 BuildMI (MBB, I, V8::LD, 2, DestReg).addFrameIndex (FrameIdx).addSImm (0); 56 else if (RC == SparcV8::FPRegsRegisterClass) 57 BuildMI (MBB, I, V8::LDFri, 2, DestReg).addFrameIndex (FrameIdx) 58 .addSImm (0); 59 else if (RC == SparcV8::DFPRegsRegisterClass) 60 BuildMI (MBB, I, V8::LDDFri, 2, DestReg).addFrameIndex (FrameIdx) 61 .addSImm (0); 62 else 63 assert (0 && "Can't load this register from stack slot"); 64 return 1; 65} 66 67int SparcV8RegisterInfo::copyRegToReg(MachineBasicBlock &MBB, 68 MachineBasicBlock::iterator I, 69 unsigned DestReg, unsigned SrcReg, 70 const TargetRegisterClass *RC) const { 71 if (RC == SparcV8::IntRegsRegisterClass) 72 BuildMI (MBB, I, V8::ORrr, 2, DestReg).addReg (V8::G0).addReg (SrcReg); 73 else if (RC == SparcV8::FPRegsRegisterClass) 74 BuildMI (MBB, I, V8::FMOVS, 1, DestReg).addReg (SrcReg); 75 else 76 assert (0 && "Can't copy this register"); 77 return 1; 78} 79 80void SparcV8RegisterInfo:: 81eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, 82 MachineBasicBlock::iterator I) const { 83 std::cerr 84 << "Sorry, I don't know how to eliminate call frame pseudo instrs yet, in\n" 85 << __FUNCTION__ << " at " << __FILE__ << ":" << __LINE__ << "\n"; 86 abort(); 87} 88 89void 90SparcV8RegisterInfo::eliminateFrameIndex(MachineFunction &MF, 91 MachineBasicBlock::iterator II) const { 92 unsigned i = 0; 93 MachineInstr &MI = *II; 94 while (!MI.getOperand(i).isFrameIndex()) { 95 ++i; 96 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); 97 } 98 99 int FrameIndex = MI.getOperand(i).getFrameIndex(); 100 101 // Replace frame index with a frame pointer reference 102 MI.SetMachineOperandReg (i, V8::FP); 103 104 // Addressable stack objects are accessed using neg. offsets from %fp 105 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) + 106 MI.getOperand(i+1).getImmedValue(); 107 // note: Offset < 0 108 MI.SetMachineOperandConst (i+1, MachineOperand::MO_SignExtendedImmed, Offset); 109} 110 111void SparcV8RegisterInfo:: 112processFunctionBeforeFrameFinalized(MachineFunction &MF) const {} 113 114void SparcV8RegisterInfo::emitPrologue(MachineFunction &MF) const { 115 MachineBasicBlock &MBB = MF.front(); 116 MachineFrameInfo *MFI = MF.getFrameInfo(); 117 118 // Get the number of bytes to allocate from the FrameInfo 119 int NumBytes = (int) MFI->getStackSize(); 120 121 // Emit the correct save instruction based on the number of bytes in the frame. 122 // Minimum stack frame size according to V8 ABI is: 123 // 16 words for register window spill 124 // 1 word for address of returned aggregate-value 125 // + 6 words for passing parameters on the stack 126 // ---------- 127 // 23 words * 4 bytes per word = 92 bytes 128 NumBytes += 92; 129 // Round up to next doubleword boundary -- a double-word boundary 130 // is required by the ABI. 131 NumBytes = (NumBytes + 7) & ~7; 132 BuildMI(MBB, MBB.begin(), V8::SAVEri, 2, 133 V8::SP).addImm(-NumBytes).addReg(V8::SP); 134} 135 136void SparcV8RegisterInfo::emitEpilogue(MachineFunction &MF, 137 MachineBasicBlock &MBB) const { 138 MachineBasicBlock::iterator MBBI = prior(MBB.end()); 139 assert(MBBI->getOpcode() == V8::RETL && 140 "Can only put epilog before 'retl' instruction!"); 141 BuildMI(MBB, MBBI, V8::RESTORErr, 2, V8::G0).addReg(V8::G0).addReg(V8::G0); 142} 143 144#include "SparcV8GenRegisterInfo.inc" 145 146const TargetRegisterClass* 147SparcV8RegisterInfo::getRegClassForType(const Type* Ty) const { 148 switch (Ty->getTypeID()) { 149 case Type::FloatTyID: return &FPRegsInstance; 150 case Type::DoubleTyID: return &DFPRegsInstance; 151 case Type::LongTyID: 152 case Type::ULongTyID: assert(0 && "Long values do not fit in registers!"); 153 default: assert(0 && "Invalid type to getClass!"); 154 case Type::BoolTyID: 155 case Type::SByteTyID: 156 case Type::UByteTyID: 157 case Type::ShortTyID: 158 case Type::UShortTyID: 159 case Type::IntTyID: 160 case Type::UIntTyID: 161 case Type::PointerTyID: return &IntRegsInstance; 162 } 163} 164 165