SparcRegisterInfo.cpp revision 6ee0857bd74dd68e46e970a6bcf756ee03ed8e99
1//===-- SparcRegisterInfo.cpp - SPARC Register Information ----------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the SPARC implementation of the TargetRegisterInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "SparcRegisterInfo.h" 15#include "Sparc.h" 16#include "SparcMachineFunctionInfo.h" 17#include "SparcSubtarget.h" 18#include "llvm/ADT/BitVector.h" 19#include "llvm/ADT/STLExtras.h" 20#include "llvm/CodeGen/MachineFrameInfo.h" 21#include "llvm/CodeGen/MachineFunction.h" 22#include "llvm/CodeGen/MachineInstrBuilder.h" 23#include "llvm/IR/Type.h" 24#include "llvm/Support/CommandLine.h" 25#include "llvm/Support/ErrorHandling.h" 26#include "llvm/Target/TargetInstrInfo.h" 27 28#define GET_REGINFO_TARGET_DESC 29#include "SparcGenRegisterInfo.inc" 30 31using namespace llvm; 32 33static cl::opt<bool> 34ReserveAppRegisters("sparc-reserve-app-registers", cl::Hidden, cl::init(false), 35 cl::desc("Reserve application registers (%g2-%g4)")); 36 37SparcRegisterInfo::SparcRegisterInfo(SparcSubtarget &st) 38 : SparcGenRegisterInfo(SP::I7), Subtarget(st) { 39} 40 41const uint16_t* SparcRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) 42 const { 43 return CSR_SaveList; 44} 45 46const uint32_t* 47SparcRegisterInfo::getCallPreservedMask(CallingConv::ID CC) const { 48 return CSR_RegMask; 49} 50 51BitVector SparcRegisterInfo::getReservedRegs(const MachineFunction &MF) const { 52 BitVector Reserved(getNumRegs()); 53 // FIXME: G1 reserved for now for large imm generation by frame code. 54 Reserved.set(SP::G1); 55 56 // G1-G4 can be used in applications. 57 if (ReserveAppRegisters) { 58 Reserved.set(SP::G2); 59 Reserved.set(SP::G3); 60 Reserved.set(SP::G4); 61 } 62 // G5 is not reserved in 64 bit mode. 63 if (!Subtarget.is64Bit()) 64 Reserved.set(SP::G5); 65 66 Reserved.set(SP::O6); 67 Reserved.set(SP::I6); 68 Reserved.set(SP::I7); 69 Reserved.set(SP::G0); 70 Reserved.set(SP::G6); 71 Reserved.set(SP::G7); 72 73 // Unaliased double registers are not available in non-V9 targets. 74 if (!Subtarget.isV9()) { 75 for (unsigned n = 0; n != 16; ++n) { 76 for (MCRegAliasIterator AI(SP::D16 + n, this, true); AI.isValid(); ++AI) 77 Reserved.set(*AI); 78 } 79 } 80 81 return Reserved; 82} 83 84const TargetRegisterClass* 85SparcRegisterInfo::getPointerRegClass(const MachineFunction &MF, 86 unsigned Kind) const { 87 return Subtarget.is64Bit() ? &SP::I64RegsRegClass : &SP::IntRegsRegClass; 88} 89 90static void replaceFI(MachineFunction &MF, 91 MachineBasicBlock::iterator II, 92 MachineInstr &MI, 93 DebugLoc dl, 94 unsigned FIOperandNum, int Offset, 95 unsigned FramePtr) 96{ 97 // Replace frame index with a frame pointer reference. 98 if (Offset >= -4096 && Offset <= 4095) { 99 // If the offset is small enough to fit in the immediate field, directly 100 // encode it. 101 MI.getOperand(FIOperandNum).ChangeToRegister(FramePtr, false); 102 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset); 103 } else { 104 // Otherwise, emit a G1 = SETHI %hi(offset). FIXME: it would be better to 105 // scavenge a register here instead of reserving G1 all of the time. 106 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); 107 unsigned OffHi = (unsigned)Offset >> 10U; 108 BuildMI(*MI.getParent(), II, dl, TII.get(SP::SETHIi), SP::G1).addImm(OffHi); 109 // Emit G1 = G1 + I6 110 BuildMI(*MI.getParent(), II, dl, TII.get(SP::ADDrr), SP::G1).addReg(SP::G1) 111 .addReg(FramePtr); 112 // Insert: G1+%lo(offset) into the user. 113 MI.getOperand(FIOperandNum).ChangeToRegister(SP::G1, false); 114 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset & ((1 << 10)-1)); 115 } 116} 117 118 119void 120SparcRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, 121 int SPAdj, unsigned FIOperandNum, 122 RegScavenger *RS) const { 123 assert(SPAdj == 0 && "Unexpected"); 124 125 MachineInstr &MI = *II; 126 DebugLoc dl = MI.getDebugLoc(); 127 int FrameIndex = MI.getOperand(FIOperandNum).getIndex(); 128 129 // Addressable stack objects are accessed using neg. offsets from %fp 130 MachineFunction &MF = *MI.getParent()->getParent(); 131 int64_t Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) + 132 MI.getOperand(FIOperandNum + 1).getImm() + 133 Subtarget.getStackPointerBias(); 134 SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>(); 135 unsigned FramePtr = SP::I6; 136 if (FuncInfo->isLeafProc()) { 137 // Use %sp and adjust offset if needed. 138 FramePtr = SP::O6; 139 int stackSize = MF.getFrameInfo()->getStackSize(); 140 Offset += (stackSize) ? Subtarget.getAdjustedFrameSize(stackSize) : 0 ; 141 } 142 143 if (!Subtarget.isV9() || !Subtarget.hasHardQuad()) { 144 if (MI.getOpcode() == SP::STQFri) { 145 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); 146 unsigned SrcReg = MI.getOperand(2).getReg(); 147 unsigned SrcEvenReg = getSubReg(SrcReg, SP::sub_even64); 148 unsigned SrcOddReg = getSubReg(SrcReg, SP::sub_odd64); 149 MachineInstr *StMI = 150 BuildMI(*MI.getParent(), II, dl, TII.get(SP::STDFri)) 151 .addReg(FramePtr).addImm(0).addReg(SrcEvenReg); 152 replaceFI(MF, II, *StMI, dl, 0, Offset, FramePtr); 153 MI.setDesc(TII.get(SP::STDFri)); 154 MI.getOperand(2).setReg(SrcOddReg); 155 Offset += 8; 156 } else if (MI.getOpcode() == SP::LDQFri) { 157 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); 158 unsigned DestReg = MI.getOperand(0).getReg(); 159 unsigned DestEvenReg = getSubReg(DestReg, SP::sub_even64); 160 unsigned DestOddReg = getSubReg(DestReg, SP::sub_odd64); 161 MachineInstr *StMI = 162 BuildMI(*MI.getParent(), II, dl, TII.get(SP::LDDFri), DestEvenReg) 163 .addReg(FramePtr).addImm(0); 164 replaceFI(MF, II, *StMI, dl, 1, Offset, FramePtr); 165 166 MI.setDesc(TII.get(SP::LDDFri)); 167 MI.getOperand(0).setReg(DestOddReg); 168 Offset += 8; 169 } 170 } 171 172 replaceFI(MF, II, MI, dl, FIOperandNum, Offset, FramePtr); 173 174} 175 176unsigned SparcRegisterInfo::getFrameRegister(const MachineFunction &MF) const { 177 return SP::I6; 178} 179 180unsigned SparcRegisterInfo::getEHExceptionRegister() const { 181 llvm_unreachable("What is the exception register"); 182} 183 184unsigned SparcRegisterInfo::getEHHandlerRegister() const { 185 llvm_unreachable("What is the exception handler register"); 186} 187