SparcRegisterInfo.cpp revision 73f50d9bc3bd46cc0abeba9bb0d46977ba1aea42 
1//===- SparcRegisterInfo.cpp - SPARC Register Information -------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the SPARC implementation of the TargetRegisterInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "Sparc.h"
15#include "SparcRegisterInfo.h"
16#include "SparcSubtarget.h"
17#include "llvm/CodeGen/MachineInstrBuilder.h"
18#include "llvm/CodeGen/MachineFunction.h"
19#include "llvm/CodeGen/MachineFrameInfo.h"
20#include "llvm/CodeGen/MachineLocation.h"
21#include "llvm/Support/ErrorHandling.h"
22#include "llvm/Target/TargetInstrInfo.h"
23#include "llvm/Type.h"
24#include "llvm/ADT/BitVector.h"
25#include "llvm/ADT/STLExtras.h"
26
27#define GET_REGINFO_MC_DESC
28#define GET_REGINFO_TARGET_DESC
29#include "SparcGenRegisterInfo.inc"
30
31using namespace llvm;
32
33SparcRegisterInfo::SparcRegisterInfo(SparcSubtarget &st,
34                                     const TargetInstrInfo &tii)
35  : SparcGenRegisterInfo(SparcRegDesc, SparcRegInfoDesc,
36                         SP::ADJCALLSTACKDOWN, SP::ADJCALLSTACKUP),
37    Subtarget(st), TII(tii) {
38}
39
40const unsigned* SparcRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF)
41                                                                         const {
42  static const unsigned CalleeSavedRegs[] = { 0 };
43  return CalleeSavedRegs;
44}
45
46BitVector SparcRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
47  BitVector Reserved(getNumRegs());
48  // FIXME: G1 reserved for now for large imm generation by frame code.
49  Reserved.set(SP::G1);
50  Reserved.set(SP::G2);
51  Reserved.set(SP::G3);
52  Reserved.set(SP::G4);
53  Reserved.set(SP::O6);
54  Reserved.set(SP::I6);
55  Reserved.set(SP::I7);
56  Reserved.set(SP::G0);
57  Reserved.set(SP::G5);
58  Reserved.set(SP::G6);
59  Reserved.set(SP::G7);
60  return Reserved;
61}
62
63void SparcRegisterInfo::
64eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
65                              MachineBasicBlock::iterator I) const {
66  MachineInstr &MI = *I;
67  DebugLoc dl = MI.getDebugLoc();
68  int Size = MI.getOperand(0).getImm();
69  if (MI.getOpcode() == SP::ADJCALLSTACKDOWN)
70    Size = -Size;
71  if (Size)
72    BuildMI(MBB, I, dl, TII.get(SP::ADDri), SP::O6).addReg(SP::O6).addImm(Size);
73  MBB.erase(I);
74}
75
76void
77SparcRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
78                                       int SPAdj, RegScavenger *RS) const {
79  assert(SPAdj == 0 && "Unexpected");
80
81  unsigned i = 0;
82  MachineInstr &MI = *II;
83  DebugLoc dl = MI.getDebugLoc();
84  while (!MI.getOperand(i).isFI()) {
85    ++i;
86    assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
87  }
88
89  int FrameIndex = MI.getOperand(i).getIndex();
90
91  // Addressable stack objects are accessed using neg. offsets from %fp
92  MachineFunction &MF = *MI.getParent()->getParent();
93  int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
94               MI.getOperand(i+1).getImm();
95
96  // Replace frame index with a frame pointer reference.
97  if (Offset >= -4096 && Offset <= 4095) {
98    // If the offset is small enough to fit in the immediate field, directly
99    // encode it.
100    MI.getOperand(i).ChangeToRegister(SP::I6, false);
101    MI.getOperand(i+1).ChangeToImmediate(Offset);
102  } else {
103    // Otherwise, emit a G1 = SETHI %hi(offset).  FIXME: it would be better to
104    // scavenge a register here instead of reserving G1 all of the time.
105    unsigned OffHi = (unsigned)Offset >> 10U;
106    BuildMI(*MI.getParent(), II, dl, TII.get(SP::SETHIi), SP::G1).addImm(OffHi);
107    // Emit G1 = G1 + I6
108    BuildMI(*MI.getParent(), II, dl, TII.get(SP::ADDrr), SP::G1).addReg(SP::G1)
109      .addReg(SP::I6);
110    // Insert: G1+%lo(offset) into the user.
111    MI.getOperand(i).ChangeToRegister(SP::G1, false);
112    MI.getOperand(i+1).ChangeToImmediate(Offset & ((1 << 10)-1));
113  }
114}
115
116void SparcRegisterInfo::
117processFunctionBeforeFrameFinalized(MachineFunction &MF) const {}
118
119unsigned SparcRegisterInfo::getRARegister() const {
120  return SP::I7;
121}
122
123unsigned SparcRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
124  return SP::I6;
125}
126
127unsigned SparcRegisterInfo::getEHExceptionRegister() const {
128  llvm_unreachable("What is the exception register");
129  return 0;
130}
131
132unsigned SparcRegisterInfo::getEHHandlerRegister() const {
133  llvm_unreachable("What is the exception handler register");
134  return 0;
135}
136
137int SparcRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
138  return SparcGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
139}
140
141int SparcRegisterInfo::getLLVMRegNum(unsigned DwarfRegNo, bool isEH) const {
142  return SparcGenRegisterInfo::getLLVMRegNumFull(DwarfRegNo,0);
143}
144