SparcRegisterInfo.cpp revision 97de9138217d6f76f25100df272ec1a3c4d31aad 
1//===- SparcRegisterInfo.cpp - SPARC Register Information -------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file was developed by the LLVM research group and is distributed under
6// the University of Illinois Open Source License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the SPARC implementation of the MRegisterInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "Sparc.h"
15#include "SparcRegisterInfo.h"
16#include "SparcSubtarget.h"
17#include "llvm/CodeGen/MachineInstrBuilder.h"
18#include "llvm/CodeGen/MachineFunction.h"
19#include "llvm/CodeGen/MachineFrameInfo.h"
20#include "llvm/CodeGen/MachineLocation.h"
21#include "llvm/Target/TargetInstrInfo.h"
22#include "llvm/Type.h"
23#include "llvm/ADT/BitVector.h"
24#include "llvm/ADT/STLExtras.h"
25using namespace llvm;
26
27SparcRegisterInfo::SparcRegisterInfo(SparcSubtarget &st,
28                                     const TargetInstrInfo &tii)
29  : SparcGenRegisterInfo(SP::ADJCALLSTACKDOWN, SP::ADJCALLSTACKUP),
30    Subtarget(st), TII(tii) {
31}
32
33void SparcRegisterInfo::
34storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
35                    unsigned SrcReg, int FI,
36                    const TargetRegisterClass *RC) const {
37  // On the order of operands here: think "[FrameIdx + 0] = SrcReg".
38  if (RC == SP::IntRegsRegisterClass)
39    BuildMI(MBB, I, TII.get(SP::STri)).addFrameIndex(FI).addImm(0)
40      .addReg(SrcReg, false, false, true);
41  else if (RC == SP::FPRegsRegisterClass)
42    BuildMI(MBB, I, TII.get(SP::STFri)).addFrameIndex(FI).addImm(0)
43      .addReg(SrcReg, false, false, true);
44  else if (RC == SP::DFPRegsRegisterClass)
45    BuildMI(MBB, I, TII.get(SP::STDFri)).addFrameIndex(FI).addImm(0)
46      .addReg(SrcReg, false, false, true);
47  else
48    assert(0 && "Can't store this register to stack slot");
49}
50
51void SparcRegisterInfo::
52loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
53                     unsigned DestReg, int FI,
54                     const TargetRegisterClass *RC) const {
55  if (RC == SP::IntRegsRegisterClass)
56    BuildMI(MBB, I, TII.get(SP::LDri), DestReg).addFrameIndex(FI).addImm(0);
57  else if (RC == SP::FPRegsRegisterClass)
58    BuildMI(MBB, I, TII.get(SP::LDFri), DestReg).addFrameIndex(FI).addImm(0);
59  else if (RC == SP::DFPRegsRegisterClass)
60    BuildMI(MBB, I, TII.get(SP::LDDFri), DestReg).addFrameIndex(FI).addImm(0);
61  else
62    assert(0 && "Can't load this register from stack slot");
63}
64
65void SparcRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
66                                     MachineBasicBlock::iterator I,
67                                     unsigned DestReg, unsigned SrcReg,
68                                     const TargetRegisterClass *RC) const {
69  if (RC == SP::IntRegsRegisterClass)
70    BuildMI(MBB, I, TII.get(SP::ORrr), DestReg).addReg(SP::G0).addReg(SrcReg);
71  else if (RC == SP::FPRegsRegisterClass)
72    BuildMI(MBB, I, TII.get(SP::FMOVS), DestReg).addReg(SrcReg);
73  else if (RC == SP::DFPRegsRegisterClass)
74    BuildMI(MBB, I, TII.get(Subtarget.isV9() ? SP::FMOVD : SP::FpMOVD),DestReg)
75      .addReg(SrcReg);
76  else
77    assert (0 && "Can't copy this register");
78}
79
80void SparcRegisterInfo::reMaterialize(MachineBasicBlock &MBB,
81                                      MachineBasicBlock::iterator I,
82                                      unsigned DestReg,
83                                      const MachineInstr *Orig) const {
84  MachineInstr *MI = Orig->clone();
85  MI->getOperand(0).setReg(DestReg);
86  MBB.insert(I, MI);
87}
88
89MachineInstr *SparcRegisterInfo::foldMemoryOperand(MachineInstr* MI,
90                                                   unsigned OpNum,
91                                                   int FI) const {
92  bool isFloat = false;
93  MachineInstr *NewMI = NULL;
94  switch (MI->getOpcode()) {
95  case SP::ORrr:
96    if (MI->getOperand(1).isRegister() && MI->getOperand(1).getReg() == SP::G0&&
97        MI->getOperand(0).isRegister() && MI->getOperand(2).isRegister()) {
98      if (OpNum == 0)    // COPY -> STORE
99        NewMI = BuildMI(TII.get(SP::STri)).addFrameIndex(FI).addImm(0)
100                                   .addReg(MI->getOperand(2).getReg());
101      else               // COPY -> LOAD
102        NewMI = BuildMI(TII.get(SP::LDri), MI->getOperand(0).getReg())
103                      .addFrameIndex(FI).addImm(0);
104    }
105    break;
106  case SP::FMOVS:
107    isFloat = true;
108    // FALLTHROUGH
109  case SP::FMOVD:
110    if (OpNum == 0)  // COPY -> STORE
111      NewMI = BuildMI(TII.get(isFloat ? SP::STFri : SP::STDFri))
112               .addFrameIndex(FI).addImm(0).addReg(MI->getOperand(1).getReg());
113    else             // COPY -> LOAD
114      NewMI = BuildMI(TII.get(isFloat ? SP::LDFri : SP::LDDFri),
115                     MI->getOperand(0).getReg()).addFrameIndex(FI).addImm(0);
116    break;
117  }
118
119  if (NewMI)
120    NewMI->copyKillDeadInfo(MI);
121  return NewMI;
122}
123
124const unsigned* SparcRegisterInfo::getCalleeSavedRegs() const {
125  static const unsigned CalleeSavedRegs[] = { 0 };
126  return CalleeSavedRegs;
127}
128
129BitVector SparcRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
130  BitVector Reserved(getNumRegs());
131  Reserved.set(SP::G2);
132  Reserved.set(SP::G3);
133  Reserved.set(SP::G4);
134  Reserved.set(SP::O6);
135  Reserved.set(SP::I6);
136  Reserved.set(SP::I7);
137  Reserved.set(SP::G0);
138  Reserved.set(SP::G5);
139  Reserved.set(SP::G6);
140  Reserved.set(SP::G7);
141  return Reserved;
142}
143
144
145const TargetRegisterClass* const*
146SparcRegisterInfo::getCalleeSavedRegClasses() const {
147  static const TargetRegisterClass * const CalleeSavedRegClasses[] = { 0 };
148  return CalleeSavedRegClasses;
149}
150
151bool SparcRegisterInfo::hasFP(const MachineFunction &MF) const {
152  return false;
153}
154
155void SparcRegisterInfo::
156eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
157                              MachineBasicBlock::iterator I) const {
158  MachineInstr &MI = *I;
159  int Size = MI.getOperand(0).getImmedValue();
160  if (MI.getOpcode() == SP::ADJCALLSTACKDOWN)
161    Size = -Size;
162  if (Size)
163    BuildMI(MBB, I, TII.get(SP::ADDri), SP::O6).addReg(SP::O6).addImm(Size);
164  MBB.erase(I);
165}
166
167void SparcRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
168                                            int SPAdj, RegScavenger *RS) const {
169  assert(SPAdj == 0 && "Unexpected");
170
171  unsigned i = 0;
172  MachineInstr &MI = *II;
173  while (!MI.getOperand(i).isFrameIndex()) {
174    ++i;
175    assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
176  }
177
178  int FrameIndex = MI.getOperand(i).getFrameIndex();
179
180  // Addressable stack objects are accessed using neg. offsets from %fp
181  MachineFunction &MF = *MI.getParent()->getParent();
182  int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
183               MI.getOperand(i+1).getImmedValue();
184
185  // Replace frame index with a frame pointer reference.
186  if (Offset >= -4096 && Offset <= 4095) {
187    // If the offset is small enough to fit in the immediate field, directly
188    // encode it.
189    MI.getOperand(i).ChangeToRegister(SP::I6, false);
190    MI.getOperand(i+1).ChangeToImmediate(Offset);
191  } else {
192    // Otherwise, emit a G1 = SETHI %hi(offset).  FIXME: it would be better to
193    // scavenge a register here instead of reserving G1 all of the time.
194    unsigned OffHi = (unsigned)Offset >> 10U;
195    BuildMI(*MI.getParent(), II, TII.get(SP::SETHIi), SP::G1).addImm(OffHi);
196    // Emit G1 = G1 + I6
197    BuildMI(*MI.getParent(), II, TII.get(SP::ADDrr), SP::G1).addReg(SP::G1)
198      .addReg(SP::I6);
199    // Insert: G1+%lo(offset) into the user.
200    MI.getOperand(i).ChangeToRegister(SP::G1, false);
201    MI.getOperand(i+1).ChangeToImmediate(Offset & ((1 << 10)-1));
202  }
203}
204
205void SparcRegisterInfo::
206processFunctionBeforeFrameFinalized(MachineFunction &MF) const {}
207
208void SparcRegisterInfo::emitPrologue(MachineFunction &MF) const {
209  MachineBasicBlock &MBB = MF.front();
210  MachineFrameInfo *MFI = MF.getFrameInfo();
211
212  // Get the number of bytes to allocate from the FrameInfo
213  int NumBytes = (int) MFI->getStackSize();
214
215  // Emit the correct save instruction based on the number of bytes in
216  // the frame. Minimum stack frame size according to V8 ABI is:
217  //   16 words for register window spill
218  //    1 word for address of returned aggregate-value
219  // +  6 words for passing parameters on the stack
220  // ----------
221  //   23 words * 4 bytes per word = 92 bytes
222  NumBytes += 92;
223  // Round up to next doubleword boundary -- a double-word boundary
224  // is required by the ABI.
225  NumBytes = (NumBytes + 7) & ~7;
226  NumBytes = -NumBytes;
227
228  if (NumBytes >= -4096) {
229    BuildMI(MBB, MBB.begin(), TII.get(SP::SAVEri),
230            SP::O6).addImm(NumBytes).addReg(SP::O6);
231  } else {
232    MachineBasicBlock::iterator InsertPt = MBB.begin();
233    // Emit this the hard way.  This clobbers G1 which we always know is
234    // available here.
235    unsigned OffHi = (unsigned)NumBytes >> 10U;
236    BuildMI(MBB, InsertPt, TII.get(SP::SETHIi), SP::G1).addImm(OffHi);
237    // Emit G1 = G1 + I6
238    BuildMI(MBB, InsertPt, TII.get(SP::ORri), SP::G1)
239      .addReg(SP::G1).addImm(NumBytes & ((1 << 10)-1));
240    BuildMI(MBB, InsertPt, TII.get(SP::SAVErr), SP::O6)
241      .addReg(SP::O6).addReg(SP::G1);
242  }
243}
244
245void SparcRegisterInfo::emitEpilogue(MachineFunction &MF,
246                                     MachineBasicBlock &MBB) const {
247  MachineBasicBlock::iterator MBBI = prior(MBB.end());
248  assert(MBBI->getOpcode() == SP::RETL &&
249         "Can only put epilog before 'retl' instruction!");
250  BuildMI(MBB, MBBI, TII.get(SP::RESTORErr), SP::G0).addReg(SP::G0)
251    .addReg(SP::G0);
252}
253
254unsigned SparcRegisterInfo::getRARegister() const {
255  assert(0 && "What is the return address register");
256  return 0;
257}
258
259unsigned SparcRegisterInfo::getFrameRegister(MachineFunction &MF) const {
260  assert(0 && "What is the frame register");
261  return SP::G1;
262}
263
264unsigned SparcRegisterInfo::getEHExceptionRegister() const {
265  assert(0 && "What is the exception register");
266  return 0;
267}
268
269unsigned SparcRegisterInfo::getEHHandlerRegister() const {
270  assert(0 && "What is the exception handler register");
271  return 0;
272}
273
274#include "SparcGenRegisterInfo.inc"
275
276