SparcRegisterInfo.cpp revision be81e82afcaa3e1b80ae26d7ec07f0dbccbccc58 
1//===- SparcV8RegisterInfo.cpp - SparcV8 Register Information ---*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file was developed by the LLVM research group and is distributed under
6// the University of Illinois Open Source License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the SparcV8 implementation of the MRegisterInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "SparcV8.h"
15#include "SparcV8RegisterInfo.h"
16#include "llvm/CodeGen/MachineInstrBuilder.h"
17#include "llvm/CodeGen/MachineFunction.h"
18#include "llvm/CodeGen/MachineFrameInfo.h"
19#include "llvm/Type.h"
20#include "Support/STLExtras.h"
21using namespace llvm;
22
23SparcV8RegisterInfo::SparcV8RegisterInfo()
24  : SparcV8GenRegisterInfo(V8::ADJCALLSTACKDOWN,
25                           V8::ADJCALLSTACKUP) {}
26
27int SparcV8RegisterInfo::storeRegToStackSlot(
28  MachineBasicBlock &MBB,
29  MachineBasicBlock::iterator I,
30  unsigned SrcReg, int FrameIdx,
31  const TargetRegisterClass *RC) const
32{
33  assert (RC == SparcV8::IntRegsRegisterClass
34          && "Can only store 32-bit values to stack slots");
35  // On the order of operands here: think "[FrameIdx + 0] = SrcReg".
36  BuildMI (MBB, I, V8::ST, 3).addFrameIndex (FrameIdx).addSImm (0).addReg (SrcReg);
37  return 1;
38}
39
40int SparcV8RegisterInfo::loadRegFromStackSlot(
41  MachineBasicBlock &MBB,
42  MachineBasicBlock::iterator I,
43  unsigned DestReg, int FrameIdx,
44  const TargetRegisterClass *RC) const
45{
46  assert (RC == SparcV8::IntRegsRegisterClass
47          && "Can only load 32-bit registers from stack slots");
48  BuildMI (MBB, I, V8::LD, 2, DestReg).addFrameIndex (FrameIdx).addSImm (0);
49  return 1;
50}
51
52int SparcV8RegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
53                                      MachineBasicBlock::iterator I,
54                                      unsigned DestReg, unsigned SrcReg,
55                                      const TargetRegisterClass *RC) const {
56  assert (RC == SparcV8::IntRegsRegisterClass
57          && "Can only copy 32-bit registers");
58  BuildMI (MBB, I, V8::ORrr, 2, DestReg).addReg (V8::G0).addReg (SrcReg);
59  return 1;
60}
61
62void SparcV8RegisterInfo::
63eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
64                              MachineBasicBlock::iterator I) const {
65  std::cerr
66    << "Sorry, I don't know how to eliminate call frame pseudo instrs yet, in\n"
67    << __FUNCTION__ << " at " << __FILE__ << ":" << __LINE__ << "\n";
68  abort();
69}
70
71void
72SparcV8RegisterInfo::eliminateFrameIndex(MachineFunction &MF,
73                                         MachineBasicBlock::iterator II) const {
74  unsigned i = 0;
75  MachineInstr &MI = *II;
76  while (!MI.getOperand(i).isFrameIndex()) {
77    ++i;
78    assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
79  }
80
81  int FrameIndex = MI.getOperand(i).getFrameIndex();
82
83  // Replace frame index with a frame pointer reference
84  MI.SetMachineOperandReg (i, V8::FP);
85
86  // Addressable stack objects are accessed using neg. offsets from %fp
87  int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
88               MI.getOperand(i+1).getImmedValue();
89  // note: Offset < 0
90  MI.SetMachineOperandConst (i+1, MachineOperand::MO_SignExtendedImmed, Offset);
91}
92
93void SparcV8RegisterInfo::
94processFunctionBeforeFrameFinalized(MachineFunction &MF) const {}
95
96void SparcV8RegisterInfo::emitPrologue(MachineFunction &MF) const {
97  MachineBasicBlock &MBB = MF.front();
98  MachineFrameInfo *MFI = MF.getFrameInfo();
99
100  // Get the number of bytes to allocate from the FrameInfo
101  int NumBytes = (int) MFI->getStackSize();
102
103  // Emit the correct save instruction based on the number of bytes in the frame.
104  // Minimum stack frame size according to V8 ABI is:
105  //   16 words for register window spill
106  //    1 word for address of returned aggregate-value
107  // +  6 words for passing parameters on the stack
108  // ----------
109  //   23 words * 4 bytes per word = 92 bytes
110  NumBytes += 92;
111  // Round up to next doubleword boundary -- a double-word boundary
112  // is required by the ABI.
113  NumBytes = (NumBytes + 7) & ~7;
114  BuildMI(MBB, MBB.begin(), V8::SAVEri, 2,
115          V8::SP).addImm(-NumBytes).addReg(V8::SP);
116}
117
118void SparcV8RegisterInfo::emitEpilogue(MachineFunction &MF,
119                                       MachineBasicBlock &MBB) const {
120  MachineBasicBlock::iterator MBBI = prior(MBB.end());
121  assert(MBBI->getOpcode() == V8::RETL &&
122         "Can only put epilog before 'retl' instruction!");
123  BuildMI(MBB, MBBI, V8::RESTORErr, 2, V8::G0).addReg(V8::G0).addReg(V8::G0);
124}
125
126#include "SparcV8GenRegisterInfo.inc"
127
128const TargetRegisterClass*
129SparcV8RegisterInfo::getRegClassForType(const Type* Ty) const {
130  switch (Ty->getTypeID()) {
131  case Type::FloatTyID:  return &FPRegsInstance;
132  case Type::DoubleTyID: return &DFPRegsInstance;
133  case Type::LongTyID:
134  case Type::ULongTyID:  assert(0 && "Long values do not fit in registers!");
135  default:               assert(0 && "Invalid type to getClass!");
136  case Type::BoolTyID:
137  case Type::SByteTyID:
138  case Type::UByteTyID:
139  case Type::ShortTyID:
140  case Type::UShortTyID:
141  case Type::IntTyID:
142  case Type::UIntTyID:
143  case Type::PointerTyID: return &IntRegsInstance;
144  }
145}
146
147