SparcRegisterInfo.cpp revision e594fd473ef5b484268935f3e80da3cd3331149f 
1//===- SparcRegisterInfo.cpp - SPARC Register Information -------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the SPARC implementation of the TargetRegisterInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "Sparc.h"
15#include "SparcRegisterInfo.h"
16#include "SparcSubtarget.h"
17#include "llvm/CodeGen/MachineInstrBuilder.h"
18#include "llvm/CodeGen/MachineFunction.h"
19#include "llvm/CodeGen/MachineFrameInfo.h"
20#include "llvm/CodeGen/MachineLocation.h"
21#include "llvm/Target/TargetInstrInfo.h"
22#include "llvm/Type.h"
23#include "llvm/ADT/BitVector.h"
24#include "llvm/ADT/STLExtras.h"
25using namespace llvm;
26
27SparcRegisterInfo::SparcRegisterInfo(SparcSubtarget &st,
28                                     const TargetInstrInfo &tii)
29  : SparcGenRegisterInfo(SP::ADJCALLSTACKDOWN, SP::ADJCALLSTACKUP),
30    Subtarget(st), TII(tii) {
31}
32
33const unsigned* SparcRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF)
34                                                                         const {
35  static const unsigned CalleeSavedRegs[] = { 0 };
36  return CalleeSavedRegs;
37}
38
39BitVector SparcRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
40  BitVector Reserved(getNumRegs());
41  Reserved.set(SP::G2);
42  Reserved.set(SP::G3);
43  Reserved.set(SP::G4);
44  Reserved.set(SP::O6);
45  Reserved.set(SP::I6);
46  Reserved.set(SP::I7);
47  Reserved.set(SP::G0);
48  Reserved.set(SP::G5);
49  Reserved.set(SP::G6);
50  Reserved.set(SP::G7);
51  return Reserved;
52}
53
54
55const TargetRegisterClass* const*
56SparcRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
57  static const TargetRegisterClass * const CalleeSavedRegClasses[] = { 0 };
58  return CalleeSavedRegClasses;
59}
60
61bool SparcRegisterInfo::hasFP(const MachineFunction &MF) const {
62  return false;
63}
64
65void SparcRegisterInfo::
66eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
67                              MachineBasicBlock::iterator I) const {
68  MachineInstr &MI = *I;
69  int Size = MI.getOperand(0).getImm();
70  if (MI.getOpcode() == SP::ADJCALLSTACKDOWN)
71    Size = -Size;
72  if (Size)
73    BuildMI(MBB, I, TII.get(SP::ADDri), SP::O6).addReg(SP::O6).addImm(Size);
74  MBB.erase(I);
75}
76
77void SparcRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
78                                            int SPAdj, RegScavenger *RS) const {
79  assert(SPAdj == 0 && "Unexpected");
80
81  unsigned i = 0;
82  MachineInstr &MI = *II;
83  while (!MI.getOperand(i).isFrameIndex()) {
84    ++i;
85    assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
86  }
87
88  int FrameIndex = MI.getOperand(i).getIndex();
89
90  // Addressable stack objects are accessed using neg. offsets from %fp
91  MachineFunction &MF = *MI.getParent()->getParent();
92  int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
93               MI.getOperand(i+1).getImm();
94
95  // Replace frame index with a frame pointer reference.
96  if (Offset >= -4096 && Offset <= 4095) {
97    // If the offset is small enough to fit in the immediate field, directly
98    // encode it.
99    MI.getOperand(i).ChangeToRegister(SP::I6, false);
100    MI.getOperand(i+1).ChangeToImmediate(Offset);
101  } else {
102    // Otherwise, emit a G1 = SETHI %hi(offset).  FIXME: it would be better to
103    // scavenge a register here instead of reserving G1 all of the time.
104    unsigned OffHi = (unsigned)Offset >> 10U;
105    BuildMI(*MI.getParent(), II, TII.get(SP::SETHIi), SP::G1).addImm(OffHi);
106    // Emit G1 = G1 + I6
107    BuildMI(*MI.getParent(), II, TII.get(SP::ADDrr), SP::G1).addReg(SP::G1)
108      .addReg(SP::I6);
109    // Insert: G1+%lo(offset) into the user.
110    MI.getOperand(i).ChangeToRegister(SP::G1, false);
111    MI.getOperand(i+1).ChangeToImmediate(Offset & ((1 << 10)-1));
112  }
113}
114
115void SparcRegisterInfo::
116processFunctionBeforeFrameFinalized(MachineFunction &MF) const {}
117
118void SparcRegisterInfo::emitPrologue(MachineFunction &MF) const {
119  MachineBasicBlock &MBB = MF.front();
120  MachineFrameInfo *MFI = MF.getFrameInfo();
121
122  // Get the number of bytes to allocate from the FrameInfo
123  int NumBytes = (int) MFI->getStackSize();
124
125  // Emit the correct save instruction based on the number of bytes in
126  // the frame. Minimum stack frame size according to V8 ABI is:
127  //   16 words for register window spill
128  //    1 word for address of returned aggregate-value
129  // +  6 words for passing parameters on the stack
130  // ----------
131  //   23 words * 4 bytes per word = 92 bytes
132  NumBytes += 92;
133  // Round up to next doubleword boundary -- a double-word boundary
134  // is required by the ABI.
135  NumBytes = (NumBytes + 7) & ~7;
136  NumBytes = -NumBytes;
137
138  if (NumBytes >= -4096) {
139    BuildMI(MBB, MBB.begin(), TII.get(SP::SAVEri),
140            SP::O6).addReg(SP::O6).addImm(NumBytes);
141  } else {
142    MachineBasicBlock::iterator InsertPt = MBB.begin();
143    // Emit this the hard way.  This clobbers G1 which we always know is
144    // available here.
145    unsigned OffHi = (unsigned)NumBytes >> 10U;
146    BuildMI(MBB, InsertPt, TII.get(SP::SETHIi), SP::G1).addImm(OffHi);
147    // Emit G1 = G1 + I6
148    BuildMI(MBB, InsertPt, TII.get(SP::ORri), SP::G1)
149      .addReg(SP::G1).addImm(NumBytes & ((1 << 10)-1));
150    BuildMI(MBB, InsertPt, TII.get(SP::SAVErr), SP::O6)
151      .addReg(SP::O6).addReg(SP::G1);
152  }
153}
154
155void SparcRegisterInfo::emitEpilogue(MachineFunction &MF,
156                                     MachineBasicBlock &MBB) const {
157  MachineBasicBlock::iterator MBBI = prior(MBB.end());
158  assert(MBBI->getOpcode() == SP::RETL &&
159         "Can only put epilog before 'retl' instruction!");
160  BuildMI(MBB, MBBI, TII.get(SP::RESTORErr), SP::G0).addReg(SP::G0)
161    .addReg(SP::G0);
162}
163
164unsigned SparcRegisterInfo::getRARegister() const {
165  assert(0 && "What is the return address register");
166  return 0;
167}
168
169unsigned SparcRegisterInfo::getFrameRegister(MachineFunction &MF) const {
170  assert(0 && "What is the frame register");
171  return SP::G1;
172}
173
174unsigned SparcRegisterInfo::getEHExceptionRegister() const {
175  assert(0 && "What is the exception register");
176  return 0;
177}
178
179unsigned SparcRegisterInfo::getEHHandlerRegister() const {
180  assert(0 && "What is the exception handler register");
181  return 0;
182}
183
184int SparcRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
185  assert(0 && "What is the dwarf register number");
186  return -1;
187}
188
189#include "SparcGenRegisterInfo.inc"
190
191