SparcRegisterInfo.cpp revision f1d78e83356a412e525c30ac90dabf090a8cfc99
1//===- SparcRegisterInfo.cpp - SPARC Register Information -------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the SPARC implementation of the MRegisterInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "Sparc.h" 15#include "SparcRegisterInfo.h" 16#include "SparcSubtarget.h" 17#include "llvm/CodeGen/MachineInstrBuilder.h" 18#include "llvm/CodeGen/MachineFunction.h" 19#include "llvm/CodeGen/MachineFrameInfo.h" 20#include "llvm/CodeGen/MachineLocation.h" 21#include "llvm/Type.h" 22#include "llvm/ADT/STLExtras.h" 23#include <iostream> 24using namespace llvm; 25 26SparcRegisterInfo::SparcRegisterInfo(SparcSubtarget &st) 27 : SparcGenRegisterInfo(SP::ADJCALLSTACKDOWN, SP::ADJCALLSTACKUP), 28 Subtarget(st) { 29} 30 31void SparcRegisterInfo:: 32storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 33 unsigned SrcReg, int FI, 34 const TargetRegisterClass *RC) const { 35 // On the order of operands here: think "[FrameIdx + 0] = SrcReg". 36 if (RC == SP::IntRegsRegisterClass) 37 BuildMI(MBB, I, SP::STri, 3).addFrameIndex(FI).addImm(0).addReg(SrcReg); 38 else if (RC == SP::FPRegsRegisterClass) 39 BuildMI(MBB, I, SP::STFri, 3).addFrameIndex(FI).addImm(0).addReg(SrcReg); 40 else if (RC == SP::DFPRegsRegisterClass) 41 BuildMI(MBB, I, SP::STDFri, 3).addFrameIndex(FI).addImm(0).addReg(SrcReg); 42 else 43 assert(0 && "Can't store this register to stack slot"); 44} 45 46void SparcRegisterInfo:: 47loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 48 unsigned DestReg, int FI, 49 const TargetRegisterClass *RC) const { 50 if (RC == SP::IntRegsRegisterClass) 51 BuildMI(MBB, I, SP::LDri, 2, DestReg).addFrameIndex(FI).addImm(0); 52 else if (RC == SP::FPRegsRegisterClass) 53 BuildMI(MBB, I, SP::LDFri, 2, DestReg).addFrameIndex(FI).addImm (0); 54 else if (RC == SP::DFPRegsRegisterClass) 55 BuildMI(MBB, I, SP::LDDFri, 2, DestReg).addFrameIndex(FI).addImm(0); 56 else 57 assert(0 && "Can't load this register from stack slot"); 58} 59 60void SparcRegisterInfo::copyRegToReg(MachineBasicBlock &MBB, 61 MachineBasicBlock::iterator I, 62 unsigned DestReg, unsigned SrcReg, 63 const TargetRegisterClass *RC) const { 64 if (RC == SP::IntRegsRegisterClass) 65 BuildMI(MBB, I, SP::ORrr, 2, DestReg).addReg(SP::G0).addReg(SrcReg); 66 else if (RC == SP::FPRegsRegisterClass) 67 BuildMI(MBB, I, SP::FMOVS, 1, DestReg).addReg(SrcReg); 68 else if (RC == SP::DFPRegsRegisterClass) 69 BuildMI(MBB, I, Subtarget.isV9() ? SP::FMOVD : SP::FpMOVD, 70 1, DestReg).addReg(SrcReg); 71 else 72 assert (0 && "Can't copy this register"); 73} 74 75MachineInstr *SparcRegisterInfo::foldMemoryOperand(MachineInstr* MI, 76 unsigned OpNum, 77 int FI) const { 78 bool isFloat = false; 79 switch (MI->getOpcode()) { 80 case SP::ORrr: 81 if (MI->getOperand(1).isRegister() && MI->getOperand(1).getReg() == SP::G0&& 82 MI->getOperand(0).isRegister() && MI->getOperand(2).isRegister()) { 83 if (OpNum == 0) // COPY -> STORE 84 return BuildMI(SP::STri, 3).addFrameIndex(FI).addImm(0) 85 .addReg(MI->getOperand(2).getReg()); 86 else // COPY -> LOAD 87 return BuildMI(SP::LDri, 2, MI->getOperand(0).getReg()) 88 .addFrameIndex(FI).addImm(0); 89 } 90 break; 91 case SP::FMOVS: 92 isFloat = true; 93 // FALLTHROUGH 94 case SP::FMOVD: 95 if (OpNum == 0) // COPY -> STORE 96 return BuildMI(isFloat ? SP::STFri : SP::STDFri, 3) 97 .addFrameIndex(FI).addImm(0).addReg(MI->getOperand(1).getReg()); 98 else // COPY -> LOAD 99 return BuildMI(isFloat ? SP::LDFri : SP::LDDFri, 2, 100 MI->getOperand(0).getReg()).addFrameIndex(FI).addImm(0); 101 break; 102 } 103 return 0; 104} 105 106void SparcRegisterInfo:: 107eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, 108 MachineBasicBlock::iterator I) const { 109 MachineInstr &MI = *I; 110 int Size = MI.getOperand(0).getImmedValue(); 111 if (MI.getOpcode() == SP::ADJCALLSTACKDOWN) 112 Size = -Size; 113 if (Size) 114 BuildMI(MBB, I, SP::ADDri, 2, SP::O6).addReg(SP::O6).addSImm(Size); 115 MBB.erase(I); 116} 117 118void 119SparcRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const { 120 unsigned i = 0; 121 MachineInstr &MI = *II; 122 while (!MI.getOperand(i).isFrameIndex()) { 123 ++i; 124 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); 125 } 126 127 int FrameIndex = MI.getOperand(i).getFrameIndex(); 128 129 // Addressable stack objects are accessed using neg. offsets from %fp 130 MachineFunction &MF = *MI.getParent()->getParent(); 131 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) + 132 MI.getOperand(i+1).getImmedValue(); 133 134 // Replace frame index with a frame pointer reference. 135 if (Offset >= -4096 && Offset <= 4095) { 136 // If the offset is small enough to fit in the immediate field, directly 137 // encode it. 138 MI.SetMachineOperandReg(i, SP::I6); 139 MI.SetMachineOperandConst(i+1, MachineOperand::MO_SignExtendedImmed,Offset); 140 } else { 141 // Otherwise, emit a G1 = SETHI %hi(offset). FIXME: it would be better to 142 // scavenge a register here instead of reserving G1 all of the time. 143 unsigned OffHi = (unsigned)Offset >> 10U; 144 BuildMI(*MI.getParent(), II, SP::SETHIi, 1, SP::G1).addImm(OffHi); 145 // Emit G1 = G1 + I6 146 BuildMI(*MI.getParent(), II, SP::ADDrr, 2, 147 SP::G1).addReg(SP::G1).addReg(SP::I6); 148 // Insert: G1+%lo(offset) into the user. 149 MI.SetMachineOperandReg(i, SP::G1); 150 MI.SetMachineOperandConst(i+1, MachineOperand::MO_SignExtendedImmed, 151 Offset & ((1 << 10)-1)); 152 } 153} 154 155void SparcRegisterInfo:: 156processFunctionBeforeFrameFinalized(MachineFunction &MF) const {} 157 158void SparcRegisterInfo::emitPrologue(MachineFunction &MF) const { 159 MachineBasicBlock &MBB = MF.front(); 160 MachineFrameInfo *MFI = MF.getFrameInfo(); 161 162 // Get the number of bytes to allocate from the FrameInfo 163 int NumBytes = (int) MFI->getStackSize(); 164 165 // Emit the correct save instruction based on the number of bytes in 166 // the frame. Minimum stack frame size according to V8 ABI is: 167 // 16 words for register window spill 168 // 1 word for address of returned aggregate-value 169 // + 6 words for passing parameters on the stack 170 // ---------- 171 // 23 words * 4 bytes per word = 92 bytes 172 NumBytes += 92; 173 // Round up to next doubleword boundary -- a double-word boundary 174 // is required by the ABI. 175 NumBytes = (NumBytes + 7) & ~7; 176 NumBytes = -NumBytes; 177 178 if (NumBytes >= -4096) { 179 BuildMI(MBB, MBB.begin(), SP::SAVEri, 2, 180 SP::O6).addImm(NumBytes).addReg(SP::O6); 181 } else { 182 MachineBasicBlock::iterator InsertPt = MBB.begin(); 183 // Emit this the hard way. This clobbers G1 which we always know is 184 // available here. 185 unsigned OffHi = (unsigned)NumBytes >> 10U; 186 BuildMI(MBB, InsertPt, SP::SETHIi, 1, SP::G1).addImm(OffHi); 187 // Emit G1 = G1 + I6 188 BuildMI(MBB, InsertPt, SP::ORri, 2, SP::G1) 189 .addReg(SP::G1).addImm(NumBytes & ((1 << 10)-1)); 190 BuildMI(MBB, InsertPt, SP::SAVErr, 2, 191 SP::O6).addReg(SP::O6).addReg(SP::G1); 192 } 193} 194 195void SparcRegisterInfo::emitEpilogue(MachineFunction &MF, 196 MachineBasicBlock &MBB) const { 197 MachineBasicBlock::iterator MBBI = prior(MBB.end()); 198 assert(MBBI->getOpcode() == SP::RETL && 199 "Can only put epilog before 'retl' instruction!"); 200 BuildMI(MBB, MBBI, SP::RESTORErr, 2, SP::G0).addReg(SP::G0).addReg(SP::G0); 201} 202 203void SparcRegisterInfo::getLocation(MachineFunction &MF, unsigned Index, 204 MachineLocation &ML) const { 205 assert(0 && "Needs to be defined for target"); 206 MachineFrameInfo *MFI = MF.getFrameInfo(); 207 208 // FIXME - Needs to handle register variables. 209 // FIXME - Faking that llvm number is same as gcc numbering. 210 ML.set(SP::G1 - SP::G0, 211 MFI->getObjectOffset(Index) + MFI->getStackSize()); 212} 213 214#include "SparcGenRegisterInfo.inc" 215 216