SparcRegisterInfo.td revision 0e362770d03a10ed49f75b75aa5673bc9026e3da 
1//===- SparcV8Reg.td - Describe the SparcV8 Register File -------*- C++ -*-===//
2// 
3//                     The LLVM Compiler Infrastructure
4//
5// This file was developed by the LLVM research group and is distributed under
6// the University of Illinois Open Source License. See LICENSE.TXT for details.
7// 
8//===----------------------------------------------------------------------===//
9//
10//  Declarations that describe the SparcV8 register file 
11//
12//===----------------------------------------------------------------------===//
13
14// Registers are identified with 5-bit ID numbers.
15// Ri - 32-bit integer registers
16class Ri<bits<5> num> : Register {
17  field bits<5> Num = num;
18}
19// Rf - 32-bit floating-point registers
20class Rf<bits<5> num> : Register {
21  field bits<5> Num = num;
22}
23// Rd - Slots in the FP register file for 64-bit floating-point values.
24class Rd<bits<5> num, string realName> : Register {
25  field bits<5> Num = num;
26  let Name = realName;
27}
28// Rs - Special "ancillary state registers" registers, like the Y, ASR, PSR,
29// WIM, TBR, etc registers
30class Rs<bits<5> num> : Register {
31  field bits<5> Num = num;
32}
33
34let Namespace = "V8" in {
35  def G0 : Ri< 0>;    def G1 : Ri< 1>;    def G2 : Ri< 2>;    def G3 : Ri< 3>;
36  def G4 : Ri< 4>;    def G5 : Ri< 5>;    def G6 : Ri< 6>;    def G7 : Ri< 7>;
37  def O0 : Ri< 8>;    def O1 : Ri< 9>;    def O2 : Ri<10>;    def O3 : Ri<11>;
38  def O4 : Ri<12>;    def O5 : Ri<13>;    def O6 : Ri<14>;    def O7 : Ri<15>;
39  def L0 : Ri<16>;    def L1 : Ri<17>;    def L2 : Ri<18>;    def L3 : Ri<19>;
40  def L4 : Ri<20>;    def L5 : Ri<21>;    def L6 : Ri<22>;    def L7 : Ri<23>;
41  def I0 : Ri<24>;    def I1 : Ri<25>;    def I2 : Ri<26>;    def I3 : Ri<27>;
42  def I4 : Ri<28>;    def I5 : Ri<29>;    def I6 : Ri<30>;    def I7 : Ri<31>;
43
44  // Standard register aliases.
45  def SP : Ri<14>;    def FP : Ri<30>;
46
47  // Floating-point registers:
48  def F0  : Rf< 0>; def F1  : Rf< 1>; def F2  : Rf< 2>; def F3  : Rf< 3>;
49  def F4  : Rf< 4>; def F5  : Rf< 5>; def F6  : Rf< 6>; def F7  : Rf< 7>;
50  def F8  : Rf< 8>; def F9  : Rf< 9>; def F10 : Rf<10>; def F11 : Rf<11>;
51  def F12 : Rf<12>; def F13 : Rf<13>; def F14 : Rf<14>; def F15 : Rf<15>;
52  def F16 : Rf<16>; def F17 : Rf<17>; def F18 : Rf<18>; def F19 : Rf<19>;
53  def F20 : Rf<20>; def F21 : Rf<21>; def F22 : Rf<22>; def F23 : Rf<23>;
54  def F24 : Rf<24>; def F25 : Rf<25>; def F26 : Rf<26>; def F27 : Rf<27>;
55  def F28 : Rf<28>; def F29 : Rf<29>; def F30 : Rf<30>; def F31 : Rf<31>;
56
57  // Aliases of the F* registers used to hold 64-bit fp values (doubles).
58  def D0  : Rd< 0,  "F0">; def D1  : Rd< 2,  "F2">; def D2  : Rd< 4,  "F4">;
59  def D3  : Rd< 6,  "F6">; def D4  : Rd< 8,  "F8">; def D5  : Rd<10, "F10">;
60  def D6  : Rd<12, "F12">; def D7  : Rd<14, "F14">; def D8  : Rd<16, "F16">;
61  def D9  : Rd<18, "F18">; def D10 : Rd<20, "F20">; def D11 : Rd<22, "F22">;
62  def D12 : Rd<24, "F24">; def D13 : Rd<26, "F26">; def D14 : Rd<28, "F28">;
63  def D15 : Rd<30, "F30">;
64
65  // The Y register.
66  def Y   : Rs<0>;
67}
68
69// Register classes.
70//
71// FIXME: the register order should be defined in terms of the preferred
72// allocation order...
73//
74def IntRegs : RegisterClass<i32, 64, [L0, L1, L2, L3, L4, L5, L6, L7,
75                                     I0, I1, I2, I3, I4, I5,
76                                     G1, G2, G3, G4, G5, G6, G7,
77                                     O0, O1, O2, O3, O4, O5, O7,
78                                     // Non-allocatable regs
79                                     O6, I6, I7, G0]> {
80  let Methods = [{
81    iterator allocation_order_end(MachineFunction &MF) const {
82      return end()-4;  // Don't allocate special registers
83    }
84  }];
85}
86
87def FPRegs : RegisterClass<f32, 32, [F0, F1, F2, F3, F4, F5, F6, F7, F8,
88  F9, F10, F11, F12, F13, F14, F15, F16, F17, F18, F19, F20, F21, F22,
89  F23, F24, F25, F26, F27, F28, F29, F30, F31]>;
90
91def DFPRegs : RegisterClass<f64, 64, [D0, D1, D2, D3, D4, D5, D6, D7,
92  D8, D9, D10, D11, D12, D13, D14, D15]>;
93
94// Tell the register file generator that the double-fp pseudo-registers
95// alias the registers used for single-fp values.
96def : RegisterAliases<D0, [F0, F1]>;
97def : RegisterAliases<D1, [F2, F3]>;
98def : RegisterAliases<D2, [F4, F5]>;
99def : RegisterAliases<D3, [F6, F7]>;
100def : RegisterAliases<D4, [F8, F9]>;
101def : RegisterAliases<D5, [F10, F11]>;
102def : RegisterAliases<D6, [F12, F13]>;
103def : RegisterAliases<D7, [F14, F15]>;
104def : RegisterAliases<D8, [F16, F17]>;
105def : RegisterAliases<D9, [F18, F19]>;
106def : RegisterAliases<D10, [F20, F21]>;
107def : RegisterAliases<D11, [F22, F23]>;
108def : RegisterAliases<D12, [F24, F25]>;
109def : RegisterAliases<D13, [F26, F27]>;
110def : RegisterAliases<D14, [F28, F29]>;
111def : RegisterAliases<D15, [F30, F31]>;
112