SparcRegisterInfo.td revision 36b56886974eae4f9c5ebc96befd3e7bfe5de338
1//===-- SparcRegisterInfo.td - Sparc Register defs ---------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10//===----------------------------------------------------------------------===// 11// Declarations that describe the Sparc register file 12//===----------------------------------------------------------------------===// 13 14class SparcReg<bits<16> Enc, string n> : Register<n> { 15 let HWEncoding = Enc; 16 let Namespace = "SP"; 17} 18 19class SparcCtrlReg<bits<16> Enc, string n>: Register<n> { 20 let HWEncoding = Enc; 21 let Namespace = "SP"; 22} 23 24let Namespace = "SP" in { 25def sub_even : SubRegIndex<32>; 26def sub_odd : SubRegIndex<32, 32>; 27def sub_even64 : SubRegIndex<64>; 28def sub_odd64 : SubRegIndex<64, 64>; 29} 30 31// Registers are identified with 5-bit ID numbers. 32// Ri - 32-bit integer registers 33class Ri<bits<16> Enc, string n> : SparcReg<Enc, n>; 34 35// Rf - 32-bit floating-point registers 36class Rf<bits<16> Enc, string n> : SparcReg<Enc, n>; 37 38// Rd - Slots in the FP register file for 64-bit floating-point values. 39class Rd<bits<16> Enc, string n, list<Register> subregs> : SparcReg<Enc, n> { 40 let SubRegs = subregs; 41 let SubRegIndices = [sub_even, sub_odd]; 42 let CoveredBySubRegs = 1; 43} 44 45// Rq - Slots in the FP register file for 128-bit floating-point values. 46class Rq<bits<16> Enc, string n, list<Register> subregs> : SparcReg<Enc, n> { 47 let SubRegs = subregs; 48 let SubRegIndices = [sub_even64, sub_odd64]; 49 let CoveredBySubRegs = 1; 50} 51 52// Control Registers 53def ICC : SparcCtrlReg<0, "ICC">; // This represents icc and xcc in 64-bit code. 54foreach I = 0-3 in 55 def FCC#I : SparcCtrlReg<I, "FCC"#I>; 56 57// Y register 58def Y : SparcCtrlReg<0, "Y">, DwarfRegNum<[64]>; 59 60// Integer registers 61def G0 : Ri< 0, "G0">, DwarfRegNum<[0]>; 62def G1 : Ri< 1, "G1">, DwarfRegNum<[1]>; 63def G2 : Ri< 2, "G2">, DwarfRegNum<[2]>; 64def G3 : Ri< 3, "G3">, DwarfRegNum<[3]>; 65def G4 : Ri< 4, "G4">, DwarfRegNum<[4]>; 66def G5 : Ri< 5, "G5">, DwarfRegNum<[5]>; 67def G6 : Ri< 6, "G6">, DwarfRegNum<[6]>; 68def G7 : Ri< 7, "G7">, DwarfRegNum<[7]>; 69def O0 : Ri< 8, "O0">, DwarfRegNum<[8]>; 70def O1 : Ri< 9, "O1">, DwarfRegNum<[9]>; 71def O2 : Ri<10, "O2">, DwarfRegNum<[10]>; 72def O3 : Ri<11, "O3">, DwarfRegNum<[11]>; 73def O4 : Ri<12, "O4">, DwarfRegNum<[12]>; 74def O5 : Ri<13, "O5">, DwarfRegNum<[13]>; 75def O6 : Ri<14, "SP">, DwarfRegNum<[14]>; 76def O7 : Ri<15, "O7">, DwarfRegNum<[15]>; 77def L0 : Ri<16, "L0">, DwarfRegNum<[16]>; 78def L1 : Ri<17, "L1">, DwarfRegNum<[17]>; 79def L2 : Ri<18, "L2">, DwarfRegNum<[18]>; 80def L3 : Ri<19, "L3">, DwarfRegNum<[19]>; 81def L4 : Ri<20, "L4">, DwarfRegNum<[20]>; 82def L5 : Ri<21, "L5">, DwarfRegNum<[21]>; 83def L6 : Ri<22, "L6">, DwarfRegNum<[22]>; 84def L7 : Ri<23, "L7">, DwarfRegNum<[23]>; 85def I0 : Ri<24, "I0">, DwarfRegNum<[24]>; 86def I1 : Ri<25, "I1">, DwarfRegNum<[25]>; 87def I2 : Ri<26, "I2">, DwarfRegNum<[26]>; 88def I3 : Ri<27, "I3">, DwarfRegNum<[27]>; 89def I4 : Ri<28, "I4">, DwarfRegNum<[28]>; 90def I5 : Ri<29, "I5">, DwarfRegNum<[29]>; 91def I6 : Ri<30, "FP">, DwarfRegNum<[30]>; 92def I7 : Ri<31, "I7">, DwarfRegNum<[31]>; 93 94// Floating-point registers 95def F0 : Rf< 0, "F0">, DwarfRegNum<[32]>; 96def F1 : Rf< 1, "F1">, DwarfRegNum<[33]>; 97def F2 : Rf< 2, "F2">, DwarfRegNum<[34]>; 98def F3 : Rf< 3, "F3">, DwarfRegNum<[35]>; 99def F4 : Rf< 4, "F4">, DwarfRegNum<[36]>; 100def F5 : Rf< 5, "F5">, DwarfRegNum<[37]>; 101def F6 : Rf< 6, "F6">, DwarfRegNum<[38]>; 102def F7 : Rf< 7, "F7">, DwarfRegNum<[39]>; 103def F8 : Rf< 8, "F8">, DwarfRegNum<[40]>; 104def F9 : Rf< 9, "F9">, DwarfRegNum<[41]>; 105def F10 : Rf<10, "F10">, DwarfRegNum<[42]>; 106def F11 : Rf<11, "F11">, DwarfRegNum<[43]>; 107def F12 : Rf<12, "F12">, DwarfRegNum<[44]>; 108def F13 : Rf<13, "F13">, DwarfRegNum<[45]>; 109def F14 : Rf<14, "F14">, DwarfRegNum<[46]>; 110def F15 : Rf<15, "F15">, DwarfRegNum<[47]>; 111def F16 : Rf<16, "F16">, DwarfRegNum<[48]>; 112def F17 : Rf<17, "F17">, DwarfRegNum<[49]>; 113def F18 : Rf<18, "F18">, DwarfRegNum<[50]>; 114def F19 : Rf<19, "F19">, DwarfRegNum<[51]>; 115def F20 : Rf<20, "F20">, DwarfRegNum<[52]>; 116def F21 : Rf<21, "F21">, DwarfRegNum<[53]>; 117def F22 : Rf<22, "F22">, DwarfRegNum<[54]>; 118def F23 : Rf<23, "F23">, DwarfRegNum<[55]>; 119def F24 : Rf<24, "F24">, DwarfRegNum<[56]>; 120def F25 : Rf<25, "F25">, DwarfRegNum<[57]>; 121def F26 : Rf<26, "F26">, DwarfRegNum<[58]>; 122def F27 : Rf<27, "F27">, DwarfRegNum<[59]>; 123def F28 : Rf<28, "F28">, DwarfRegNum<[60]>; 124def F29 : Rf<29, "F29">, DwarfRegNum<[61]>; 125def F30 : Rf<30, "F30">, DwarfRegNum<[62]>; 126def F31 : Rf<31, "F31">, DwarfRegNum<[63]>; 127 128// Aliases of the F* registers used to hold 64-bit fp values (doubles) 129def D0 : Rd< 0, "F0", [F0, F1]>, DwarfRegNum<[72]>; 130def D1 : Rd< 2, "F2", [F2, F3]>, DwarfRegNum<[73]>; 131def D2 : Rd< 4, "F4", [F4, F5]>, DwarfRegNum<[74]>; 132def D3 : Rd< 6, "F6", [F6, F7]>, DwarfRegNum<[75]>; 133def D4 : Rd< 8, "F8", [F8, F9]>, DwarfRegNum<[76]>; 134def D5 : Rd<10, "F10", [F10, F11]>, DwarfRegNum<[77]>; 135def D6 : Rd<12, "F12", [F12, F13]>, DwarfRegNum<[78]>; 136def D7 : Rd<14, "F14", [F14, F15]>, DwarfRegNum<[79]>; 137def D8 : Rd<16, "F16", [F16, F17]>, DwarfRegNum<[80]>; 138def D9 : Rd<18, "F18", [F18, F19]>, DwarfRegNum<[81]>; 139def D10 : Rd<20, "F20", [F20, F21]>, DwarfRegNum<[82]>; 140def D11 : Rd<22, "F22", [F22, F23]>, DwarfRegNum<[83]>; 141def D12 : Rd<24, "F24", [F24, F25]>, DwarfRegNum<[84]>; 142def D13 : Rd<26, "F26", [F26, F27]>, DwarfRegNum<[85]>; 143def D14 : Rd<28, "F28", [F28, F29]>, DwarfRegNum<[86]>; 144def D15 : Rd<30, "F30", [F30, F31]>, DwarfRegNum<[87]>; 145 146// Unaliased double precision floating point registers. 147// FIXME: Define DwarfRegNum for these registers. 148def D16 : SparcReg< 1, "F32">; 149def D17 : SparcReg< 3, "F34">; 150def D18 : SparcReg< 5, "F36">; 151def D19 : SparcReg< 7, "F38">; 152def D20 : SparcReg< 9, "F40">; 153def D21 : SparcReg<11, "F42">; 154def D22 : SparcReg<13, "F44">; 155def D23 : SparcReg<15, "F46">; 156def D24 : SparcReg<17, "F48">; 157def D25 : SparcReg<19, "F50">; 158def D26 : SparcReg<21, "F52">; 159def D27 : SparcReg<23, "F54">; 160def D28 : SparcReg<25, "F56">; 161def D29 : SparcReg<27, "F58">; 162def D30 : SparcReg<29, "F60">; 163def D31 : SparcReg<31, "F62">; 164 165// Aliases of the F* registers used to hold 128-bit for values (long doubles). 166def Q0 : Rq< 0, "F0", [D0, D1]>; 167def Q1 : Rq< 4, "F4", [D2, D3]>; 168def Q2 : Rq< 8, "F8", [D4, D5]>; 169def Q3 : Rq<12, "F12", [D6, D7]>; 170def Q4 : Rq<16, "F16", [D8, D9]>; 171def Q5 : Rq<20, "F20", [D10, D11]>; 172def Q6 : Rq<24, "F24", [D12, D13]>; 173def Q7 : Rq<28, "F28", [D14, D15]>; 174def Q8 : Rq< 1, "F32", [D16, D17]>; 175def Q9 : Rq< 5, "F36", [D18, D19]>; 176def Q10 : Rq< 9, "F40", [D20, D21]>; 177def Q11 : Rq<13, "F44", [D22, D23]>; 178def Q12 : Rq<17, "F48", [D24, D25]>; 179def Q13 : Rq<21, "F52", [D26, D27]>; 180def Q14 : Rq<25, "F56", [D28, D29]>; 181def Q15 : Rq<29, "F60", [D30, D31]>; 182 183// Register classes. 184// 185// FIXME: the register order should be defined in terms of the preferred 186// allocation order... 187// 188// This register class should not be used to hold i64 values, use the I64Regs 189// register class for that. The i64 type is included here to allow i64 patterns 190// using the integer instructions. 191def IntRegs : RegisterClass<"SP", [i32, i64], 32, 192 (add (sequence "I%u", 0, 7), 193 (sequence "G%u", 0, 7), 194 (sequence "L%u", 0, 7), 195 (sequence "O%u", 0, 7))>; 196 197// Register class for 64-bit mode, with a 64-bit spill slot size. 198// These are the same as the 32-bit registers, so TableGen will consider this 199// to be a sub-class of IntRegs. That works out because requiring a 64-bit 200// spill slot is a stricter constraint than only requiring a 32-bit spill slot. 201def I64Regs : RegisterClass<"SP", [i64], 64, (add IntRegs)>; 202 203// Floating point register classes. 204def FPRegs : RegisterClass<"SP", [f32], 32, (sequence "F%u", 0, 31)>; 205 206def DFPRegs : RegisterClass<"SP", [f64], 64, (sequence "D%u", 0, 31)>; 207 208def QFPRegs : RegisterClass<"SP", [f128], 128, (sequence "Q%u", 0, 15)>; 209 210// Floating point control register classes. 211def FCCRegs : RegisterClass<"SP", [i1], 1, (sequence "FCC%u", 0, 3)>; 212