SparcRegisterInfo.td revision 7c90f73a1b06040d971a3dd95a491031ae6238d5
1//===- SparcRegisterInfo.td - Sparc Register defs ----------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10//===----------------------------------------------------------------------===// 11// Declarations that describe the Sparc register file 12//===----------------------------------------------------------------------===// 13 14class SparcReg<string n> : Register<n> { 15 field bits<5> Num; 16 let Namespace = "SP"; 17} 18 19// Registers are identified with 5-bit ID numbers. 20// Ri - 32-bit integer registers 21class Ri<bits<5> num, string n> : SparcReg<n> { 22 let Num = num; 23} 24// Rf - 32-bit floating-point registers 25class Rf<bits<5> num, string n> : SparcReg<n> { 26 let Num = num; 27} 28// Rd - Slots in the FP register file for 64-bit floating-point values. 29class Rd<bits<5> num, string n, list<Register> aliases> : SparcReg<n> { 30 let Num = num; 31 let Aliases = aliases; 32} 33 34// Integer registers 35def G0 : Ri< 0, "G0">; def G1 : Ri< 1, "G1">; def G2 : Ri< 2, "G2">; 36def G3 : Ri< 3, "G3">; def G4 : Ri< 4, "G4">; def G5 : Ri< 5, "G5">; 37def G6 : Ri< 6, "G6">; def G7 : Ri< 7, "G7">; 38def O0 : Ri< 8, "O0">; def O1 : Ri< 9, "O1">; def O2 : Ri<10, "O2">; 39def O3 : Ri<11, "O3">; def O4 : Ri<12, "O4">; def O5 : Ri<13, "O5">; 40def O6 : Ri<14, "O6">; def O7 : Ri<15, "O7">; 41def L0 : Ri<16, "L0">; def L1 : Ri<17, "L1">; def L2 : Ri<18, "L2">; 42def L3 : Ri<19, "L3">; def L4 : Ri<20, "L4">; def L5 : Ri<21, "L5">; 43def L6 : Ri<22, "L6">; def L7 : Ri<23, "L7">; 44def I0 : Ri<24, "I0">; def I1 : Ri<25, "I1">; def I2 : Ri<26, "I2">; 45def I3 : Ri<27, "I3">; def I4 : Ri<28, "I4">; def I5 : Ri<29, "I5">; 46def I6 : Ri<30, "I6">; def I7 : Ri<31, "I7">; 47 48// Floating-point registers 49def F0 : Rf< 0, "F0">; def F1 : Rf< 1, "F1">; def F2 : Rf< 2, "F2">; 50def F3 : Rf< 3, "F3">; def F4 : Rf< 4, "F4">; def F5 : Rf< 5, "F5">; 51def F6 : Rf< 6, "F6">; def F7 : Rf< 7, "F7">; def F8 : Rf< 8, "F8">; 52def F9 : Rf< 9, "F9">; def F10 : Rf<10, "F10">; def F11 : Rf<11, "F11">; 53def F12 : Rf<12, "F12">; def F13 : Rf<13, "F13">; def F14 : Rf<14, "F14">; 54def F15 : Rf<15, "F15">; def F16 : Rf<16, "F16">; def F17 : Rf<17, "F17">; 55def F18 : Rf<18, "F18">; def F19 : Rf<19, "F19">; def F20 : Rf<20, "F20">; 56def F21 : Rf<21, "F21">; def F22 : Rf<22, "F22">; def F23 : Rf<23, "F23">; 57def F24 : Rf<24, "F24">; def F25 : Rf<25, "F25">; def F26 : Rf<26, "F26">; 58def F27 : Rf<27, "F27">; def F28 : Rf<28, "F28">; def F29 : Rf<29, "F29">; 59def F30 : Rf<30, "F30">; def F31 : Rf<31, "F31">; 60 61// Aliases of the F* registers used to hold 64-bit fp values (doubles) 62def D0 : Rd< 0, "F0", [F0, F1]>; def D1 : Rd< 2, "F2", [F2, F3]>; 63def D2 : Rd< 4, "F4", [F4, F5]>; def D3 : Rd< 6, "F6", [F6, F7]>; 64def D4 : Rd< 8, "F8", [F8, F9]>; def D5 : Rd<10, "F10", [F10, F11]>; 65def D6 : Rd<12, "F12", [F12, F13]>; def D7 : Rd<14, "F14", [F14, F15]>; 66def D8 : Rd<16, "F16", [F16, F17]>; def D9 : Rd<18, "F18", [F18, F19]>; 67def D10 : Rd<20, "F20", [F20, F21]>; def D11 : Rd<22, "F22", [F22, F23]>; 68def D12 : Rd<24, "F24", [F24, F25]>; def D13 : Rd<26, "F26", [F26, F27]>; 69def D14 : Rd<28, "F28", [F28, F29]>; def D15 : Rd<30, "F30", [F30, F31]>; 70 71/// Integer and FP Condition codes. 72let Namespace = "SP" in { 73 def ICC : Register<"ICC">; 74 def FCC : Register<"FCC">; 75} 76def FLAGS_REGS : RegisterClass<"SP", [FlagVT], 32, [ICC, FCC]> { 77 let Size = 32; 78} 79 80// Register classes. 81// 82// FIXME: the register order should be defined in terms of the preferred 83// allocation order... 84// 85def IntRegs : RegisterClass<"SP", [i32], 32, [L0, L1, L2, L3, L4, L5, L6, L7, 86 I0, I1, I2, I3, I4, I5, 87 O0, O1, O2, O3, O4, O5, O7, 88 89 // FIXME: G1 reserved for now for large imm generation by frame code. 90 G1, 91 // Non-allocatable regs: 92 G2, G3, G4, // FIXME: OK for use only in 93 // applications, not libraries. 94 O6, // stack ptr 95 I6, // frame ptr 96 I7, // return address 97 G0, // constant zero 98 G5, G6, G7 // reserved for kernel 99 ]> { 100 let MethodProtos = [{ 101 iterator allocation_order_end(MachineFunction &MF) const; 102 }]; 103 let MethodBodies = [{ 104 IntRegsClass::iterator 105 IntRegsClass::allocation_order_end(MachineFunction &MF) const { 106 // FIXME: These special regs should be taken out of the regclass! 107 return end()-10 // Don't allocate special registers 108 -1; // FIXME: G1 reserved for large imm generation by frame code. 109 } 110 }]; 111} 112 113def FPRegs : RegisterClass<"SP", [f32], 32, [F0, F1, F2, F3, F4, F5, F6, F7, F8, 114 F9, F10, F11, F12, F13, F14, F15, F16, F17, F18, F19, F20, F21, F22, 115 F23, F24, F25, F26, F27, F28, F29, F30, F31]>; 116 117def DFPRegs : RegisterClass<"SP", [f64], 64, [D0, D1, D2, D3, D4, D5, D6, D7, 118 D8, D9, D10, D11, D12, D13, D14, D15]>; 119