SparcRegisterInfo.td revision c95759c2f53fbc90334952491ec9c8739e565218
1//===- SparcV8RegisterInfo.td - SparcV8 Register defs ------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10//===----------------------------------------------------------------------===// 11// Declarations that describe the SparcV8 register file 12//===----------------------------------------------------------------------===// 13 14class SparcReg<string n> : Register<n> { 15 field bits<5> Num; 16 let Namespace = "V8"; 17} 18 19include "../SparcRegisterInfo.td" 20 21// Register classes. 22// 23// FIXME: the register order should be defined in terms of the preferred 24// allocation order... 25// 26def IntRegs : RegisterClass<i64, 64, [L0, L1, L2, L3, L4, L5, L6, L7, 27 I0, I1, I2, I3, I4, I5, 28 G1, G2, G3, G4, G5, G6, G7, 29 O0, O1, O2, O3, O4, O5, O7, 30 // Non-allocatable regs 31 O6, I6, I7, G0]> { 32 let Methods = [{ 33 iterator allocation_order_end(MachineFunction &MF) const { 34 return end()-4; // Don't allocate special registers 35 } 36 }]; 37} 38 39def FPRegs : RegisterClass<f32, 32, [F0, F1, F2, F3, F4, F5, F6, F7, F8, 40 F9, F10, F11, F12, F13, F14, F15, F16, F17, F18, F19, F20, F21, F22, 41 F23, F24, F25, F26, F27, F28, F29, F30, F31]>; 42 43def DFPRegs : RegisterClass<f64, 64, [D0, D1, D2, D3, D4, D5, D6, D7, 44 D8, D9, D10, D11, D12, D13, D14, D15]>; 45