1//===-- SparcTargetMachine.cpp - Define TargetMachine for Sparc -----------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10//
11//===----------------------------------------------------------------------===//
12
13#include "SparcTargetMachine.h"
14#include "Sparc.h"
15#include "llvm/CodeGen/Passes.h"
16#include "llvm/PassManager.h"
17#include "llvm/Support/TargetRegistry.h"
18using namespace llvm;
19
20extern "C" void LLVMInitializeSparcTarget() {
21  // Register the target.
22  RegisterTargetMachine<SparcV8TargetMachine> X(TheSparcTarget);
23  RegisterTargetMachine<SparcV9TargetMachine> Y(TheSparcV9Target);
24}
25
26/// SparcTargetMachine ctor - Create an ILP32 architecture model
27///
28SparcTargetMachine::SparcTargetMachine(const Target &T, StringRef TT,
29                                       StringRef CPU, StringRef FS,
30                                       const TargetOptions &Options,
31                                       Reloc::Model RM, CodeModel::Model CM,
32                                       CodeGenOpt::Level OL,
33                                       bool is64bit)
34  : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
35    Subtarget(TT, CPU, FS, *this, is64bit) {
36  initAsmInfo();
37}
38
39namespace {
40/// Sparc Code Generator Pass Configuration Options.
41class SparcPassConfig : public TargetPassConfig {
42public:
43  SparcPassConfig(SparcTargetMachine *TM, PassManagerBase &PM)
44    : TargetPassConfig(TM, PM) {}
45
46  SparcTargetMachine &getSparcTargetMachine() const {
47    return getTM<SparcTargetMachine>();
48  }
49
50  bool addInstSelector() override;
51  bool addPreEmitPass() override;
52};
53} // namespace
54
55TargetPassConfig *SparcTargetMachine::createPassConfig(PassManagerBase &PM) {
56  return new SparcPassConfig(this, PM);
57}
58
59bool SparcPassConfig::addInstSelector() {
60  addPass(createSparcISelDag(getSparcTargetMachine()));
61  return false;
62}
63
64bool SparcTargetMachine::addCodeEmitter(PassManagerBase &PM,
65                                        JITCodeEmitter &JCE) {
66  // Machine code emitter pass for Sparc.
67  PM.add(createSparcJITCodeEmitterPass(*this, JCE));
68  return false;
69}
70
71/// addPreEmitPass - This pass may be implemented by targets that want to run
72/// passes immediately before machine code is emitted.  This should return
73/// true if -print-machineinstrs should print out the code after the passes.
74bool SparcPassConfig::addPreEmitPass(){
75  addPass(createSparcDelaySlotFillerPass(getSparcTargetMachine()));
76  return true;
77}
78
79void SparcV8TargetMachine::anchor() { }
80
81SparcV8TargetMachine::SparcV8TargetMachine(const Target &T,
82                                           StringRef TT, StringRef CPU,
83                                           StringRef FS,
84                                           const TargetOptions &Options,
85                                           Reloc::Model RM,
86                                           CodeModel::Model CM,
87                                           CodeGenOpt::Level OL)
88  : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {
89}
90
91void SparcV9TargetMachine::anchor() { }
92
93SparcV9TargetMachine::SparcV9TargetMachine(const Target &T,
94                                           StringRef TT,  StringRef CPU,
95                                           StringRef FS,
96                                           const TargetOptions &Options,
97                                           Reloc::Model RM,
98                                           CodeModel::Model CM,
99                                           CodeGenOpt::Level OL)
100  : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {
101}
102