SparcTargetMachine.cpp revision 34ad6db8b958fdc0d38e122edf753b5326e69b03
1//===-- SparcTargetMachine.cpp - Define TargetMachine for Sparc -----------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// 11//===----------------------------------------------------------------------===// 12 13#include "Sparc.h" 14#include "SparcTargetMachine.h" 15#include "llvm/PassManager.h" 16#include "llvm/Target/TargetRegistry.h" 17using namespace llvm; 18 19extern "C" void LLVMInitializeSparcTarget() { 20 // Register the target. 21 RegisterTargetMachine<SparcV8TargetMachine> X(TheSparcTarget); 22 RegisterTargetMachine<SparcV9TargetMachine> Y(TheSparcV9Target); 23} 24 25/// SparcTargetMachine ctor - Create an ILP32 architecture model 26/// 27SparcTargetMachine::SparcTargetMachine(const Target &T, StringRef TT, 28 StringRef CPU, StringRef FS, 29 Reloc::Model RM, CodeModel::Model CM, 30 bool is64bit) 31 : LLVMTargetMachine(T, TT, CPU, FS, RM, CM), 32 Subtarget(TT, CPU, FS, is64bit), 33 DataLayout(Subtarget.getDataLayout()), 34 TLInfo(*this), TSInfo(*this), InstrInfo(Subtarget), 35 FrameLowering(Subtarget) { 36} 37 38bool SparcTargetMachine::addInstSelector(PassManagerBase &PM, 39 CodeGenOpt::Level OptLevel) { 40 PM.add(createSparcISelDag(*this)); 41 return false; 42} 43 44/// addPreEmitPass - This pass may be implemented by targets that want to run 45/// passes immediately before machine code is emitted. This should return 46/// true if -print-machineinstrs should print out the code after the passes. 47bool SparcTargetMachine::addPreEmitPass(PassManagerBase &PM, 48 CodeGenOpt::Level OptLevel){ 49 PM.add(createSparcFPMoverPass(*this)); 50 PM.add(createSparcDelaySlotFillerPass(*this)); 51 return true; 52} 53 54SparcV8TargetMachine::SparcV8TargetMachine(const Target &T, 55 StringRef TT, StringRef CPU, 56 StringRef FS, Reloc::Model RM, 57 CodeModel::Model CM) 58 : SparcTargetMachine(T, TT, CPU, FS, RM, CM, false) { 59} 60 61SparcV9TargetMachine::SparcV9TargetMachine(const Target &T, 62 StringRef TT, StringRef CPU, 63 StringRef FS, Reloc::Model RM, 64 CodeModel::Model CM) 65 : SparcTargetMachine(T, TT, CPU, FS, RM, CM, true) { 66} 67