SparcTargetMachine.cpp revision 36b56886974eae4f9c5ebc96befd3e7bfe5de338 
1//===-- SparcTargetMachine.cpp - Define TargetMachine for Sparc -----------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10//
11//===----------------------------------------------------------------------===//
12
13#include "SparcTargetMachine.h"
14#include "Sparc.h"
15#include "llvm/CodeGen/Passes.h"
16#include "llvm/PassManager.h"
17#include "llvm/Support/TargetRegistry.h"
18using namespace llvm;
19
20extern "C" void LLVMInitializeSparcTarget() {
21  // Register the target.
22  RegisterTargetMachine<SparcV8TargetMachine> X(TheSparcTarget);
23  RegisterTargetMachine<SparcV9TargetMachine> Y(TheSparcV9Target);
24}
25
26static std::string computeDataLayout(const SparcSubtarget &ST) {
27  // Sparc is big endian.
28  std::string Ret = "E-m:e";
29
30  // Some ABIs have 32bit pointers.
31  if (!ST.is64Bit())
32    Ret += "-p:32:32";
33
34  // Alignments for 64 bit integers.
35  Ret += "-i64:64";
36
37  // On SparcV9 128 floats are aligned to 128 bits, on others only to 64.
38  // On SparcV9 registers can hold 64 or 32 bits, on others only 32.
39  if (ST.is64Bit())
40    Ret += "-n32:64";
41  else
42    Ret += "-f128:64-n32";
43
44  if (ST.is64Bit())
45    Ret += "-S128";
46  else
47    Ret += "-S64";
48
49  return Ret;
50}
51
52/// SparcTargetMachine ctor - Create an ILP32 architecture model
53///
54SparcTargetMachine::SparcTargetMachine(const Target &T, StringRef TT,
55                                       StringRef CPU, StringRef FS,
56                                       const TargetOptions &Options,
57                                       Reloc::Model RM, CodeModel::Model CM,
58                                       CodeGenOpt::Level OL,
59                                       bool is64bit)
60  : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
61    Subtarget(TT, CPU, FS, is64bit),
62    DL(computeDataLayout(Subtarget)),
63    InstrInfo(Subtarget),
64    TLInfo(*this), TSInfo(*this),
65    FrameLowering(Subtarget) {
66  initAsmInfo();
67}
68
69namespace {
70/// Sparc Code Generator Pass Configuration Options.
71class SparcPassConfig : public TargetPassConfig {
72public:
73  SparcPassConfig(SparcTargetMachine *TM, PassManagerBase &PM)
74    : TargetPassConfig(TM, PM) {}
75
76  SparcTargetMachine &getSparcTargetMachine() const {
77    return getTM<SparcTargetMachine>();
78  }
79
80  virtual bool addInstSelector();
81  virtual bool addPreEmitPass();
82};
83} // namespace
84
85TargetPassConfig *SparcTargetMachine::createPassConfig(PassManagerBase &PM) {
86  return new SparcPassConfig(this, PM);
87}
88
89bool SparcPassConfig::addInstSelector() {
90  addPass(createSparcISelDag(getSparcTargetMachine()));
91  return false;
92}
93
94bool SparcTargetMachine::addCodeEmitter(PassManagerBase &PM,
95                                        JITCodeEmitter &JCE) {
96  // Machine code emitter pass for Sparc.
97  PM.add(createSparcJITCodeEmitterPass(*this, JCE));
98  return false;
99}
100
101/// addPreEmitPass - This pass may be implemented by targets that want to run
102/// passes immediately before machine code is emitted.  This should return
103/// true if -print-machineinstrs should print out the code after the passes.
104bool SparcPassConfig::addPreEmitPass(){
105  addPass(createSparcDelaySlotFillerPass(getSparcTargetMachine()));
106  return true;
107}
108
109void SparcV8TargetMachine::anchor() { }
110
111SparcV8TargetMachine::SparcV8TargetMachine(const Target &T,
112                                           StringRef TT, StringRef CPU,
113                                           StringRef FS,
114                                           const TargetOptions &Options,
115                                           Reloc::Model RM,
116                                           CodeModel::Model CM,
117                                           CodeGenOpt::Level OL)
118  : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {
119}
120
121void SparcV9TargetMachine::anchor() { }
122
123SparcV9TargetMachine::SparcV9TargetMachine(const Target &T,
124                                           StringRef TT,  StringRef CPU,
125                                           StringRef FS,
126                                           const TargetOptions &Options,
127                                           Reloc::Model RM,
128                                           CodeModel::Model CM,
129                                           CodeGenOpt::Level OL)
130  : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {
131}
132