SparcTargetMachine.cpp revision 3ea78c4276dfbf5a078292ad8fd8dc952c4ff8b9
1//===-- SparcV8TargetMachine.cpp - Define TargetMachine for SparcV8 -------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// 11//===----------------------------------------------------------------------===// 12 13#include "SparcV8TargetMachine.h" 14#include "SparcV8.h" 15#include "llvm/Assembly/PrintModulePass.h" 16#include "llvm/Module.h" 17#include "llvm/PassManager.h" 18#include "llvm/CodeGen/MachineFunction.h" 19#include "llvm/CodeGen/Passes.h" 20#include "llvm/Target/TargetOptions.h" 21#include "llvm/Target/TargetMachineRegistry.h" 22#include "llvm/Transforms/Scalar.h" 23#include <iostream> 24using namespace llvm; 25 26namespace { 27 // Register the target. 28 RegisterTarget<SparcV8TargetMachine> X("sparcv8"," SPARC V8 (experimental)"); 29} 30 31/// SparcV8TargetMachine ctor - Create an ILP32 architecture model 32/// 33SparcV8TargetMachine::SparcV8TargetMachine(const Module &M, 34 IntrinsicLowering *IL) 35 : TargetMachine("SparcV8", IL, false, 4, 4), 36 FrameInfo(TargetFrameInfo::StackGrowsDown, 8, 0), JITInfo(*this) { 37} 38 39unsigned SparcV8TargetMachine::getJITMatchQuality() { 40 return 0; // No JIT yet. 41} 42 43unsigned SparcV8TargetMachine::getModuleMatchQuality(const Module &M) { 44 std::string TT = M.getTargetTriple(); 45 if (TT.size() >= 6 && std::string(TT.begin(), TT.begin()+6) == "sparc-") 46 return 20; 47 48 if (M.getEndianness() == Module::BigEndian && 49 M.getPointerSize() == Module::Pointer32) 50#ifdef __sparc__ 51 return 20; // BE/32 ==> Prefer sparcv8 on sparc 52#else 53 return 5; // BE/32 ==> Prefer ppc elsewhere 54#endif 55 else if (M.getEndianness() != Module::AnyEndianness || 56 M.getPointerSize() != Module::AnyPointerSize) 57 return 0; // Match for some other target 58 59 return getJITMatchQuality()/2; 60} 61 62/// addPassesToEmitAssembly - Add passes to the specified pass manager 63/// to implement a static compiler for this target. 64/// 65bool SparcV8TargetMachine::addPassesToEmitAssembly(PassManager &PM, 66 std::ostream &Out) { 67 // FIXME: Implement efficient support for garbage collection intrinsics. 68 PM.add(createLowerGCPass()); 69 70 // Replace malloc and free instructions with library calls. 71 PM.add(createLowerAllocationsPass()); 72 73 // FIXME: implement the switch instruction in the instruction selector. 74 PM.add(createLowerSwitchPass()); 75 76 // FIXME: implement the invoke/unwind instructions! 77 PM.add(createLowerInvokePass()); 78 79 PM.add(createLowerConstantExpressionsPass()); 80 81 // Make sure that no unreachable blocks are instruction selected. 82 PM.add(createUnreachableBlockEliminationPass()); 83 84 // FIXME: implement the select instruction in the instruction selector. 85 PM.add(createLowerSelectPass()); 86 87 // Print LLVM code input to instruction selector: 88 if (PrintMachineCode) 89 PM.add(new PrintFunctionPass()); 90 91 PM.add(createSparcV8SimpleInstructionSelector(*this)); 92 93 // Print machine instructions as they were initially generated. 94 if (PrintMachineCode) 95 PM.add(createMachineFunctionPrinterPass(&std::cerr)); 96 97 PM.add(createRegisterAllocator()); 98 PM.add(createPrologEpilogCodeInserter()); 99 100 // Print machine instructions after register allocation and prolog/epilog 101 // insertion. 102 if (PrintMachineCode) 103 PM.add(createMachineFunctionPrinterPass(&std::cerr)); 104 105 PM.add(createSparcV8FPMoverPass(*this)); 106 PM.add(createSparcV8DelaySlotFillerPass(*this)); 107 108 // Print machine instructions after filling delay slots. 109 if (PrintMachineCode) 110 PM.add(createMachineFunctionPrinterPass(&std::cerr)); 111 112 // Output assembly language. 113 PM.add(createSparcV8CodePrinterPass(Out, *this)); 114 115 // Delete the MachineInstrs we generated, since they're no longer needed. 116 PM.add(createMachineCodeDeleter()); 117 return false; 118} 119 120/// addPassesToJITCompile - Add passes to the specified pass manager to 121/// implement a fast dynamic compiler for this target. 122/// 123void SparcV8JITInfo::addPassesToJITCompile(FunctionPassManager &PM) { 124 // FIXME: Implement efficient support for garbage collection intrinsics. 125 PM.add(createLowerGCPass()); 126 127 // Replace malloc and free instructions with library calls. 128 PM.add(createLowerAllocationsPass()); 129 130 // FIXME: implement the switch instruction in the instruction selector. 131 PM.add(createLowerSwitchPass()); 132 133 // FIXME: implement the invoke/unwind instructions! 134 PM.add(createLowerInvokePass()); 135 136 PM.add(createLowerConstantExpressionsPass()); 137 138 // Make sure that no unreachable blocks are instruction selected. 139 PM.add(createUnreachableBlockEliminationPass()); 140 141 // FIXME: implement the select instruction in the instruction selector. 142 PM.add(createLowerSelectPass()); 143 144 // Print LLVM code input to instruction selector: 145 if (PrintMachineCode) 146 PM.add(new PrintFunctionPass()); 147 148 PM.add(createSparcV8SimpleInstructionSelector(TM)); 149 150 // Print machine instructions as they were initially generated. 151 if (PrintMachineCode) 152 PM.add(createMachineFunctionPrinterPass(&std::cerr)); 153 154 PM.add(createRegisterAllocator()); 155 PM.add(createPrologEpilogCodeInserter()); 156 157 // Print machine instructions after register allocation and prolog/epilog 158 // insertion. 159 if (PrintMachineCode) 160 PM.add(createMachineFunctionPrinterPass(&std::cerr)); 161 162 PM.add(createSparcV8FPMoverPass(TM)); 163 PM.add(createSparcV8DelaySlotFillerPass(TM)); 164 165 // Print machine instructions after filling delay slots. 166 if (PrintMachineCode) 167 PM.add(createMachineFunctionPrinterPass(&std::cerr)); 168} 169