SystemZMCCodeEmitter.cpp revision 36b56886974eae4f9c5ebc96befd3e7bfe5de338 
1//===-- SystemZMCCodeEmitter.cpp - Convert SystemZ code to machine code ---===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the SystemZMCCodeEmitter class.
11//
12//===----------------------------------------------------------------------===//
13
14#define DEBUG_TYPE "mccodeemitter"
15#include "MCTargetDesc/SystemZMCTargetDesc.h"
16#include "MCTargetDesc/SystemZMCFixups.h"
17#include "llvm/MC/MCCodeEmitter.h"
18#include "llvm/MC/MCContext.h"
19#include "llvm/MC/MCExpr.h"
20#include "llvm/MC/MCInstrInfo.h"
21
22using namespace llvm;
23
24namespace {
25class SystemZMCCodeEmitter : public MCCodeEmitter {
26  const MCInstrInfo &MCII;
27  MCContext &Ctx;
28
29public:
30  SystemZMCCodeEmitter(const MCInstrInfo &mcii, MCContext &ctx)
31    : MCII(mcii), Ctx(ctx) {
32  }
33
34  ~SystemZMCCodeEmitter() {}
35
36  // OVerride MCCodeEmitter.
37  void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
38                         SmallVectorImpl<MCFixup> &Fixups,
39                         const MCSubtargetInfo &STI) const override;
40
41private:
42  // Automatically generated by TableGen.
43  uint64_t getBinaryCodeForInstr(const MCInst &MI,
44                                 SmallVectorImpl<MCFixup> &Fixups,
45                                 const MCSubtargetInfo &STI) const;
46
47  // Called by the TableGen code to get the binary encoding of operand
48  // MO in MI.  Fixups is the list of fixups against MI.
49  uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO,
50                             SmallVectorImpl<MCFixup> &Fixups,
51                             const MCSubtargetInfo &STI) const;
52
53  // Called by the TableGen code to get the binary encoding of an address.
54  // The index or length, if any, is encoded first, followed by the base,
55  // followed by the displacement.  In a 20-bit displacement,
56  // the low 12 bits are encoded before the high 8 bits.
57  uint64_t getBDAddr12Encoding(const MCInst &MI, unsigned OpNum,
58                               SmallVectorImpl<MCFixup> &Fixups,
59                               const MCSubtargetInfo &STI) const;
60  uint64_t getBDAddr20Encoding(const MCInst &MI, unsigned OpNum,
61                               SmallVectorImpl<MCFixup> &Fixups,
62                               const MCSubtargetInfo &STI) const;
63  uint64_t getBDXAddr12Encoding(const MCInst &MI, unsigned OpNum,
64                                SmallVectorImpl<MCFixup> &Fixups,
65                                const MCSubtargetInfo &STI) const;
66  uint64_t getBDXAddr20Encoding(const MCInst &MI, unsigned OpNum,
67                                SmallVectorImpl<MCFixup> &Fixups,
68                                const MCSubtargetInfo &STI) const;
69  uint64_t getBDLAddr12Len8Encoding(const MCInst &MI, unsigned OpNum,
70                                    SmallVectorImpl<MCFixup> &Fixups,
71                                    const MCSubtargetInfo &STI) const;
72
73  // Operand OpNum of MI needs a PC-relative fixup of kind Kind at
74  // Offset bytes from the start of MI.  Add the fixup to Fixups
75  // and return the in-place addend, which since we're a RELA target
76  // is always 0.
77  uint64_t getPCRelEncoding(const MCInst &MI, unsigned OpNum,
78                            SmallVectorImpl<MCFixup> &Fixups,
79                            unsigned Kind, int64_t Offset) const;
80
81  uint64_t getPC16DBLEncoding(const MCInst &MI, unsigned OpNum,
82                              SmallVectorImpl<MCFixup> &Fixups,
83                              const MCSubtargetInfo &STI) const {
84    return getPCRelEncoding(MI, OpNum, Fixups, SystemZ::FK_390_PC16DBL, 2);
85  }
86  uint64_t getPC32DBLEncoding(const MCInst &MI, unsigned OpNum,
87                              SmallVectorImpl<MCFixup> &Fixups,
88                              const MCSubtargetInfo &STI) const {
89    return getPCRelEncoding(MI, OpNum, Fixups, SystemZ::FK_390_PC32DBL, 2);
90  }
91};
92} // end anonymous namespace
93
94MCCodeEmitter *llvm::createSystemZMCCodeEmitter(const MCInstrInfo &MCII,
95                                                const MCRegisterInfo &MRI,
96                                                const MCSubtargetInfo &MCSTI,
97                                                MCContext &Ctx) {
98  return new SystemZMCCodeEmitter(MCII, Ctx);
99}
100
101void SystemZMCCodeEmitter::
102EncodeInstruction(const MCInst &MI, raw_ostream &OS,
103                  SmallVectorImpl<MCFixup> &Fixups,
104                  const MCSubtargetInfo &STI) const {
105  uint64_t Bits = getBinaryCodeForInstr(MI, Fixups, STI);
106  unsigned Size = MCII.get(MI.getOpcode()).getSize();
107  // Big-endian insertion of Size bytes.
108  unsigned ShiftValue = (Size * 8) - 8;
109  for (unsigned I = 0; I != Size; ++I) {
110    OS << uint8_t(Bits >> ShiftValue);
111    ShiftValue -= 8;
112  }
113}
114
115uint64_t SystemZMCCodeEmitter::
116getMachineOpValue(const MCInst &MI, const MCOperand &MO,
117                  SmallVectorImpl<MCFixup> &Fixups,
118                  const MCSubtargetInfo &STI) const {
119  if (MO.isReg())
120    return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg());
121  if (MO.isImm())
122    return static_cast<uint64_t>(MO.getImm());
123  llvm_unreachable("Unexpected operand type!");
124}
125
126uint64_t SystemZMCCodeEmitter::
127getBDAddr12Encoding(const MCInst &MI, unsigned OpNum,
128                    SmallVectorImpl<MCFixup> &Fixups,
129                    const MCSubtargetInfo &STI) const {
130  uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups, STI);
131  uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups, STI);
132  assert(isUInt<4>(Base) && isUInt<12>(Disp));
133  return (Base << 12) | Disp;
134}
135
136uint64_t SystemZMCCodeEmitter::
137getBDAddr20Encoding(const MCInst &MI, unsigned OpNum,
138                    SmallVectorImpl<MCFixup> &Fixups,
139                    const MCSubtargetInfo &STI) const {
140  uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups, STI);
141  uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups, STI);
142  assert(isUInt<4>(Base) && isInt<20>(Disp));
143  return (Base << 20) | ((Disp & 0xfff) << 8) | ((Disp & 0xff000) >> 12);
144}
145
146uint64_t SystemZMCCodeEmitter::
147getBDXAddr12Encoding(const MCInst &MI, unsigned OpNum,
148                     SmallVectorImpl<MCFixup> &Fixups,
149                     const MCSubtargetInfo &STI) const {
150  uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups, STI);
151  uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups, STI);
152  uint64_t Index = getMachineOpValue(MI, MI.getOperand(OpNum + 2), Fixups, STI);
153  assert(isUInt<4>(Base) && isUInt<12>(Disp) && isUInt<4>(Index));
154  return (Index << 16) | (Base << 12) | Disp;
155}
156
157uint64_t SystemZMCCodeEmitter::
158getBDXAddr20Encoding(const MCInst &MI, unsigned OpNum,
159                     SmallVectorImpl<MCFixup> &Fixups,
160                     const MCSubtargetInfo &STI) const {
161  uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups, STI);
162  uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups, STI);
163  uint64_t Index = getMachineOpValue(MI, MI.getOperand(OpNum + 2), Fixups, STI);
164  assert(isUInt<4>(Base) && isInt<20>(Disp) && isUInt<4>(Index));
165  return (Index << 24) | (Base << 20) | ((Disp & 0xfff) << 8)
166    | ((Disp & 0xff000) >> 12);
167}
168
169uint64_t SystemZMCCodeEmitter::
170getBDLAddr12Len8Encoding(const MCInst &MI, unsigned OpNum,
171                         SmallVectorImpl<MCFixup> &Fixups,
172                         const MCSubtargetInfo &STI) const {
173  uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups, STI);
174  uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups, STI);
175  uint64_t Len  = getMachineOpValue(MI, MI.getOperand(OpNum + 2), Fixups, STI) - 1;
176  assert(isUInt<4>(Base) && isUInt<12>(Disp) && isUInt<8>(Len));
177  return (Len << 16) | (Base << 12) | Disp;
178}
179
180uint64_t
181SystemZMCCodeEmitter::getPCRelEncoding(const MCInst &MI, unsigned OpNum,
182                                       SmallVectorImpl<MCFixup> &Fixups,
183                                       unsigned Kind, int64_t Offset) const {
184  const MCOperand &MO = MI.getOperand(OpNum);
185  const MCExpr *Expr;
186  if (MO.isImm())
187    Expr = MCConstantExpr::Create(MO.getImm() + Offset, Ctx);
188  else {
189    Expr = MO.getExpr();
190    if (Offset) {
191      // The operand value is relative to the start of MI, but the fixup
192      // is relative to the operand field itself, which is Offset bytes
193      // into MI.  Add Offset to the relocation value to cancel out
194      // this difference.
195      const MCExpr *OffsetExpr = MCConstantExpr::Create(Offset, Ctx);
196      Expr = MCBinaryExpr::CreateAdd(Expr, OffsetExpr, Ctx);
197    }
198  }
199  Fixups.push_back(MCFixup::Create(Offset, Expr, (MCFixupKind)Kind));
200  return 0;
201}
202
203#include "SystemZGenMCCodeEmitter.inc"
204