1//===-- SystemZISelLowering.h - SystemZ DAG lowering interface --*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the interfaces that SystemZ uses to lower LLVM code into a
11// selection DAG.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef LLVM_TARGET_SystemZ_ISELLOWERING_H
16#define LLVM_TARGET_SystemZ_ISELLOWERING_H
17
18#include "SystemZ.h"
19#include "llvm/CodeGen/MachineBasicBlock.h"
20#include "llvm/CodeGen/SelectionDAG.h"
21#include "llvm/Target/TargetLowering.h"
22
23namespace llvm {
24namespace SystemZISD {
25enum {
26  FIRST_NUMBER = ISD::BUILTIN_OP_END,
27
28  // Return with a flag operand.  Operand 0 is the chain operand.
29  RET_FLAG,
30
31  // Calls a function.  Operand 0 is the chain operand and operand 1
32  // is the target address.  The arguments start at operand 2.
33  // There is an optional glue operand at the end.
34  CALL,
35  SIBCALL,
36
37  // Wraps a TargetGlobalAddress that should be loaded using PC-relative
38  // accesses (LARL).  Operand 0 is the address.
39  PCREL_WRAPPER,
40
41  // Used in cases where an offset is applied to a TargetGlobalAddress.
42  // Operand 0 is the full TargetGlobalAddress and operand 1 is a
43  // PCREL_WRAPPER for an anchor point.  This is used so that we can
44  // cheaply refer to either the full address or the anchor point
45  // as a register base.
46  PCREL_OFFSET,
47
48  // Integer absolute.
49  IABS,
50
51  // Integer comparisons.  There are three operands: the two values
52  // to compare, and an integer of type SystemZICMP.
53  ICMP,
54
55  // Floating-point comparisons.  The two operands are the values to compare.
56  FCMP,
57
58  // Test under mask.  The first operand is ANDed with the second operand
59  // and the condition codes are set on the result.  The third operand is
60  // a boolean that is true if the condition codes need to distinguish
61  // between CCMASK_TM_MIXED_MSB_0 and CCMASK_TM_MIXED_MSB_1 (which the
62  // register forms do but the memory forms don't).
63  TM,
64
65  // Branches if a condition is true.  Operand 0 is the chain operand;
66  // operand 1 is the 4-bit condition-code mask, with bit N in
67  // big-endian order meaning "branch if CC=N"; operand 2 is the
68  // target block and operand 3 is the flag operand.
69  BR_CCMASK,
70
71  // Selects between operand 0 and operand 1.  Operand 2 is the
72  // mask of condition-code values for which operand 0 should be
73  // chosen over operand 1; it has the same form as BR_CCMASK.
74  // Operand 3 is the flag operand.
75  SELECT_CCMASK,
76
77  // Evaluates to the gap between the stack pointer and the
78  // base of the dynamically-allocatable area.
79  ADJDYNALLOC,
80
81  // Extracts the value of a 32-bit access register.  Operand 0 is
82  // the number of the register.
83  EXTRACT_ACCESS,
84
85  // Wrappers around the ISD opcodes of the same name.  The output and
86  // first input operands are GR128s.  The trailing numbers are the
87  // widths of the second operand in bits.
88  UMUL_LOHI64,
89  SDIVREM32,
90  SDIVREM64,
91  UDIVREM32,
92  UDIVREM64,
93
94  // Use a series of MVCs to copy bytes from one memory location to another.
95  // The operands are:
96  // - the target address
97  // - the source address
98  // - the constant length
99  //
100  // This isn't a memory opcode because we'd need to attach two
101  // MachineMemOperands rather than one.
102  MVC,
103
104  // Like MVC, but implemented as a loop that handles X*256 bytes
105  // followed by straight-line code to handle the rest (if any).
106  // The value of X is passed as an additional operand.
107  MVC_LOOP,
108
109  // Similar to MVC and MVC_LOOP, but for logic operations (AND, OR, XOR).
110  NC,
111  NC_LOOP,
112  OC,
113  OC_LOOP,
114  XC,
115  XC_LOOP,
116
117  // Use CLC to compare two blocks of memory, with the same comments
118  // as for MVC and MVC_LOOP.
119  CLC,
120  CLC_LOOP,
121
122  // Use an MVST-based sequence to implement stpcpy().
123  STPCPY,
124
125  // Use a CLST-based sequence to implement strcmp().  The two input operands
126  // are the addresses of the strings to compare.
127  STRCMP,
128
129  // Use an SRST-based sequence to search a block of memory.  The first
130  // operand is the end address, the second is the start, and the third
131  // is the character to search for.  CC is set to 1 on success and 2
132  // on failure.
133  SEARCH_STRING,
134
135  // Store the CC value in bits 29 and 28 of an integer.
136  IPM,
137
138  // Perform a serialization operation.  (BCR 15,0 or BCR 14,0.)
139  SERIALIZE,
140
141  // Wrappers around the inner loop of an 8- or 16-bit ATOMIC_SWAP or
142  // ATOMIC_LOAD_<op>.
143  //
144  // Operand 0: the address of the containing 32-bit-aligned field
145  // Operand 1: the second operand of <op>, in the high bits of an i32
146  //            for everything except ATOMIC_SWAPW
147  // Operand 2: how many bits to rotate the i32 left to bring the first
148  //            operand into the high bits
149  // Operand 3: the negative of operand 2, for rotating the other way
150  // Operand 4: the width of the field in bits (8 or 16)
151  ATOMIC_SWAPW = ISD::FIRST_TARGET_MEMORY_OPCODE,
152  ATOMIC_LOADW_ADD,
153  ATOMIC_LOADW_SUB,
154  ATOMIC_LOADW_AND,
155  ATOMIC_LOADW_OR,
156  ATOMIC_LOADW_XOR,
157  ATOMIC_LOADW_NAND,
158  ATOMIC_LOADW_MIN,
159  ATOMIC_LOADW_MAX,
160  ATOMIC_LOADW_UMIN,
161  ATOMIC_LOADW_UMAX,
162
163  // A wrapper around the inner loop of an ATOMIC_CMP_SWAP.
164  //
165  // Operand 0: the address of the containing 32-bit-aligned field
166  // Operand 1: the compare value, in the low bits of an i32
167  // Operand 2: the swap value, in the low bits of an i32
168  // Operand 3: how many bits to rotate the i32 left to bring the first
169  //            operand into the high bits
170  // Operand 4: the negative of operand 2, for rotating the other way
171  // Operand 5: the width of the field in bits (8 or 16)
172  ATOMIC_CMP_SWAPW,
173
174  // Prefetch from the second operand using the 4-bit control code in
175  // the first operand.  The code is 1 for a load prefetch and 2 for
176  // a store prefetch.
177  PREFETCH
178};
179
180// Return true if OPCODE is some kind of PC-relative address.
181inline bool isPCREL(unsigned Opcode) {
182  return Opcode == PCREL_WRAPPER || Opcode == PCREL_OFFSET;
183}
184} // end namespace SystemZISD
185
186namespace SystemZICMP {
187// Describes whether an integer comparison needs to be signed or unsigned,
188// or whether either type is OK.
189enum {
190  Any,
191  UnsignedOnly,
192  SignedOnly
193};
194} // end namespace SystemZICMP
195
196class SystemZSubtarget;
197class SystemZTargetMachine;
198
199class SystemZTargetLowering : public TargetLowering {
200public:
201  explicit SystemZTargetLowering(const TargetMachine &TM);
202
203  // Override TargetLowering.
204  MVT getScalarShiftAmountTy(EVT LHSTy) const override {
205    return MVT::i32;
206  }
207  EVT getSetCCResultType(LLVMContext &, EVT) const override;
208  bool isFMAFasterThanFMulAndFAdd(EVT VT) const override;
209  bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
210  bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const override;
211  bool allowsUnalignedMemoryAccesses(EVT VT, unsigned AS,
212                                     bool *Fast) const override;
213  bool isTruncateFree(Type *, Type *) const override;
214  bool isTruncateFree(EVT, EVT) const override;
215  const char *getTargetNodeName(unsigned Opcode) const override;
216  std::pair<unsigned, const TargetRegisterClass *>
217    getRegForInlineAsmConstraint(const std::string &Constraint,
218                                 MVT VT) const override;
219  TargetLowering::ConstraintType
220    getConstraintType(const std::string &Constraint) const override;
221  TargetLowering::ConstraintWeight
222    getSingleConstraintMatchWeight(AsmOperandInfo &info,
223                                   const char *constraint) const override;
224  void LowerAsmOperandForConstraint(SDValue Op,
225                                    std::string &Constraint,
226                                    std::vector<SDValue> &Ops,
227                                    SelectionDAG &DAG) const override;
228  MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI,
229                                                 MachineBasicBlock *BB) const
230    override;
231  SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
232  bool allowTruncateForTailCall(Type *, Type *) const override;
233  bool mayBeEmittedAsTailCall(CallInst *CI) const override;
234  SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
235                               bool isVarArg,
236                               const SmallVectorImpl<ISD::InputArg> &Ins,
237                               SDLoc DL, SelectionDAG &DAG,
238                               SmallVectorImpl<SDValue> &InVals) const override;
239  SDValue LowerCall(CallLoweringInfo &CLI,
240                    SmallVectorImpl<SDValue> &InVals) const override;
241
242  SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
243                      const SmallVectorImpl<ISD::OutputArg> &Outs,
244                      const SmallVectorImpl<SDValue> &OutVals,
245                      SDLoc DL, SelectionDAG &DAG) const override;
246  SDValue prepareVolatileOrAtomicLoad(SDValue Chain, SDLoc DL,
247                                      SelectionDAG &DAG) const override;
248  SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
249
250private:
251  const SystemZSubtarget &Subtarget;
252
253  // Implement LowerOperation for individual opcodes.
254  SDValue lowerSETCC(SDValue Op, SelectionDAG &DAG) const;
255  SDValue lowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
256  SDValue lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
257  SDValue lowerGlobalAddress(GlobalAddressSDNode *Node,
258                             SelectionDAG &DAG) const;
259  SDValue lowerGlobalTLSAddress(GlobalAddressSDNode *Node,
260                                SelectionDAG &DAG) const;
261  SDValue lowerBlockAddress(BlockAddressSDNode *Node,
262                            SelectionDAG &DAG) const;
263  SDValue lowerJumpTable(JumpTableSDNode *JT, SelectionDAG &DAG) const;
264  SDValue lowerConstantPool(ConstantPoolSDNode *CP, SelectionDAG &DAG) const;
265  SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
266  SDValue lowerVACOPY(SDValue Op, SelectionDAG &DAG) const;
267  SDValue lowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
268  SDValue lowerSMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
269  SDValue lowerUMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
270  SDValue lowerSDIVREM(SDValue Op, SelectionDAG &DAG) const;
271  SDValue lowerUDIVREM(SDValue Op, SelectionDAG &DAG) const;
272  SDValue lowerBITCAST(SDValue Op, SelectionDAG &DAG) const;
273  SDValue lowerOR(SDValue Op, SelectionDAG &DAG) const;
274  SDValue lowerATOMIC_LOAD(SDValue Op, SelectionDAG &DAG) const;
275  SDValue lowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) const;
276  SDValue lowerATOMIC_LOAD_OP(SDValue Op, SelectionDAG &DAG,
277                              unsigned Opcode) const;
278  SDValue lowerATOMIC_LOAD_SUB(SDValue Op, SelectionDAG &DAG) const;
279  SDValue lowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const;
280  SDValue lowerLOAD_SEQUENCE_POINT(SDValue Op, SelectionDAG &DAG) const;
281  SDValue lowerSTACKSAVE(SDValue Op, SelectionDAG &DAG) const;
282  SDValue lowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG) const;
283  SDValue lowerPREFETCH(SDValue Op, SelectionDAG &DAG) const;
284
285  // If the last instruction before MBBI in MBB was some form of COMPARE,
286  // try to replace it with a COMPARE AND BRANCH just before MBBI.
287  // CCMask and Target are the BRC-like operands for the branch.
288  // Return true if the change was made.
289  bool convertPrevCompareToBranch(MachineBasicBlock *MBB,
290                                  MachineBasicBlock::iterator MBBI,
291                                  unsigned CCMask,
292                                  MachineBasicBlock *Target) const;
293
294  // Implement EmitInstrWithCustomInserter for individual operation types.
295  MachineBasicBlock *emitSelect(MachineInstr *MI,
296                                MachineBasicBlock *BB) const;
297  MachineBasicBlock *emitCondStore(MachineInstr *MI,
298                                   MachineBasicBlock *BB,
299                                   unsigned StoreOpcode, unsigned STOCOpcode,
300                                   bool Invert) const;
301  MachineBasicBlock *emitExt128(MachineInstr *MI,
302                                MachineBasicBlock *MBB,
303                                bool ClearEven, unsigned SubReg) const;
304  MachineBasicBlock *emitAtomicLoadBinary(MachineInstr *MI,
305                                          MachineBasicBlock *BB,
306                                          unsigned BinOpcode, unsigned BitSize,
307                                          bool Invert = false) const;
308  MachineBasicBlock *emitAtomicLoadMinMax(MachineInstr *MI,
309                                          MachineBasicBlock *MBB,
310                                          unsigned CompareOpcode,
311                                          unsigned KeepOldMask,
312                                          unsigned BitSize) const;
313  MachineBasicBlock *emitAtomicCmpSwapW(MachineInstr *MI,
314                                        MachineBasicBlock *BB) const;
315  MachineBasicBlock *emitMemMemWrapper(MachineInstr *MI,
316                                       MachineBasicBlock *BB,
317                                       unsigned Opcode) const;
318  MachineBasicBlock *emitStringWrapper(MachineInstr *MI,
319                                       MachineBasicBlock *BB,
320                                       unsigned Opcode) const;
321};
322} // end namespace llvm
323
324#endif // LLVM_TARGET_SystemZ_ISELLOWERING_H
325